__raw_writel(MICRON_V_ACTIMB_200_2, SDRC_ACTIM_CTRLB_1);
__raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_0);
__raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_1);
+
+ /* reprogram CORE DPLL to 400MHz */
+ sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
+ wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
+ sr32(CM_CLKSEL1_PLL, 16, 11, 400); /* Set M */
+ sr32(CM_CLKSEL1_PLL, 8, 7, N_13); /* Set N */
+ sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
+ wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
} else {
__raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
__raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
/* MPU DPLL (unlocked already) */
+ m = (cpu_family == CPU_OMAP36XX) ? 600 : 500;
sr32(CM_CLKSEL2_PLL_MPU, 0, 5, 0x01); /* Set M2 */
- sr32(CM_CLKSEL1_PLL_MPU, 8, 11, 500); /* Set M */
+ sr32(CM_CLKSEL1_PLL_MPU, 8, 11, m); /* Set M */
sr32(CM_CLKSEL1_PLL_MPU, 0, 7, 0x0C); /* Set N */
sr32(CM_CLKEN_PLL_MPU, 4, 4, 0x03); /* FREQSEL */
sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */