OMAP4: Select DPLL PER Clock as source for SGX FCLK

OMAP4: Select DPLL PER Clock as source for SGX FCLK

The correct frequency for SGX is 307.2 Mhz. If DPLL_PER
is set 1536 Mhz, There is no need to change dividers, just
parent clock need to change. And DPLL PER is set at 1536.

Signed-off-by: Rajeev Kulkarni <rajeevk@ti.com>
Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com>
Signed-off-by: Sebastien Jan <s-jan@ti.com>
Signed-off-by: Anand Gadiyar <gadiyar@ti.com>