3 * Texas Instruments <www.ti.com>
4 * Richard Woodruff <r-woodruff2@ti.com>
6 * X-Loader Configuation settings for the Pandora board.
8 * Derived from /include/configs/omap3evm.h
9 * John Willis <source@distant-earth.com>
10 * GraÅžvydas Ignotas <notasas@gmail.com>
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 /* serial printf facility takes about 3.5K */
38 * High Level Configuration Options
40 #define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
41 #define CONFIG_OMAP 1 /* in a TI OMAP core */
42 #define CONFIG_OMAP34XX 1 /* which is a 34XX */
43 #define CONFIG_OMAP3430 1 /* which is in a 3430 */
44 #define CONFIG_OMAP3_PANDORA 1 /* working with a Pandora */
46 /* Enable the below macro if MMC boot support is required */
51 /* Enable I2C stuff */
52 /* I2C to power serial shifter */
54 #define CFG_I2C_SPEED 100000
55 #define CFG_I2C_SLAVE 1
57 #define CFG_I2C_BUS_SELECT 1
58 #define CONFIG_DRIVER_OMAP34XX_I2C 1
60 #include <asm/arch/cpu.h> /* get chip and board defs */
63 #define V_OSCK 26000000 /* Clock output from T2 */
65 #if (V_OSCK > 19200000)
66 #define V_SCLK (V_OSCK >> 1)
71 #define PRCM_CLK_CFG2_332MHZ 1 /* VDD2=1.15v - 166MHz DDR */
72 #define PRCM_PCLK_OPP2 1 /* ARM=381MHz - VDD1=1.20v */
75 #define CFG_3430SDRAM_DDR 1
77 /* The actual register values are defined in u-boot- mem.h */
78 /* SDRAM Bank Allocation method */
81 #define NAND_BASE_ADR NAND_BASE
83 #define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M
88 #define CFG_NS16550_SERIAL
89 #define CFG_NS16550_REG_SIZE -4
90 #define CFG_NS16550_CLK 48000000
91 #define CFG_NS16550_COM3 OMAP34XX_UART3
94 * select serial console configuration
96 #define CONFIG_SERIAL1 3 /* UART3 for Serial, Thanks */
97 #define CONFIG_CONS_INDEX 3
99 #define CONFIG_BAUDRATE 115200
100 #define CFG_PBSIZE 256
102 #endif /* CFG_PRINTF */
105 * Miscellaneous configurable options
107 #define CFG_LOADADDR 0x80008000
109 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
111 /*-----------------------------------------------------------------------
114 * The stack sizes are set up in start.S using the settings below
116 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
118 /*-----------------------------------------------------------------------
122 #define CFG_NAND_K9F1G08R0A /* Micron 16-bit 256MB chip large page NAND chip */
125 /* NAND is partitioned:
126 * 0x00000000 - 0x0007FFFF Booting Image
127 * 0x00080000 - 0x0025FFFF U-Boot Image
128 * 0x00260000 - 0x0027FFFF U-Boot Env Data (X-loader doesn't care)
129 * 0x00280000 - ... depends on application
131 #define NAND_UBOOT_START 0x0080000 /* Leaving first 4 blocks for x-load */
132 #define NAND_UBOOT_END 0x0160000 /* Only read part for faster boot */
133 #define NAND_BLOCK_SIZE 0x20000
135 #define GPMC_CONFIG (OMAP34XX_GPMC_BASE+0x50)
136 #define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE+0x7C)
137 #define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE+0x80)
138 #define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE+0x84)
141 #define WRITE_NAND_COMMAND(d, adr) \
142 do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d; } while (0)
143 #define WRITE_NAND_ADDRESS(d, adr) \
144 do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d; } while (0)
145 #define WRITE_NAND(d, adr) \
146 do {*(volatile u16 *)GPMC_NAND_DATA_0 = d; } while (0)
147 #define READ_NAND(adr) \
148 (*(volatile u16 *)GPMC_NAND_DATA_0)
149 #define NAND_WAIT_READY()
150 #define NAND_WP_OFF() \
151 do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0)
152 #define NAND_WP_ON() \
153 do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0)
155 #else /* to support 8-bit NAND devices */
156 #define WRITE_NAND_COMMAND(d, adr) \
157 do {*(volatile u8 *)GPMC_NAND_COMMAND_0 = d; } while (0)
158 #define WRITE_NAND_ADDRESS(d, adr) \
159 do {*(volatile u8 *)GPMC_NAND_ADDRESS_0 = d; } while (0)
160 #define WRITE_NAND(d, adr) \
161 do {*(volatile u8 *)GPMC_NAND_DATA_0 = d; } while (0)
162 #define READ_NAND(adr) \
163 (*(volatile u8 *)GPMC_NAND_DATA_0);
164 #define NAND_WAIT_READY()
165 #define NAND_WP_OFF() \
166 do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0)
167 #define NAND_WP_ON() \
168 do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0)
172 #define NAND_CTL_CLRALE(adr)
173 #define NAND_CTL_SETALE(adr)
174 #define NAND_CTL_CLRCLE(adr)
175 #define NAND_CTL_SETCLE(adr)
176 #define NAND_DISABLE_CE()
177 #define NAND_ENABLE_CE()
179 #endif /* __CONFIG_H */