4 * Jian Zhang <jzhang@ti.com>, Kshitij Gupta <kshitij@ti.com>
5 * X-Loader Configuation settings for the TI OMAP H3 board.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 /* exactly uncomment one */
30 #define CFG_BOOT_CS0 /* ROM code -> signed X-Loader in NNAD */
31 //#define CFG_BOOT_CS3 /* unsigned X-loader in NOR for development */
33 /* serial printf facility takes about 3.5K */
37 /* uncomment it if you need timer based udelay(). it takes about 250 bytes */
41 * High Level Configuration Options
44 #define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
45 #define CONFIG_OMAP 1 /* in a TI OMAP core */
46 #define CONFIG_OMAP1710 1 /* which is in a 1710 */
47 #define CONFIG_H3_OMAP1710 1 /* a H3 Board */
49 /* input clock of PLL */
50 /* the OMAP1710 H3 has 12MHz input clock */
51 #define CONFIG_SYS_CLK_FREQ 12000000
57 #define CFG_NS16550_SERIAL
58 #define CFG_NS16550_REG_SIZE (-4)
59 #define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
60 #define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart on helen */
62 #define CONFIG_CONS_INDEX 1
63 #define CONFIG_BAUDRATE 115200
65 #endif /* CFG_PRINTF */
67 #include <configs/omap1510.h>
70 * Miscellaneous configurable options
72 #define CFG_PBSIZE 256
73 #define CFG_LOADADDR 0x11000000
75 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
77 /* The 1710 has 6 timers, they can be driven by the RefClk (12Mhz) or by
78 * DPLL1. This time is further subdivided by a local divisor.
80 #define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */
81 #define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */
82 #define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
84 /*-----------------------------------------------------------------------
87 * The stack sizes are set up in start.S using the settings below
89 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
91 /*-----------------------------------------------------------------------
94 #define CFG_NAND_K9F5616 /* Samsung 16-bit 32MB chip */
97 #define NAND_ADDR 0x0c000000 /* physical address to access nand at CS3*/
99 #define NAND_ADDR 0x0a000000 /* physical address to access nand at CS2B*/
102 /* H3 NAND is partitioned:
103 * 0x0000000 - 0x0010000 Booting Image
104 * 0x0010000 - 0x0050000 U-Boot Image
105 * 0x0050000 - 0x0080000 U-Boot Env Data (X-loader doesn't care)
106 * 0x0080000 - 0x2000000 depends on application
108 #define NAND_UBOOT_START 0x0010000
109 #define NAND_UBOOT_END 0x0050000
110 #define NAND_BLOCK_SIZE 0x4000
112 #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr + 2) = (__u8)(d); } while(0)
113 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr + 4) = (__u8)(d); } while(0)
114 #define WRITE_NAND(d, adr) do{ *(volatile __u16 *)((unsigned long)adr) = (__u16)(d); } while(0)
115 #define READ_NAND(adr) ((volatile __u16)(*(volatile __u16 *)(unsigned long)adr))
117 #define GPIO1_DATAIN 0xfffbe42c
118 #define NAND_WAIT_READY() while(!((*(volatile __u16 *)(GPIO1_DATAIN) & 0x0400) == 0x0400));
120 #define NAND_CTL_CLRALE(adr)
121 #define NAND_CTL_SETALE(adr)
122 #define NAND_CTL_CLRCLE(adr)
123 #define NAND_CTL_SETCLE(adr)
124 #define NAND_DISABLE_CE()
125 #define NAND_ENABLE_CE()
128 #endif /* __CONFIG_H */