drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   3         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   4
   5         Based on the original rt2800pci.c and rt2800usb.c.
   6           Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
   7           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   8           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   9           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  10           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  11           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  12           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  13           <http://rt2x00.serialmonkey.com>
  14
  15         This program is free software; you can redistribute it and/or modify
  16         it under the terms of the GNU General Public License as published by
  17         the Free Software Foundation; either version 2 of the License, or
  18         (at your option) any later version.
  19
  20         This program is distributed in the hope that it will be useful,
  21         but WITHOUT ANY WARRANTY; without even the implied warranty of
  22         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23         GNU General Public License for more details.
  24
  25         You should have received a copy of the GNU General Public License
  26         along with this program; if not, write to the
  27         Free Software Foundation, Inc.,
  28         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  29  */
  30
  31 /*
  32         Module: rt2800lib
  33         Abstract: rt2800 generic device routines.
  34  */
  35
  36 #include <linux/kernel.h>
  37 #include <linux/module.h>
  38
  39 #include "rt2x00.h"
  40 #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
  41 #include "rt2x00usb.h"
  42 #endif
  43 #if defined(CONFIG_RT2X00_LIB_PCI) || defined(CONFIG_RT2X00_LIB_PCI_MODULE)
  44 #include "rt2x00pci.h"
  45 #endif
  46 #include "rt2800lib.h"
  47 #include "rt2800.h"
  48 #include "rt2800usb.h"
  49
  50 MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
  51 MODULE_DESCRIPTION("rt2800 library");
  52 MODULE_LICENSE("GPL");
  53
  54 /*
  55  * Register access.
  56  * All access to the CSR registers will go through the methods
  57  * rt2800_register_read and rt2800_register_write.
  58  * BBP and RF register require indirect register access,
  59  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  60  * These indirect registers work with busy bits,
  61  * and we will try maximal REGISTER_BUSY_COUNT times to access
  62  * the register while taking a REGISTER_BUSY_DELAY us delay
  63  * between each attampt. When the busy bit is still set at that time,
  64  * the access attempt is considered to have failed,
  65  * and we will print an error.
  66  * The _lock versions must be used if you already hold the csr_mutex
  67  */
  68 #define WAIT_FOR_BBP(__dev, __reg) \
  69         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  70 #define WAIT_FOR_RFCSR(__dev, __reg) \
  71         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  72 #define WAIT_FOR_RF(__dev, __reg) \
  73         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  74 #define WAIT_FOR_MCU(__dev, __reg) \
  75         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  76                             H2M_MAILBOX_CSR_OWNER, (__reg))
  77
  78 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  79                              const unsigned int word, const u8 value)
  80 {
  81         u32 reg;
  82
  83         mutex_lock(&rt2x00dev->csr_mutex);
  84
  85         /*
  86          * Wait until the BBP becomes available, afterwards we
  87          * can safely write the new data into the register.
  88          */
  89         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  90                 reg = 0;
  91                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
  92                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
  93                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
  94                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
  95                 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
  96                         rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
  97
  98                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
  99         }
 100
 101         mutex_unlock(&rt2x00dev->csr_mutex);
 102 }
 103
 104 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 105                             const unsigned int word, u8 *value)
 106 {
 107         u32 reg;
 108
 109         mutex_lock(&rt2x00dev->csr_mutex);
 110
 111         /*
 112          * Wait until the BBP becomes available, afterwards we
 113          * can safely write the read request into the register.
 114          * After the data has been written, we wait until hardware
 115          * returns the correct value, if at any time the register
 116          * doesn't become available in time, reg will be 0xffffffff
 117          * which means we return 0xff to the caller.
 118          */
 119         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 120                 reg = 0;
 121                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 122                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 123                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 124                 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
 125                         rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 126
 127                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 128
 129                 WAIT_FOR_BBP(rt2x00dev, &reg);
 130         }
 131
 132         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 133
 134         mutex_unlock(&rt2x00dev->csr_mutex);
 135 }
 136
 137 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 138                                const unsigned int word, const u8 value)
 139 {
 140         u32 reg;
 141
 142         mutex_lock(&rt2x00dev->csr_mutex);
 143
 144         /*
 145          * Wait until the RFCSR becomes available, afterwards we
 146          * can safely write the new data into the register.
 147          */
 148         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 149                 reg = 0;
 150                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 151                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 152                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 153                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 154
 155                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 156         }
 157
 158         mutex_unlock(&rt2x00dev->csr_mutex);
 159 }
 160
 161 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 162                               const unsigned int word, u8 *value)
 163 {
 164         u32 reg;
 165
 166         mutex_lock(&rt2x00dev->csr_mutex);
 167
 168         /*
 169          * Wait until the RFCSR becomes available, afterwards we
 170          * can safely write the read request into the register.
 171          * After the data has been written, we wait until hardware
 172          * returns the correct value, if at any time the register
 173          * doesn't become available in time, reg will be 0xffffffff
 174          * which means we return 0xff to the caller.
 175          */
 176         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 177                 reg = 0;
 178                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 179                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 180                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 181
 182                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 183
 184                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 185         }
 186
 187         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 188
 189         mutex_unlock(&rt2x00dev->csr_mutex);
 190 }
 191
 192 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 193                             const unsigned int word, const u32 value)
 194 {
 195         u32 reg;
 196
 197         mutex_lock(&rt2x00dev->csr_mutex);
 198
 199         /*
 200          * Wait until the RF becomes available, afterwards we
 201          * can safely write the new data into the register.
 202          */
 203         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 204                 reg = 0;
 205                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 206                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 207                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 208                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 209
 210                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 211                 rt2x00_rf_write(rt2x00dev, word, value);
 212         }
 213
 214         mutex_unlock(&rt2x00dev->csr_mutex);
 215 }
 216
 217 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 218                         const u8 command, const u8 token,
 219                         const u8 arg0, const u8 arg1)
 220 {
 221         u32 reg;
 222
 223         /*
 224          * SOC devices don't support MCU requests.
 225          */
 226         if (rt2x00_is_soc(rt2x00dev))
 227                 return;
 228
 229         mutex_lock(&rt2x00dev->csr_mutex);
 230
 231         /*
 232          * Wait until the MCU becomes available, afterwards we
 233          * can safely write the new data into the register.
 234          */
 235         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 236                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 237                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 238                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 239                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 240                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 241
 242                 reg = 0;
 243                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 244                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 245         }
 246
 247         mutex_unlock(&rt2x00dev->csr_mutex);
 248 }
 249 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 250
 251 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 252 {
 253         unsigned int i;
 254         u32 reg;
 255
 256         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 257                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 258                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 259                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 260                         return 0;
 261
 262                 msleep(1);
 263         }
 264
 265         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
 266         return -EACCES;
 267 }
 268 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 269
 270 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 271 const struct rt2x00debug rt2800_rt2x00debug = {
 272         .owner  = THIS_MODULE,
 273         .csr    = {
 274                 .read           = rt2800_register_read,
 275                 .write          = rt2800_register_write,
 276                 .flags          = RT2X00DEBUGFS_OFFSET,
 277                 .word_base      = CSR_REG_BASE,
 278                 .word_size      = sizeof(u32),
 279                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 280         },
 281         .eeprom = {
 282                 .read           = rt2x00_eeprom_read,
 283                 .write          = rt2x00_eeprom_write,
 284                 .word_base      = EEPROM_BASE,
 285                 .word_size      = sizeof(u16),
 286                 .word_count     = EEPROM_SIZE / sizeof(u16),
 287         },
 288         .bbp    = {
 289                 .read           = rt2800_bbp_read,
 290                 .write          = rt2800_bbp_write,
 291                 .word_base      = BBP_BASE,
 292                 .word_size      = sizeof(u8),
 293                 .word_count     = BBP_SIZE / sizeof(u8),
 294         },
 295         .rf     = {
 296                 .read           = rt2x00_rf_read,
 297                 .write          = rt2800_rf_write,
 298                 .word_base      = RF_BASE,
 299                 .word_size      = sizeof(u32),
 300                 .word_count     = RF_SIZE / sizeof(u32),
 301         },
 302 };
 303 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
 304 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 305
 306 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 307 {
 308         u32 reg;
 309
 310         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 311         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 312 }
 313 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
 314
 315 #ifdef CONFIG_RT2X00_LIB_LEDS
 316 static void rt2800_brightness_set(struct led_classdev *led_cdev,
 317                                   enum led_brightness brightness)
 318 {
 319         struct rt2x00_led *led =
 320             container_of(led_cdev, struct rt2x00_led, led_dev);
 321         unsigned int enabled = brightness != LED_OFF;
 322         unsigned int bg_mode =
 323             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 324         unsigned int polarity =
 325                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 326                                    EEPROM_FREQ_LED_POLARITY);
 327         unsigned int ledmode =
 328                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 329                                    EEPROM_FREQ_LED_MODE);
 330
 331         if (led->type == LED_TYPE_RADIO) {
 332                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 333                                       enabled ? 0x20 : 0);
 334         } else if (led->type == LED_TYPE_ASSOC) {
 335                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 336                                       enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 337         } else if (led->type == LED_TYPE_QUALITY) {
 338                 /*
 339                  * The brightness is divided into 6 levels (0 - 5),
 340                  * The specs tell us the following levels:
 341                  *      0, 1 ,3, 7, 15, 31
 342                  * to determine the level in a simple way we can simply
 343                  * work with bitshifting:
 344                  *      (1 << level) - 1
 345                  */
 346                 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 347                                       (1 << brightness / (LED_FULL / 6)) - 1,
 348                                       polarity);
 349         }
 350 }
 351
 352 static int rt2800_blink_set(struct led_classdev *led_cdev,
 353                             unsigned long *delay_on, unsigned long *delay_off)
 354 {
 355         struct rt2x00_led *led =
 356             container_of(led_cdev, struct rt2x00_led, led_dev);
 357         u32 reg;
 358
 359         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 360         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 361         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 362         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
 363         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
 364         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
 365         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
 366         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
 367         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 368
 369         return 0;
 370 }
 371
 372 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
 373                      struct rt2x00_led *led, enum led_type type)
 374 {
 375         led->rt2x00dev = rt2x00dev;
 376         led->type = type;
 377         led->led_dev.brightness_set = rt2800_brightness_set;
 378         led->led_dev.blink_set = rt2800_blink_set;
 379         led->flags = LED_INITIALIZED;
 380 }
 381 #endif /* CONFIG_RT2X00_LIB_LEDS */
 382
 383 /*
 384  * Configuration handlers.
 385  */
 386 static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 387                                     struct rt2x00lib_crypto *crypto,
 388                                     struct ieee80211_key_conf *key)
 389 {
 390         struct mac_wcid_entry wcid_entry;
 391         struct mac_iveiv_entry iveiv_entry;
 392         u32 offset;
 393         u32 reg;
 394
 395         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 396
 397         rt2800_register_read(rt2x00dev, offset, &reg);
 398         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 399                            !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 400         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 401                            (crypto->cmd == SET_KEY) * crypto->cipher);
 402         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 403                            (crypto->cmd == SET_KEY) * crypto->bssidx);
 404         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 405         rt2800_register_write(rt2x00dev, offset, reg);
 406
 407         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 408
 409         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 410         if ((crypto->cipher == CIPHER_TKIP) ||
 411             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 412             (crypto->cipher == CIPHER_AES))
 413                 iveiv_entry.iv[3] |= 0x20;
 414         iveiv_entry.iv[3] |= key->keyidx << 6;
 415         rt2800_register_multiwrite(rt2x00dev, offset,
 416                                       &iveiv_entry, sizeof(iveiv_entry));
 417
 418         offset = MAC_WCID_ENTRY(key->hw_key_idx);
 419
 420         memset(&wcid_entry, 0, sizeof(wcid_entry));
 421         if (crypto->cmd == SET_KEY)
 422                 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
 423         rt2800_register_multiwrite(rt2x00dev, offset,
 424                                       &wcid_entry, sizeof(wcid_entry));
 425 }
 426
 427 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
 428                              struct rt2x00lib_crypto *crypto,
 429                              struct ieee80211_key_conf *key)
 430 {
 431         struct hw_key_entry key_entry;
 432         struct rt2x00_field32 field;
 433         u32 offset;
 434         u32 reg;
 435
 436         if (crypto->cmd == SET_KEY) {
 437                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
 438
 439                 memcpy(key_entry.key, crypto->key,
 440                        sizeof(key_entry.key));
 441                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 442                        sizeof(key_entry.tx_mic));
 443                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 444                        sizeof(key_entry.rx_mic));
 445
 446                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
 447                 rt2800_register_multiwrite(rt2x00dev, offset,
 448                                               &key_entry, sizeof(key_entry));
 449         }
 450
 451         /*
 452          * The cipher types are stored over multiple registers
 453          * starting with SHARED_KEY_MODE_BASE each word will have
 454          * 32 bits and contains the cipher types for 2 bssidx each.
 455          * Using the correct defines correctly will cause overhead,
 456          * so just calculate the correct offset.
 457          */
 458         field.bit_offset = 4 * (key->hw_key_idx % 8);
 459         field.bit_mask = 0x7 << field.bit_offset;
 460
 461         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
 462
 463         rt2800_register_read(rt2x00dev, offset, &reg);
 464         rt2x00_set_field32(&reg, field,
 465                            (crypto->cmd == SET_KEY) * crypto->cipher);
 466         rt2800_register_write(rt2x00dev, offset, reg);
 467
 468         /*
 469          * Update WCID information
 470          */
 471         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
 472
 473         return 0;
 474 }
 475 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
 476
 477 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 478                                struct rt2x00lib_crypto *crypto,
 479                                struct ieee80211_key_conf *key)
 480 {
 481         struct hw_key_entry key_entry;
 482         u32 offset;
 483
 484         if (crypto->cmd == SET_KEY) {
 485                 /*
 486                  * 1 pairwise key is possible per AID, this means that the AID
 487                  * equals our hw_key_idx. Make sure the WCID starts _after_ the
 488                  * last possible shared key entry.
 489                  */
 490                 if (crypto->aid > (256 - 32))
 491                         return -ENOSPC;
 492
 493                 key->hw_key_idx = 32 + crypto->aid;
 494
 495                 memcpy(key_entry.key, crypto->key,
 496                        sizeof(key_entry.key));
 497                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 498                        sizeof(key_entry.tx_mic));
 499                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 500                        sizeof(key_entry.rx_mic));
 501
 502                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 503                 rt2800_register_multiwrite(rt2x00dev, offset,
 504                                               &key_entry, sizeof(key_entry));
 505         }
 506
 507         /*
 508          * Update WCID information
 509          */
 510         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
 511
 512         return 0;
 513 }
 514 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
 515
 516 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
 517                           const unsigned int filter_flags)
 518 {
 519         u32 reg;
 520
 521         /*
 522          * Start configuration steps.
 523          * Note that the version error will always be dropped
 524          * and broadcast frames will always be accepted since
 525          * there is no filter for it at this time.
 526          */
 527         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
 528         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
 529                            !(filter_flags & FIF_FCSFAIL));
 530         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
 531                            !(filter_flags & FIF_PLCPFAIL));
 532         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
 533                            !(filter_flags & FIF_PROMISC_IN_BSS));
 534         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
 535         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
 536         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
 537                            !(filter_flags & FIF_ALLMULTI));
 538         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
 539         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
 540         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
 541                            !(filter_flags & FIF_CONTROL));
 542         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
 543                            !(filter_flags & FIF_CONTROL));
 544         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
 545                            !(filter_flags & FIF_CONTROL));
 546         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
 547                            !(filter_flags & FIF_CONTROL));
 548         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
 549                            !(filter_flags & FIF_CONTROL));
 550         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
 551                            !(filter_flags & FIF_PSPOLL));
 552         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
 553         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
 554         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
 555                            !(filter_flags & FIF_CONTROL));
 556         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
 557 }
 558 EXPORT_SYMBOL_GPL(rt2800_config_filter);
 559
 560 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
 561                         struct rt2x00intf_conf *conf, const unsigned int flags)
 562 {
 563         unsigned int beacon_base;
 564         u32 reg;
 565
 566         if (flags & CONFIG_UPDATE_TYPE) {
 567                 /*
 568                  * Clear current synchronisation setup.
 569                  * For the Beacon base registers we only need to clear
 570                  * the first byte since that byte contains the VALID and OWNER
 571                  * bits which (when set to 0) will invalidate the entire beacon.
 572                  */
 573                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 574                 rt2800_register_write(rt2x00dev, beacon_base, 0);
 575
 576                 /*
 577                  * Enable synchronisation.
 578                  */
 579                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 580                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 581                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
 582                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
 583                                    (conf->sync == TSF_SYNC_BEACON));
 584                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 585         }
 586
 587         if (flags & CONFIG_UPDATE_MAC) {
 588                 reg = le32_to_cpu(conf->mac[1]);
 589                 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
 590                 conf->mac[1] = cpu_to_le32(reg);
 591
 592                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
 593                                               conf->mac, sizeof(conf->mac));
 594         }
 595
 596         if (flags & CONFIG_UPDATE_BSSID) {
 597                 reg = le32_to_cpu(conf->bssid[1]);
 598                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
 599                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
 600                 conf->bssid[1] = cpu_to_le32(reg);
 601
 602                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
 603                                               conf->bssid, sizeof(conf->bssid));
 604         }
 605 }
 606 EXPORT_SYMBOL_GPL(rt2800_config_intf);
 607
 608 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
 609 {
 610         u32 reg;
 611
 612         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
 613         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
 614         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
 615
 616         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
 617         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
 618                            !!erp->short_preamble);
 619         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
 620                            !!erp->short_preamble);
 621         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
 622
 623         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
 624         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
 625                            erp->cts_protection ? 2 : 0);
 626         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
 627
 628         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
 629                                  erp->basic_rates);
 630         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
 631
 632         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
 633         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
 634         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
 635         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
 636
 637         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
 638         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
 639         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
 640         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
 641         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
 642         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
 643         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
 644
 645         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 646         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
 647                            erp->beacon_int * 16);
 648         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 649 }
 650 EXPORT_SYMBOL_GPL(rt2800_config_erp);
 651
 652 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
 653 {
 654         u8 r1;
 655         u8 r3;
 656
 657         rt2800_bbp_read(rt2x00dev, 1, &r1);
 658         rt2800_bbp_read(rt2x00dev, 3, &r3);
 659
 660         /*
 661          * Configure the TX antenna.
 662          */
 663         switch ((int)ant->tx) {
 664         case 1:
 665                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
 666                 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
 667                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 668                 break;
 669         case 2:
 670                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
 671                 break;
 672         case 3:
 673                 /* Do nothing */
 674                 break;
 675         }
 676
 677         /*
 678          * Configure the RX antenna.
 679          */
 680         switch ((int)ant->rx) {
 681         case 1:
 682                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 683                 break;
 684         case 2:
 685                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
 686                 break;
 687         case 3:
 688                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
 689                 break;
 690         }
 691
 692         rt2800_bbp_write(rt2x00dev, 3, r3);
 693         rt2800_bbp_write(rt2x00dev, 1, r1);
 694 }
 695 EXPORT_SYMBOL_GPL(rt2800_config_ant);
 696
 697 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 698                                    struct rt2x00lib_conf *libconf)
 699 {
 700         u16 eeprom;
 701         short lna_gain;
 702
 703         if (libconf->rf.channel <= 14) {
 704                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 705                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
 706         } else if (libconf->rf.channel <= 64) {
 707                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 708                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
 709         } else if (libconf->rf.channel <= 128) {
 710                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 711                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
 712         } else {
 713                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 714                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
 715         }
 716
 717         rt2x00dev->lna_gain = lna_gain;
 718 }
 719
 720 static void rt2800_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
 721                                        struct ieee80211_conf *conf,
 722                                        struct rf_channel *rf,
 723                                        struct channel_info *info)
 724 {
 725         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 726
 727         if (rt2x00dev->default_ant.tx == 1)
 728                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
 729
 730         if (rt2x00dev->default_ant.rx == 1) {
 731                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
 732                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 733         } else if (rt2x00dev->default_ant.rx == 2)
 734                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 735
 736         if (rf->channel > 14) {
 737                 /*
 738                  * When TX power is below 0, we should increase it by 7 to
 739                  * make it a positive value (Minumum value is -7).
 740                  * However this means that values between 0 and 7 have
 741                  * double meaning, and we should set a 7DBm boost flag.
 742                  */
 743                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
 744                                    (info->tx_power1 >= 0));
 745
 746                 if (info->tx_power1 < 0)
 747                         info->tx_power1 += 7;
 748
 749                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
 750                                    TXPOWER_A_TO_DEV(info->tx_power1));
 751
 752                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
 753                                    (info->tx_power2 >= 0));
 754
 755                 if (info->tx_power2 < 0)
 756                         info->tx_power2 += 7;
 757
 758                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
 759                                    TXPOWER_A_TO_DEV(info->tx_power2));
 760         } else {
 761                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
 762                                    TXPOWER_G_TO_DEV(info->tx_power1));
 763                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
 764                                    TXPOWER_G_TO_DEV(info->tx_power2));
 765         }
 766
 767         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
 768
 769         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 770         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 771         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 772         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 773
 774         udelay(200);
 775
 776         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 777         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 778         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 779         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 780
 781         udelay(200);
 782
 783         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 784         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 785         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 786         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 787 }
 788
 789 static void rt2800_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
 790                                        struct ieee80211_conf *conf,
 791                                        struct rf_channel *rf,
 792                                        struct channel_info *info)
 793 {
 794         u8 rfcsr;
 795
 796         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
 797         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
 798
 799         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
 800         rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
 801         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
 802
 803         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
 804         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
 805                           TXPOWER_G_TO_DEV(info->tx_power1));
 806         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
 807
 808         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
 809         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
 810         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
 811
 812         rt2800_rfcsr_write(rt2x00dev, 24,
 813                               rt2x00dev->calibration[conf_is_ht40(conf)]);
 814
 815         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
 816         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
 817         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
 818 }
 819
 820 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
 821                                   struct ieee80211_conf *conf,
 822                                   struct rf_channel *rf,
 823                                   struct channel_info *info)
 824 {
 825         u32 reg;
 826         unsigned int tx_pin;
 827         u8 bbp;
 828
 829         if ((rt2x00_rt(rt2x00dev, RT3070) ||
 830              rt2x00_rt(rt2x00dev, RT3090)) &&
 831             (rt2x00_rf(rt2x00dev, RF2020) ||
 832              rt2x00_rf(rt2x00dev, RF3020) ||
 833              rt2x00_rf(rt2x00dev, RF3021) ||
 834              rt2x00_rf(rt2x00dev, RF3022)))
 835                 rt2800_config_channel_rt3x(rt2x00dev, conf, rf, info);
 836         else
 837                 rt2800_config_channel_rt2x(rt2x00dev, conf, rf, info);
 838
 839         /*
 840          * Change BBP settings
 841          */
 842         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 843         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 844         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 845         rt2800_bbp_write(rt2x00dev, 86, 0);
 846
 847         if (rf->channel <= 14) {
 848                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 849                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
 850                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
 851                 } else {
 852                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
 853                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
 854                 }
 855         } else {
 856                 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
 857
 858                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 859                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
 860                 else
 861                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
 862         }
 863
 864         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
 865         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
 866         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
 867         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
 868         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
 869
 870         tx_pin = 0;
 871
 872         /* Turn on unused PA or LNA when not using 1T or 1R */
 873         if (rt2x00dev->default_ant.tx != 1) {
 874                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
 875                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
 876         }
 877
 878         /* Turn on unused PA or LNA when not using 1T or 1R */
 879         if (rt2x00dev->default_ant.rx != 1) {
 880                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
 881                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
 882         }
 883
 884         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
 885         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
 886         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
 887         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
 888         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
 889         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
 890
 891         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 892
 893         rt2800_bbp_read(rt2x00dev, 4, &bbp);
 894         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
 895         rt2800_bbp_write(rt2x00dev, 4, bbp);
 896
 897         rt2800_bbp_read(rt2x00dev, 3, &bbp);
 898         rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
 899         rt2800_bbp_write(rt2x00dev, 3, bbp);
 900
 901         if (rt2x00_rt(rt2x00dev, RT2860) &&
 902             (rt2x00_rev(rt2x00dev) == RT2860C_VERSION)) {
 903                 if (conf_is_ht40(conf)) {
 904                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
 905                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
 906                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
 907                 } else {
 908                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
 909                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
 910                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
 911                 }
 912         }
 913
 914         msleep(1);
 915 }
 916
 917 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
 918                                   const int txpower)
 919 {
 920         u32 reg;
 921         u32 value = TXPOWER_G_TO_DEV(txpower);
 922         u8 r1;
 923
 924         rt2800_bbp_read(rt2x00dev, 1, &r1);
 925         rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
 926         rt2800_bbp_write(rt2x00dev, 1, r1);
 927
 928         rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
 929         rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
 930         rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
 931         rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
 932         rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
 933         rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
 934         rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
 935         rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
 936         rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
 937         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
 938
 939         rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
 940         rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
 941         rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
 942         rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
 943         rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
 944         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
 945         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
 946         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
 947         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
 948         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
 949
 950         rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
 951         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
 952         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
 953         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
 954         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
 955         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
 956         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
 957         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
 958         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
 959         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
 960
 961         rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
 962         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
 963         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
 964         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
 965         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
 966         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
 967         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
 968         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
 969         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
 970         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
 971
 972         rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
 973         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
 974         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
 975         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
 976         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
 977         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
 978 }
 979
 980 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 981                                       struct rt2x00lib_conf *libconf)
 982 {
 983         u32 reg;
 984
 985         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
 986         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
 987                            libconf->conf->short_frame_max_tx_count);
 988         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
 989                            libconf->conf->long_frame_max_tx_count);
 990         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
 991         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
 992         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
 993         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
 994         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
 995 }
 996
 997 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
 998                              struct rt2x00lib_conf *libconf)
 999 {
1000         enum dev_state state =
1001             (libconf->conf->flags & IEEE80211_CONF_PS) ?
1002                 STATE_SLEEP : STATE_AWAKE;
1003         u32 reg;
1004
1005         if (state == STATE_SLEEP) {
1006                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1007
1008                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1009                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1010                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1011                                    libconf->conf->listen_interval - 1);
1012                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1013                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1014
1015                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1016         } else {
1017                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1018
1019                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1020                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1021                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1022                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1023                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1024         }
1025 }
1026
1027 void rt2800_config(struct rt2x00_dev *rt2x00dev,
1028                    struct rt2x00lib_conf *libconf,
1029                    const unsigned int flags)
1030 {
1031         /* Always recalculate LNA gain before changing configuration */
1032         rt2800_config_lna_gain(rt2x00dev, libconf);
1033
1034         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1035                 rt2800_config_channel(rt2x00dev, libconf->conf,
1036                                       &libconf->rf, &libconf->channel);
1037         if (flags & IEEE80211_CONF_CHANGE_POWER)
1038                 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1039         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1040                 rt2800_config_retry_limit(rt2x00dev, libconf);
1041         if (flags & IEEE80211_CONF_CHANGE_PS)
1042                 rt2800_config_ps(rt2x00dev, libconf);
1043 }
1044 EXPORT_SYMBOL_GPL(rt2800_config);
1045
1046 /*
1047  * Link tuning
1048  */
1049 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1050 {
1051         u32 reg;
1052
1053         /*
1054          * Update FCS error count from register.
1055          */
1056         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1057         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1058 }
1059 EXPORT_SYMBOL_GPL(rt2800_link_stats);
1060
1061 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1062 {
1063         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1064                 if (rt2x00_is_usb(rt2x00dev) &&
1065                     rt2x00_rt(rt2x00dev, RT3070) &&
1066                     (rt2x00_rev(rt2x00dev) == RT3070_VERSION))
1067                         return 0x1c + (2 * rt2x00dev->lna_gain);
1068                 else
1069                         return 0x2e + rt2x00dev->lna_gain;
1070         }
1071
1072         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1073                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1074         else
1075                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1076 }
1077
1078 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1079                                   struct link_qual *qual, u8 vgc_level)
1080 {
1081         if (qual->vgc_level != vgc_level) {
1082                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1083                 qual->vgc_level = vgc_level;
1084                 qual->vgc_level_reg = vgc_level;
1085         }
1086 }
1087
1088 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1089 {
1090         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1091 }
1092 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1093
1094 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1095                        const u32 count)
1096 {
1097         if (rt2x00_rt(rt2x00dev, RT2860) &&
1098             (rt2x00_rev(rt2x00dev) == RT2860C_VERSION))
1099                 return;
1100
1101         /*
1102          * When RSSI is better then -80 increase VGC level with 0x10
1103          */
1104         rt2800_set_vgc(rt2x00dev, qual,
1105                        rt2800_get_default_vgc(rt2x00dev) +
1106                        ((qual->rssi > -80) * 0x10));
1107 }
1108 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
1109
1110 /*
1111  * Initialization functions.
1112  */
1113 int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1114 {
1115         u32 reg;
1116         unsigned int i;
1117
1118         if (rt2x00_is_usb(rt2x00dev)) {
1119                 /*
1120                  * Wait until BBP and RF are ready.
1121                  */
1122                 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1123                         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1124                         if (reg && reg != ~0)
1125                                 break;
1126                         msleep(1);
1127                 }
1128
1129                 if (i == REGISTER_BUSY_COUNT) {
1130                         ERROR(rt2x00dev, "Unstable hardware.\n");
1131                         return -EBUSY;
1132                 }
1133
1134                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1135                 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL,
1136                                       reg & ~0x00002000);
1137         } else if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
1138                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1139
1140         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1141         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1142         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1143         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1144
1145         if (rt2x00_is_usb(rt2x00dev)) {
1146                 rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1147 #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
1148                 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1149                                             USB_MODE_RESET, REGISTER_TIMEOUT);
1150 #endif
1151         }
1152
1153         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1154
1155         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1156         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1157         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1158         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1159         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1160         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1161
1162         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1163         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1164         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1165         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1166         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1167         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1168
1169         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1170         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1171
1172         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1173
1174         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1175         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1176         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1177         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1178         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1179         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1180         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1181         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1182
1183         if (rt2x00_is_usb(rt2x00dev) &&
1184             rt2x00_rt(rt2x00dev, RT3070) &&
1185             (rt2x00_rev(rt2x00dev) == RT3070_VERSION)) {
1186                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1187                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1188                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1189         } else {
1190                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1191                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1192         }
1193
1194         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1195         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1196         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1197         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1198         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1199         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1200         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1201         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1202         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1203         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1204
1205         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1206         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1207         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1208         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1209
1210         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1211         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1212         if ((rt2x00_rt(rt2x00dev, RT2872) &&
1213              (rt2x00_rev(rt2x00dev) >= RT2880E_VERSION)) ||
1214             rt2x00_rt(rt2x00dev, RT2880) ||
1215             rt2x00_rt(rt2x00dev, RT2883) ||
1216             rt2x00_rt(rt2x00dev, RT2890) ||
1217             rt2x00_rt(rt2x00dev, RT3052) ||
1218             (rt2x00_rt(rt2x00dev, RT3070) &&
1219              (rt2x00_rev(rt2x00dev) < RT3070_VERSION)))
1220                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1221         else
1222                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1223         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1224         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1225         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1226
1227         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1228
1229         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1230         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1231         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1232         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1233         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1234         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1235         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1236
1237         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1238         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1239         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1240         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1241         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1242         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1243         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1244         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1245         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1246         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1247         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1248
1249         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1250         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1251         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1252         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1253         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1254         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1255         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1256         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1257         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1258         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1259         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1260
1261         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1262         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1263         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1264         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1265         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1266         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1267         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1268         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1269         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1270         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1271         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1272
1273         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1274         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1275         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1276         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1277         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1278         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1279         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1280         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1281         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1282         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1283         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1284
1285         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1286         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1287         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1288         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1289         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1290         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1291         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1292         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1293         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1294         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1295         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1296
1297         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1298         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1299         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1300         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1301         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1302         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1303         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1304         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1305         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1306         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1307         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1308
1309         if (rt2x00_is_usb(rt2x00dev)) {
1310                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1311
1312                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1313                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1314                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1315                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1316                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1317                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1318                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1319                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1320                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1321                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1322                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1323         }
1324
1325         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1326         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1327
1328         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1329         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1330         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1331                            IEEE80211_MAX_RTS_THRESHOLD);
1332         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1333         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1334
1335         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1336         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1337
1338         /*
1339          * ASIC will keep garbage value after boot, clear encryption keys.
1340          */
1341         for (i = 0; i < 4; i++)
1342                 rt2800_register_write(rt2x00dev,
1343                                          SHARED_KEY_MODE_ENTRY(i), 0);
1344
1345         for (i = 0; i < 256; i++) {
1346                 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1347                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1348                                               wcid, sizeof(wcid));
1349
1350                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1351                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1352         }
1353
1354         /*
1355          * Clear all beacons
1356          * For the Beacon base registers we only need to clear
1357          * the first byte since that byte contains the VALID and OWNER
1358          * bits which (when set to 0) will invalidate the entire beacon.
1359          */
1360         rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1361         rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1362         rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1363         rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1364         rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1365         rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1366         rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1367         rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1368
1369         if (rt2x00_is_usb(rt2x00dev)) {
1370                 rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1371                 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1372                 rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg);
1373         }
1374
1375         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1376         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1377         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1378         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1379         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1380         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1381         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1382         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1383         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1384         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1385
1386         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1387         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1388         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1389         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1390         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1391         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1392         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1393         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1394         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1395         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1396
1397         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1398         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1399         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1400         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1401         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1402         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1403         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1404         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1405         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1406         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1407
1408         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1409         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1410         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1411         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1412         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1413         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1414
1415         /*
1416          * We must clear the error counters.
1417          * These registers are cleared on read,
1418          * so we may pass a useless variable to store the value.
1419          */
1420         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1421         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1422         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1423         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1424         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1425         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1426
1427         return 0;
1428 }
1429 EXPORT_SYMBOL_GPL(rt2800_init_registers);
1430
1431 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1432 {
1433         unsigned int i;
1434         u32 reg;
1435
1436         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1437                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1438                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1439                         return 0;
1440
1441                 udelay(REGISTER_BUSY_DELAY);
1442         }
1443
1444         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1445         return -EACCES;
1446 }
1447
1448 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1449 {
1450         unsigned int i;
1451         u8 value;
1452
1453         /*
1454          * BBP was enabled after firmware was loaded,
1455          * but we need to reactivate it now.
1456          */
1457         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1458         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1459         msleep(1);
1460
1461         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1462                 rt2800_bbp_read(rt2x00dev, 0, &value);
1463                 if ((value != 0xff) && (value != 0x00))
1464                         return 0;
1465                 udelay(REGISTER_BUSY_DELAY);
1466         }
1467
1468         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1469         return -EACCES;
1470 }
1471
1472 int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1473 {
1474         unsigned int i;
1475         u16 eeprom;
1476         u8 reg_id;
1477         u8 value;
1478
1479         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
1480                      rt2800_wait_bbp_ready(rt2x00dev)))
1481                 return -EACCES;
1482
1483         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1484         rt2800_bbp_write(rt2x00dev, 66, 0x38);
1485         rt2800_bbp_write(rt2x00dev, 69, 0x12);
1486         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1487         rt2800_bbp_write(rt2x00dev, 73, 0x10);
1488         rt2800_bbp_write(rt2x00dev, 81, 0x37);
1489         rt2800_bbp_write(rt2x00dev, 82, 0x62);
1490         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
1491         rt2800_bbp_write(rt2x00dev, 84, 0x99);
1492         rt2800_bbp_write(rt2x00dev, 86, 0x00);
1493         rt2800_bbp_write(rt2x00dev, 91, 0x04);
1494         rt2800_bbp_write(rt2x00dev, 92, 0x00);
1495         rt2800_bbp_write(rt2x00dev, 103, 0x00);
1496         rt2800_bbp_write(rt2x00dev, 105, 0x05);
1497
1498         if (rt2x00_rt(rt2x00dev, RT2860) &&
1499             (rt2x00_rev(rt2x00dev) == RT2860C_VERSION)) {
1500                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1501                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1502         }
1503
1504         if (rt2x00_rt(rt2x00dev, RT2860) &&
1505             (rt2x00_rev(rt2x00dev) > RT2860D_VERSION))
1506                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1507
1508         if (rt2x00_is_usb(rt2x00dev) &&
1509             rt2x00_rt(rt2x00dev, RT3070) &&
1510             (rt2x00_rev(rt2x00dev) == RT3070_VERSION)) {
1511                 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1512                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1513                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1514         }
1515
1516         if (rt2x00_rt(rt2x00dev, RT3052)) {
1517                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1518                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1519                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
1520         }
1521
1522         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1523                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1524
1525                 if (eeprom != 0xffff && eeprom != 0x0000) {
1526                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1527                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1528                         rt2800_bbp_write(rt2x00dev, reg_id, value);
1529                 }
1530         }
1531
1532         return 0;
1533 }
1534 EXPORT_SYMBOL_GPL(rt2800_init_bbp);
1535
1536 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1537                                 bool bw40, u8 rfcsr24, u8 filter_target)
1538 {
1539         unsigned int i;
1540         u8 bbp;
1541         u8 rfcsr;
1542         u8 passband;
1543         u8 stopband;
1544         u8 overtuned = 0;
1545
1546         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1547
1548         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1549         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1550         rt2800_bbp_write(rt2x00dev, 4, bbp);
1551
1552         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1553         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1554         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1555
1556         /*
1557          * Set power & frequency of passband test tone
1558          */
1559         rt2800_bbp_write(rt2x00dev, 24, 0);
1560
1561         for (i = 0; i < 100; i++) {
1562                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1563                 msleep(1);
1564
1565                 rt2800_bbp_read(rt2x00dev, 55, &passband);
1566                 if (passband)
1567                         break;
1568         }
1569
1570         /*
1571          * Set power & frequency of stopband test tone
1572          */
1573         rt2800_bbp_write(rt2x00dev, 24, 0x06);
1574
1575         for (i = 0; i < 100; i++) {
1576                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1577                 msleep(1);
1578
1579                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
1580
1581                 if ((passband - stopband) <= filter_target) {
1582                         rfcsr24++;
1583                         overtuned += ((passband - stopband) == filter_target);
1584                 } else
1585                         break;
1586
1587                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1588         }
1589
1590         rfcsr24 -= !!overtuned;
1591
1592         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1593         return rfcsr24;
1594 }
1595
1596 int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1597 {
1598         u8 rfcsr;
1599         u8 bbp;
1600
1601         if (rt2x00_is_usb(rt2x00dev) &&
1602             rt2x00_rt(rt2x00dev, RT3070) &&
1603             (rt2x00_rev(rt2x00dev) != RT3070_VERSION))
1604                 return 0;
1605
1606         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) {
1607                 if (!rt2x00_rf(rt2x00dev, RF3020) &&
1608                     !rt2x00_rf(rt2x00dev, RF3021) &&
1609                     !rt2x00_rf(rt2x00dev, RF3022))
1610                         return 0;
1611         }
1612
1613         /*
1614          * Init RF calibration.
1615          */
1616         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1617         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1618         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1619         msleep(1);
1620         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1621         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1622
1623         if (rt2x00_is_usb(rt2x00dev)) {
1624                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1625                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1626                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1627                 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1628                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1629                 rt2800_rfcsr_write(rt2x00dev, 10, 0x71);
1630                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1631                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1632                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1633                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1634                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1635                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1636                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1637                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1638                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1639                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1640                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1641                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1642                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1643                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
1644         } else if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) {
1645                 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
1646                 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
1647                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
1648                 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
1649                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1650                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1651                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1652                 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
1653                 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
1654                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1655                 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
1656                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1657                 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
1658                 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
1659                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1660                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1661                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1662                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1663                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1664                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1665                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1666                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1667                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1668                 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
1669                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1670                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1671                 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
1672                 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
1673                 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
1674                 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
1675         }
1676
1677         /*
1678          * Set RX Filter calibration for 20MHz and 40MHz
1679          */
1680         rt2x00dev->calibration[0] =
1681             rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1682         rt2x00dev->calibration[1] =
1683             rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1684
1685         /*
1686          * Set back to initial state
1687          */
1688         rt2800_bbp_write(rt2x00dev, 24, 0);
1689
1690         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1691         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1692         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1693
1694         /*
1695          * set BBP back to BW20
1696          */
1697         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1698         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1699         rt2800_bbp_write(rt2x00dev, 4, bbp);
1700
1701         return 0;
1702 }
1703 EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
1704
1705 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
1706 {
1707         u32 reg;
1708
1709         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
1710
1711         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
1712 }
1713 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
1714
1715 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
1716 {
1717         u32 reg;
1718
1719         mutex_lock(&rt2x00dev->csr_mutex);
1720
1721         rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
1722         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
1723         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
1724         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
1725         rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
1726
1727         /* Wait until the EEPROM has been loaded */
1728         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
1729
1730         /* Apparently the data is read from end to start */
1731         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
1732                                         (u32 *)&rt2x00dev->eeprom[i]);
1733         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
1734                                         (u32 *)&rt2x00dev->eeprom[i + 2]);
1735         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
1736                                         (u32 *)&rt2x00dev->eeprom[i + 4]);
1737         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
1738                                         (u32 *)&rt2x00dev->eeprom[i + 6]);
1739
1740         mutex_unlock(&rt2x00dev->csr_mutex);
1741 }
1742
1743 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
1744 {
1745         unsigned int i;
1746
1747         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
1748                 rt2800_efuse_read(rt2x00dev, i);
1749 }
1750 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
1751
1752 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1753 {
1754         u16 word;
1755         u8 *mac;
1756         u8 default_lna_gain;
1757
1758         /*
1759          * Start validation of the data that has been read.
1760          */
1761         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1762         if (!is_valid_ether_addr(mac)) {
1763                 random_ether_addr(mac);
1764                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1765         }
1766
1767         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1768         if (word == 0xffff) {
1769                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1770                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
1771                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
1772                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1773                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1774         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
1775                    rt2x00_rt(rt2x00dev, RT2870) ||
1776                    rt2x00_rt(rt2x00dev, RT2872) ||
1777                    rt2x00_rt(rt2x00dev, RT2880) ||
1778                    (rt2x00_rt(rt2x00dev, RT2883) &&
1779                     (rt2x00_rev(rt2x00dev) < RT2883_VERSION))) {
1780                 /*
1781                  * There is a max of 2 RX streams for RT28x0 series
1782                  */
1783                 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
1784                         rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1785                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1786         }
1787
1788         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1789         if (word == 0xffff) {
1790                 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
1791                 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
1792                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1793                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1794                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1795                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
1796                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
1797                 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
1798                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
1799                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
1800                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1801                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1802         }
1803
1804         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1805         if ((word & 0x00ff) == 0x00ff) {
1806                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1807                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
1808                                    LED_MODE_TXRX_ACTIVITY);
1809                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
1810                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1811                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
1812                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
1813                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
1814                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1815         }
1816
1817         /*
1818          * During the LNA validation we are going to use
1819          * lna0 as correct value. Note that EEPROM_LNA
1820          * is never validated.
1821          */
1822         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
1823         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
1824
1825         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
1826         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
1827                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
1828         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
1829                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
1830         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
1831
1832         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
1833         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
1834                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
1835         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
1836             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
1837                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
1838                                    default_lna_gain);
1839         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
1840
1841         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
1842         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
1843                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
1844         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
1845                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
1846         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
1847
1848         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
1849         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
1850                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
1851         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
1852             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
1853                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
1854                                    default_lna_gain);
1855         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
1856
1857         return 0;
1858 }
1859 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
1860
1861 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
1862 {
1863         u32 reg;
1864         u16 value;
1865         u16 eeprom;
1866
1867         /*
1868          * Read EEPROM word for configuration.
1869          */
1870         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1871
1872         /*
1873          * Identify RF chipset.
1874          */
1875         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1876         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1877
1878         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
1879                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
1880
1881         if (!rt2x00_rt(rt2x00dev, RT2860) &&
1882             !rt2x00_rt(rt2x00dev, RT2870) &&
1883             !rt2x00_rt(rt2x00dev, RT2872) &&
1884             !rt2x00_rt(rt2x00dev, RT2880) &&
1885             !rt2x00_rt(rt2x00dev, RT2883) &&
1886             !rt2x00_rt(rt2x00dev, RT2890) &&
1887             !rt2x00_rt(rt2x00dev, RT3052) &&
1888             !rt2x00_rt(rt2x00dev, RT3070) &&
1889             !rt2x00_rt(rt2x00dev, RT3071) &&
1890             !rt2x00_rt(rt2x00dev, RT3090) &&
1891             !rt2x00_rt(rt2x00dev, RT3390) &&
1892             !rt2x00_rt(rt2x00dev, RT3572)) {
1893                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1894                 return -ENODEV;
1895         }
1896
1897         if (!rt2x00_rf(rt2x00dev, RF2820) &&
1898             !rt2x00_rf(rt2x00dev, RF2850) &&
1899             !rt2x00_rf(rt2x00dev, RF2720) &&
1900             !rt2x00_rf(rt2x00dev, RF2750) &&
1901             !rt2x00_rf(rt2x00dev, RF3020) &&
1902             !rt2x00_rf(rt2x00dev, RF2020) &&
1903             !rt2x00_rf(rt2x00dev, RF3021) &&
1904             !rt2x00_rf(rt2x00dev, RF3022) &&
1905             !rt2x00_rf(rt2x00dev, RF3052)) {
1906                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1907                 return -ENODEV;
1908         }
1909
1910         /*
1911          * Identify default antenna configuration.
1912          */
1913         rt2x00dev->default_ant.tx =
1914             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
1915         rt2x00dev->default_ant.rx =
1916             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
1917
1918         /*
1919          * Read frequency offset and RF programming sequence.
1920          */
1921         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1922         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1923
1924         /*
1925          * Read external LNA informations.
1926          */
1927         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1928
1929         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
1930                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1931         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1932                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1933
1934         /*
1935          * Detect if this device has an hardware controlled radio.
1936          */
1937         if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
1938                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1939
1940         /*
1941          * Store led settings, for correct led behaviour.
1942          */
1943 #ifdef CONFIG_RT2X00_LIB_LEDS
1944         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1945         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1946         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
1947
1948         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
1949 #endif /* CONFIG_RT2X00_LIB_LEDS */
1950
1951         return 0;
1952 }
1953 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
1954
1955 /*
1956  * RF value list for rt28x0
1957  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
1958  */
1959 static const struct rf_channel rf_vals[] = {
1960         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
1961         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
1962         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
1963         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
1964         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
1965         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
1966         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
1967         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
1968         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
1969         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
1970         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
1971         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
1972         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
1973         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
1974
1975         /* 802.11 UNI / HyperLan 2 */
1976         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
1977         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
1978         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
1979         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
1980         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
1981         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
1982         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
1983         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
1984         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
1985         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
1986         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
1987         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
1988
1989         /* 802.11 HyperLan 2 */
1990         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
1991         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
1992         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
1993         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
1994         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
1995         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
1996         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
1997         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
1998         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
1999         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2000         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2001         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2002         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2003         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2004         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2005         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2006
2007         /* 802.11 UNII */
2008         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2009         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2010         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2011         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2012         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2013         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2014         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2015         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2016         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2017         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2018         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2019
2020         /* 802.11 Japan */
2021         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2022         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2023         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2024         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2025         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2026         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2027         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2028 };
2029
2030 /*
2031  * RF value list for rt3070
2032  * Supports: 2.4 GHz
2033  */
2034 static const struct rf_channel rf_vals_302x[] = {
2035         {1,  241, 2, 2 },
2036         {2,  241, 2, 7 },
2037         {3,  242, 2, 2 },
2038         {4,  242, 2, 7 },
2039         {5,  243, 2, 2 },
2040         {6,  243, 2, 7 },
2041         {7,  244, 2, 2 },
2042         {8,  244, 2, 7 },
2043         {9,  245, 2, 2 },
2044         {10, 245, 2, 7 },
2045         {11, 246, 2, 2 },
2046         {12, 246, 2, 7 },
2047         {13, 247, 2, 2 },
2048         {14, 248, 2, 4 },
2049 };
2050
2051 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2052 {
2053         struct hw_mode_spec *spec = &rt2x00dev->spec;
2054         struct channel_info *info;
2055         char *tx_power1;
2056         char *tx_power2;
2057         unsigned int i;
2058         u16 eeprom;
2059
2060         /*
2061          * Disable powersaving as default on PCI devices.
2062          */
2063         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
2064                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2065
2066         /*
2067          * Initialize all hw fields.
2068          */
2069         rt2x00dev->hw->flags =
2070             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2071             IEEE80211_HW_SIGNAL_DBM |
2072             IEEE80211_HW_SUPPORTS_PS |
2073             IEEE80211_HW_PS_NULLFUNC_STACK;
2074
2075         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2076         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2077                                 rt2x00_eeprom_addr(rt2x00dev,
2078                                                    EEPROM_MAC_ADDR_0));
2079
2080         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2081
2082         /*
2083          * Initialize hw_mode information.
2084          */
2085         spec->supported_bands = SUPPORT_BAND_2GHZ;
2086         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2087
2088         if (rt2x00_rf(rt2x00dev, RF2820) ||
2089             rt2x00_rf(rt2x00dev, RF2720) ||
2090             rt2x00_rf(rt2x00dev, RF3052)) {
2091                 spec->num_channels = 14;
2092                 spec->channels = rf_vals;
2093         } else if (rt2x00_rf(rt2x00dev, RF2850) || rt2x00_rf(rt2x00dev, RF2750)) {
2094                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2095                 spec->num_channels = ARRAY_SIZE(rf_vals);
2096                 spec->channels = rf_vals;
2097         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
2098                    rt2x00_rf(rt2x00dev, RF2020) ||
2099                    rt2x00_rf(rt2x00dev, RF3021) ||
2100                    rt2x00_rf(rt2x00dev, RF3022)) {
2101                 spec->num_channels = ARRAY_SIZE(rf_vals_302x);
2102                 spec->channels = rf_vals_302x;
2103         }
2104
2105         /*
2106          * Initialize HT information.
2107          */
2108         if (!rt2x00_rf(rt2x00dev, RF2020))
2109                 spec->ht.ht_supported = true;
2110         else
2111                 spec->ht.ht_supported = false;
2112
2113         spec->ht.cap =
2114             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2115             IEEE80211_HT_CAP_GRN_FLD |
2116             IEEE80211_HT_CAP_SGI_20 |
2117             IEEE80211_HT_CAP_SGI_40 |
2118             IEEE80211_HT_CAP_TX_STBC |
2119             IEEE80211_HT_CAP_RX_STBC;
2120         spec->ht.ampdu_factor = 3;
2121         spec->ht.ampdu_density = 4;
2122         spec->ht.mcs.tx_params =
2123             IEEE80211_HT_MCS_TX_DEFINED |
2124             IEEE80211_HT_MCS_TX_RX_DIFF |
2125             ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2126                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2127
2128         switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2129         case 3:
2130                 spec->ht.mcs.rx_mask[2] = 0xff;
2131         case 2:
2132                 spec->ht.mcs.rx_mask[1] = 0xff;
2133         case 1:
2134                 spec->ht.mcs.rx_mask[0] = 0xff;
2135                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2136                 break;
2137         }
2138
2139         /*
2140          * Create channel information array
2141          */
2142         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2143         if (!info)
2144                 return -ENOMEM;
2145
2146         spec->channels_info = info;
2147
2148         tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2149         tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2150
2151         for (i = 0; i < 14; i++) {
2152                 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2153                 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2154         }
2155
2156         if (spec->num_channels > 14) {
2157                 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2158                 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2159
2160                 for (i = 14; i < spec->num_channels; i++) {
2161                         info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2162                         info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2163                 }
2164         }
2165
2166         return 0;
2167 }
2168 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
2169
2170 /*
2171  * IEEE80211 stack callback functions.
2172  */
2173 static void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2174                                 u32 *iv32, u16 *iv16)
2175 {
2176         struct rt2x00_dev *rt2x00dev = hw->priv;
2177         struct mac_iveiv_entry iveiv_entry;
2178         u32 offset;
2179
2180         offset = MAC_IVEIV_ENTRY(hw_key_idx);
2181         rt2800_register_multiread(rt2x00dev, offset,
2182                                       &iveiv_entry, sizeof(iveiv_entry));
2183
2184         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
2185         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2186 }
2187
2188 static int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2189 {
2190         struct rt2x00_dev *rt2x00dev = hw->priv;
2191         u32 reg;
2192         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2193
2194         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2195         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2196         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2197
2198         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2199         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2200         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2201
2202         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2203         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2204         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2205
2206         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2207         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2208         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2209
2210         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2211         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2212         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2213
2214         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2215         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2216         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2217
2218         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2219         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2220         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2221
2222         return 0;
2223 }
2224
2225 static int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2226                           const struct ieee80211_tx_queue_params *params)
2227 {
2228         struct rt2x00_dev *rt2x00dev = hw->priv;
2229         struct data_queue *queue;
2230         struct rt2x00_field32 field;
2231         int retval;
2232         u32 reg;
2233         u32 offset;
2234
2235         /*
2236          * First pass the configuration through rt2x00lib, that will
2237          * update the queue settings and validate the input. After that
2238          * we are free to update the registers based on the value
2239          * in the queue parameter.
2240          */
2241         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2242         if (retval)
2243                 return retval;
2244
2245         /*
2246          * We only need to perform additional register initialization
2247          * for WMM queues/
2248          */
2249         if (queue_idx >= 4)
2250                 return 0;
2251
2252         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2253
2254         /* Update WMM TXOP register */
2255         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2256         field.bit_offset = (queue_idx & 1) * 16;
2257         field.bit_mask = 0xffff << field.bit_offset;
2258
2259         rt2800_register_read(rt2x00dev, offset, &reg);
2260         rt2x00_set_field32(&reg, field, queue->txop);
2261         rt2800_register_write(rt2x00dev, offset, reg);
2262
2263         /* Update WMM registers */
2264         field.bit_offset = queue_idx * 4;
2265         field.bit_mask = 0xf << field.bit_offset;
2266
2267         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2268         rt2x00_set_field32(&reg, field, queue->aifs);
2269         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2270
2271         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2272         rt2x00_set_field32(&reg, field, queue->cw_min);
2273         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2274
2275         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2276         rt2x00_set_field32(&reg, field, queue->cw_max);
2277         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2278
2279         /* Update EDCA registers */
2280         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2281
2282         rt2800_register_read(rt2x00dev, offset, &reg);
2283         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2284         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2285         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2286         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2287         rt2800_register_write(rt2x00dev, offset, reg);
2288
2289         return 0;
2290 }
2291
2292 static u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2293 {
2294         struct rt2x00_dev *rt2x00dev = hw->priv;
2295         u64 tsf;
2296         u32 reg;
2297
2298         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2299         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2300         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2301         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2302
2303         return tsf;
2304 }
2305
2306 const struct ieee80211_ops rt2800_mac80211_ops = {
2307         .tx                     = rt2x00mac_tx,
2308         .start                  = rt2x00mac_start,
2309         .stop                   = rt2x00mac_stop,
2310         .add_interface          = rt2x00mac_add_interface,
2311         .remove_interface       = rt2x00mac_remove_interface,
2312         .config                 = rt2x00mac_config,
2313         .configure_filter       = rt2x00mac_configure_filter,
2314         .set_tim                = rt2x00mac_set_tim,
2315         .set_key                = rt2x00mac_set_key,
2316         .get_stats              = rt2x00mac_get_stats,
2317         .get_tkip_seq           = rt2800_get_tkip_seq,
2318         .set_rts_threshold      = rt2800_set_rts_threshold,
2319         .bss_info_changed       = rt2x00mac_bss_info_changed,
2320         .conf_tx                = rt2800_conf_tx,
2321         .get_tsf                = rt2800_get_tsf,
2322         .rfkill_poll            = rt2x00mac_rfkill_poll,
2323 };
2324 EXPORT_SYMBOL_GPL(rt2800_mac80211_ops);