drivers/net/wireless/ath/ath5k/phy.c

   1 /*
   2  * PHY functions
   3  *
   4  * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
   5  * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
   6  * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
   7  * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
   8  *
   9  * Permission to use, copy, modify, and distribute this software for any
  10  * purpose with or without fee is hereby granted, provided that the above
  11  * copyright notice and this permission notice appear in all copies.
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  14  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  15  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  16  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  17  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  18  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  19  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  20  *
  21  */
  22
  23 #define _ATH5K_PHY
  24
  25 #include <linux/delay.h>
  26
  27 #include "ath5k.h"
  28 #include "reg.h"
  29 #include "base.h"
  30 #include "rfbuffer.h"
  31 #include "rfgain.h"
  32
  33 /*
  34  * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
  35  */
  36 static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
  37                                         const struct ath5k_rf_reg *rf_regs,
  38                                         u32 val, u8 reg_id, bool set)
  39 {
  40         const struct ath5k_rf_reg *rfreg = NULL;
  41         u8 offset, bank, num_bits, col, position;
  42         u16 entry;
  43         u32 mask, data, last_bit, bits_shifted, first_bit;
  44         u32 *rfb;
  45         s32 bits_left;
  46         int i;
  47
  48         data = 0;
  49         rfb = ah->ah_rf_banks;
  50
  51         for (i = 0; i < ah->ah_rf_regs_count; i++) {
  52                 if (rf_regs[i].index == reg_id) {
  53                         rfreg = &rf_regs[i];
  54                         break;
  55                 }
  56         }
  57
  58         if (rfb == NULL || rfreg == NULL) {
  59                 ATH5K_PRINTF("Rf register not found!\n");
  60                 /* should not happen */
  61                 return 0;
  62         }
  63
  64         bank = rfreg->bank;
  65         num_bits = rfreg->field.len;
  66         first_bit = rfreg->field.pos;
  67         col = rfreg->field.col;
  68
  69         /* first_bit is an offset from bank's
  70          * start. Since we have all banks on
  71          * the same array, we use this offset
  72          * to mark each bank's start */
  73         offset = ah->ah_offset[bank];
  74
  75         /* Boundary check */
  76         if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) {
  77                 ATH5K_PRINTF("invalid values at offset %u\n", offset);
  78                 return 0;
  79         }
  80
  81         entry = ((first_bit - 1) / 8) + offset;
  82         position = (first_bit - 1) % 8;
  83
  84         if (set)
  85                 data = ath5k_hw_bitswap(val, num_bits);
  86
  87         for (bits_shifted = 0, bits_left = num_bits; bits_left > 0;
  88         position = 0, entry++) {
  89
  90                 last_bit = (position + bits_left > 8) ? 8 :
  91                                         position + bits_left;
  92
  93                 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) <<
  94                                                                 (col * 8);
  95
  96                 if (set) {
  97                         rfb[entry] &= ~mask;
  98                         rfb[entry] |= ((data << position) << (col * 8)) & mask;
  99                         data >>= (8 - position);
 100                 } else {
 101                         data |= (((rfb[entry] & mask) >> (col * 8)) >> position)
 102                                 << bits_shifted;
 103                         bits_shifted += last_bit - position;
 104                 }
 105
 106                 bits_left -= 8 - position;
 107         }
 108
 109         data = set ? 1 : ath5k_hw_bitswap(data, num_bits);
 110
 111         return data;
 112 }
 113
 114 /**********************\
 115 * RF Gain optimization *
 116 \**********************/
 117
 118 /*
 119  * This code is used to optimize rf gain on different environments
 120  * (temperature mostly) based on feedback from a power detector.
 121  *
 122  * It's only used on RF5111 and RF5112, later RF chips seem to have
 123  * auto adjustment on hw -notice they have a much smaller BANK 7 and
 124  * no gain optimization ladder-.
 125  *
 126  * For more infos check out this patent doc
 127  * http://www.freepatentsonline.com/7400691.html
 128  *
 129  * This paper describes power drops as seen on the receiver due to
 130  * probe packets
 131  * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
 132  * %20of%20Power%20Control.pdf
 133  *
 134  * And this is the MadWiFi bug entry related to the above
 135  * http://madwifi-project.org/ticket/1659
 136  * with various measurements and diagrams
 137  *
 138  * TODO: Deal with power drops due to probes by setting an apropriate
 139  * tx power on the probe packets ! Make this part of the calibration process.
 140  */
 141
 142 /* Initialize ah_gain durring attach */
 143 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
 144 {
 145         /* Initialize the gain optimization values */
 146         switch (ah->ah_radio) {
 147         case AR5K_RF5111:
 148                 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
 149                 ah->ah_gain.g_low = 20;
 150                 ah->ah_gain.g_high = 35;
 151                 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
 152                 break;
 153         case AR5K_RF5112:
 154                 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
 155                 ah->ah_gain.g_low = 20;
 156                 ah->ah_gain.g_high = 85;
 157                 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
 158                 break;
 159         default:
 160                 return -EINVAL;
 161         }
 162
 163         return 0;
 164 }
 165
 166 /* Schedule a gain probe check on the next transmited packet.
 167  * That means our next packet is going to be sent with lower
 168  * tx power and a Peak to Average Power Detector (PAPD) will try
 169  * to measure the gain.
 170  *
 171  * XXX:  How about forcing a tx packet (bypassing PCU arbitrator etc)
 172  * just after we enable the probe so that we don't mess with
 173  * standard traffic ? Maybe it's time to use sw interrupts and
 174  * a probe tasklet !!!
 175  */
 176 static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
 177 {
 178
 179         /* Skip if gain calibration is inactive or
 180          * we already handle a probe request */
 181         if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE)
 182                 return;
 183
 184         /* Send the packet with 2dB below max power as
 185          * patent doc suggest */
 186         ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4,
 187                         AR5K_PHY_PAPD_PROBE_TXPOWER) |
 188                         AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
 189
 190         ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED;
 191
 192 }
 193
 194 /* Calculate gain_F measurement correction
 195  * based on the current step for RF5112 rev. 2 */
 196 static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
 197 {
 198         u32 mix, step;
 199         u32 *rf;
 200         const struct ath5k_gain_opt *go;
 201         const struct ath5k_gain_opt_step *g_step;
 202         const struct ath5k_rf_reg *rf_regs;
 203
 204         /* Only RF5112 Rev. 2 supports it */
 205         if ((ah->ah_radio != AR5K_RF5112) ||
 206         (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A))
 207                 return 0;
 208
 209         go = &rfgain_opt_5112;
 210         rf_regs = rf_regs_5112a;
 211         ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
 212
 213         g_step = &go->go_step[ah->ah_gain.g_step_idx];
 214
 215         if (ah->ah_rf_banks == NULL)
 216                 return 0;
 217
 218         rf = ah->ah_rf_banks;
 219         ah->ah_gain.g_f_corr = 0;
 220
 221         /* No VGA (Variable Gain Amplifier) override, skip */
 222         if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1)
 223                 return 0;
 224
 225         /* Mix gain stepping */
 226         step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false);
 227
 228         /* Mix gain override */
 229         mix = g_step->gos_param[0];
 230
 231         switch (mix) {
 232         case 3:
 233                 ah->ah_gain.g_f_corr = step * 2;
 234                 break;
 235         case 2:
 236                 ah->ah_gain.g_f_corr = (step - 5) * 2;
 237                 break;
 238         case 1:
 239                 ah->ah_gain.g_f_corr = step;
 240                 break;
 241         default:
 242                 ah->ah_gain.g_f_corr = 0;
 243                 break;
 244         }
 245
 246         return ah->ah_gain.g_f_corr;
 247 }
 248
 249 /* Check if current gain_F measurement is in the range of our
 250  * power detector windows. If we get a measurement outside range
 251  * we know it's not accurate (detectors can't measure anything outside
 252  * their detection window) so we must ignore it */
 253 static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
 254 {
 255         const struct ath5k_rf_reg *rf_regs;
 256         u32 step, mix_ovr, level[4];
 257         u32 *rf;
 258
 259         if (ah->ah_rf_banks == NULL)
 260                 return false;
 261
 262         rf = ah->ah_rf_banks;
 263
 264         if (ah->ah_radio == AR5K_RF5111) {
 265
 266                 rf_regs = rf_regs_5111;
 267                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
 268
 269                 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP,
 270                         false);
 271
 272                 level[0] = 0;
 273                 level[1] = (step == 63) ? 50 : step + 4;
 274                 level[2] = (step != 63) ? 64 : level[0];
 275                 level[3] = level[2] + 50 ;
 276
 277                 ah->ah_gain.g_high = level[3] -
 278                         (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
 279                 ah->ah_gain.g_low = level[0] +
 280                         (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
 281         } else {
 282
 283                 rf_regs = rf_regs_5112;
 284                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
 285
 286                 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR,
 287                         false);
 288
 289                 level[0] = level[2] = 0;
 290
 291                 if (mix_ovr == 1) {
 292                         level[1] = level[3] = 83;
 293                 } else {
 294                         level[1] = level[3] = 107;
 295                         ah->ah_gain.g_high = 55;
 296                 }
 297         }
 298
 299         return (ah->ah_gain.g_current >= level[0] &&
 300                         ah->ah_gain.g_current <= level[1]) ||
 301                 (ah->ah_gain.g_current >= level[2] &&
 302                         ah->ah_gain.g_current <= level[3]);
 303 }
 304
 305 /* Perform gain_F adjustment by choosing the right set
 306  * of parameters from rf gain optimization ladder */
 307 static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
 308 {
 309         const struct ath5k_gain_opt *go;
 310         const struct ath5k_gain_opt_step *g_step;
 311         int ret = 0;
 312
 313         switch (ah->ah_radio) {
 314         case AR5K_RF5111:
 315                 go = &rfgain_opt_5111;
 316                 break;
 317         case AR5K_RF5112:
 318                 go = &rfgain_opt_5112;
 319                 break;
 320         default:
 321                 return 0;
 322         }
 323
 324         g_step = &go->go_step[ah->ah_gain.g_step_idx];
 325
 326         if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
 327
 328                 /* Reached maximum */
 329                 if (ah->ah_gain.g_step_idx == 0)
 330                         return -1;
 331
 332                 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
 333                                 ah->ah_gain.g_target >=  ah->ah_gain.g_high &&
 334                                 ah->ah_gain.g_step_idx > 0;
 335                                 g_step = &go->go_step[ah->ah_gain.g_step_idx])
 336                         ah->ah_gain.g_target -= 2 *
 337                             (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
 338                             g_step->gos_gain);
 339
 340                 ret = 1;
 341                 goto done;
 342         }
 343
 344         if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
 345
 346                 /* Reached minimum */
 347                 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
 348                         return -2;
 349
 350                 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
 351                                 ah->ah_gain.g_target <= ah->ah_gain.g_low &&
 352                                 ah->ah_gain.g_step_idx < go->go_steps_count-1;
 353                                 g_step = &go->go_step[ah->ah_gain.g_step_idx])
 354                         ah->ah_gain.g_target -= 2 *
 355                             (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
 356                             g_step->gos_gain);
 357
 358                 ret = 2;
 359                 goto done;
 360         }
 361
 362 done:
 363         ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
 364                 "ret %d, gain step %u, current gain %u, target gain %u\n",
 365                 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
 366                 ah->ah_gain.g_target);
 367
 368         return ret;
 369 }
 370
 371 /* Main callback for thermal rf gain calibration engine
 372  * Check for a new gain reading and schedule an adjustment
 373  * if needed.
 374  *
 375  * TODO: Use sw interrupt to schedule reset if gain_F needs
 376  * adjustment */
 377 enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
 378 {
 379         u32 data, type;
 380         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 381
 382         ATH5K_TRACE(ah->ah_sc);
 383
 384         if (ah->ah_rf_banks == NULL ||
 385         ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE)
 386                 return AR5K_RFGAIN_INACTIVE;
 387
 388         /* No check requested, either engine is inactive
 389          * or an adjustment is already requested */
 390         if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED)
 391                 goto done;
 392
 393         /* Read the PAPD (Peak to Average Power Detector)
 394          * register */
 395         data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
 396
 397         /* No probe is scheduled, read gain_F measurement */
 398         if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
 399                 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
 400                 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
 401
 402                 /* If tx packet is CCK correct the gain_F measurement
 403                  * by cck ofdm gain delta */
 404                 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) {
 405                         if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
 406                                 ah->ah_gain.g_current +=
 407                                         ee->ee_cck_ofdm_gain_delta;
 408                         else
 409                                 ah->ah_gain.g_current +=
 410                                         AR5K_GAIN_CCK_PROBE_CORR;
 411                 }
 412
 413                 /* Further correct gain_F measurement for
 414                  * RF5112A radios */
 415                 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
 416                         ath5k_hw_rf_gainf_corr(ah);
 417                         ah->ah_gain.g_current =
 418                                 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ?
 419                                 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) :
 420                                 0;
 421                 }
 422
 423                 /* Check if measurement is ok and if we need
 424                  * to adjust gain, schedule a gain adjustment,
 425                  * else switch back to the acive state */
 426                 if (ath5k_hw_rf_check_gainf_readback(ah) &&
 427                 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
 428                 ath5k_hw_rf_gainf_adjust(ah)) {
 429                         ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE;
 430                 } else {
 431                         ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
 432                 }
 433         }
 434
 435 done:
 436         return ah->ah_gain.g_state;
 437 }
 438
 439 /* Write initial rf gain table to set the RF sensitivity
 440  * this one works on all RF chips and has nothing to do
 441  * with gain_F calibration */
 442 int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq)
 443 {
 444         const struct ath5k_ini_rfgain *ath5k_rfg;
 445         unsigned int i, size;
 446
 447         switch (ah->ah_radio) {
 448         case AR5K_RF5111:
 449                 ath5k_rfg = rfgain_5111;
 450                 size = ARRAY_SIZE(rfgain_5111);
 451                 break;
 452         case AR5K_RF5112:
 453                 ath5k_rfg = rfgain_5112;
 454                 size = ARRAY_SIZE(rfgain_5112);
 455                 break;
 456         case AR5K_RF2413:
 457                 ath5k_rfg = rfgain_2413;
 458                 size = ARRAY_SIZE(rfgain_2413);
 459                 break;
 460         case AR5K_RF2316:
 461                 ath5k_rfg = rfgain_2316;
 462                 size = ARRAY_SIZE(rfgain_2316);
 463                 break;
 464         case AR5K_RF5413:
 465                 ath5k_rfg = rfgain_5413;
 466                 size = ARRAY_SIZE(rfgain_5413);
 467                 break;
 468         case AR5K_RF2317:
 469         case AR5K_RF2425:
 470                 ath5k_rfg = rfgain_2425;
 471                 size = ARRAY_SIZE(rfgain_2425);
 472                 break;
 473         default:
 474                 return -EINVAL;
 475         }
 476
 477         switch (freq) {
 478         case AR5K_INI_RFGAIN_2GHZ:
 479         case AR5K_INI_RFGAIN_5GHZ:
 480                 break;
 481         default:
 482                 return -EINVAL;
 483         }
 484
 485         for (i = 0; i < size; i++) {
 486                 AR5K_REG_WAIT(i);
 487                 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq],
 488                         (u32)ath5k_rfg[i].rfg_register);
 489         }
 490
 491         return 0;
 492 }
 493
 494
 495
 496 /********************\
 497 * RF Registers setup *
 498 \********************/
 499
 500
 501 /*
 502  * Setup RF registers by writing rf buffer on hw
 503  */
 504 int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
 505                 unsigned int mode)
 506 {
 507         const struct ath5k_rf_reg *rf_regs;
 508         const struct ath5k_ini_rfbuffer *ini_rfb;
 509         const struct ath5k_gain_opt *go = NULL;
 510         const struct ath5k_gain_opt_step *g_step;
 511         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 512         u8 ee_mode = 0;
 513         u32 *rfb;
 514         int i, obdb = -1, bank = -1;
 515
 516         switch (ah->ah_radio) {
 517         case AR5K_RF5111:
 518                 rf_regs = rf_regs_5111;
 519                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
 520                 ini_rfb = rfb_5111;
 521                 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111);
 522                 go = &rfgain_opt_5111;
 523                 break;
 524         case AR5K_RF5112:
 525                 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
 526                         rf_regs = rf_regs_5112a;
 527                         ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
 528                         ini_rfb = rfb_5112a;
 529                         ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a);
 530                 } else {
 531                         rf_regs = rf_regs_5112;
 532                         ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
 533                         ini_rfb = rfb_5112;
 534                         ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112);
 535                 }
 536                 go = &rfgain_opt_5112;
 537                 break;
 538         case AR5K_RF2413:
 539                 rf_regs = rf_regs_2413;
 540                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413);
 541                 ini_rfb = rfb_2413;
 542                 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413);
 543                 break;
 544         case AR5K_RF2316:
 545                 rf_regs = rf_regs_2316;
 546                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316);
 547                 ini_rfb = rfb_2316;
 548                 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316);
 549                 break;
 550         case AR5K_RF5413:
 551                 rf_regs = rf_regs_5413;
 552                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413);
 553                 ini_rfb = rfb_5413;
 554                 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413);
 555                 break;
 556         case AR5K_RF2317:
 557                 rf_regs = rf_regs_2425;
 558                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
 559                 ini_rfb = rfb_2317;
 560                 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317);
 561                 break;
 562         case AR5K_RF2425:
 563                 rf_regs = rf_regs_2425;
 564                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
 565                 if (ah->ah_mac_srev < AR5K_SREV_AR2417) {
 566                         ini_rfb = rfb_2425;
 567                         ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425);
 568                 } else {
 569                         ini_rfb = rfb_2417;
 570                         ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417);
 571                 }
 572                 break;
 573         default:
 574                 return -EINVAL;
 575         }
 576
 577         /* If it's the first time we set rf buffer, allocate
 578          * ah->ah_rf_banks based on ah->ah_rf_banks_size
 579          * we set above */
 580         if (ah->ah_rf_banks == NULL) {
 581                 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size,
 582                                                                 GFP_KERNEL);
 583                 if (ah->ah_rf_banks == NULL) {
 584                         ATH5K_ERR(ah->ah_sc, "out of memory\n");
 585                         return -ENOMEM;
 586                 }
 587         }
 588
 589         /* Copy values to modify them */
 590         rfb = ah->ah_rf_banks;
 591
 592         for (i = 0; i < ah->ah_rf_banks_size; i++) {
 593                 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) {
 594                         ATH5K_ERR(ah->ah_sc, "invalid bank\n");
 595                         return -EINVAL;
 596                 }
 597
 598                 /* Bank changed, write down the offset */
 599                 if (bank != ini_rfb[i].rfb_bank) {
 600                         bank = ini_rfb[i].rfb_bank;
 601                         ah->ah_offset[bank] = i;
 602                 }
 603
 604                 rfb[i] = ini_rfb[i].rfb_mode_data[mode];
 605         }
 606
 607         /* Set Output and Driver bias current (OB/DB) */
 608         if (channel->hw_value & CHANNEL_2GHZ) {
 609
 610                 if (channel->hw_value & CHANNEL_CCK)
 611                         ee_mode = AR5K_EEPROM_MODE_11B;
 612                 else
 613                         ee_mode = AR5K_EEPROM_MODE_11G;
 614
 615                 /* For RF511X/RF211X combination we
 616                  * use b_OB and b_DB parameters stored
 617                  * in eeprom on ee->ee_ob[ee_mode][0]
 618                  *
 619                  * For all other chips we use OB/DB for 2Ghz
 620                  * stored in the b/g modal section just like
 621                  * 802.11a on ee->ee_ob[ee_mode][1] */
 622                 if ((ah->ah_radio == AR5K_RF5111) ||
 623                 (ah->ah_radio == AR5K_RF5112))
 624                         obdb = 0;
 625                 else
 626                         obdb = 1;
 627
 628                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
 629                                                 AR5K_RF_OB_2GHZ, true);
 630
 631                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
 632                                                 AR5K_RF_DB_2GHZ, true);
 633
 634         /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */
 635         } else if ((channel->hw_value & CHANNEL_5GHZ) ||
 636                         (ah->ah_radio == AR5K_RF5111)) {
 637
 638                 /* For 11a, Turbo and XR we need to choose
 639                  * OB/DB based on frequency range */
 640                 ee_mode = AR5K_EEPROM_MODE_11A;
 641                 obdb =   channel->center_freq >= 5725 ? 3 :
 642                         (channel->center_freq >= 5500 ? 2 :
 643                         (channel->center_freq >= 5260 ? 1 :
 644                          (channel->center_freq > 4000 ? 0 : -1)));
 645
 646                 if (obdb < 0)
 647                         return -EINVAL;
 648
 649                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
 650                                                 AR5K_RF_OB_5GHZ, true);
 651
 652                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
 653                                                 AR5K_RF_DB_5GHZ, true);
 654         }
 655
 656         g_step = &go->go_step[ah->ah_gain.g_step_idx];
 657
 658         /* Bank Modifications (chip-specific) */
 659         if (ah->ah_radio == AR5K_RF5111) {
 660
 661                 /* Set gain_F settings according to current step */
 662                 if (channel->hw_value & CHANNEL_OFDM) {
 663
 664                         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
 665                                         AR5K_PHY_FRAME_CTL_TX_CLIP,
 666                                         g_step->gos_param[0]);
 667
 668                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
 669                                                         AR5K_RF_PWD_90, true);
 670
 671                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
 672                                                         AR5K_RF_PWD_84, true);
 673
 674                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
 675                                                 AR5K_RF_RFGAIN_SEL, true);
 676
 677                         /* We programmed gain_F parameters, switch back
 678                          * to active state */
 679                         ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
 680
 681                 }
 682
 683                 /* Bank 6/7 setup */
 684
 685                 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode],
 686                                                 AR5K_RF_PWD_XPD, true);
 687
 688                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode],
 689                                                 AR5K_RF_XPD_GAIN, true);
 690
 691                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
 692                                                 AR5K_RF_GAIN_I, true);
 693
 694                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
 695                                                 AR5K_RF_PLO_SEL, true);
 696
 697                 /* TODO: Half/quarter channel support */
 698         }
 699
 700         if (ah->ah_radio == AR5K_RF5112) {
 701
 702                 /* Set gain_F settings according to current step */
 703                 if (channel->hw_value & CHANNEL_OFDM) {
 704
 705                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0],
 706                                                 AR5K_RF_MIXGAIN_OVR, true);
 707
 708                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
 709                                                 AR5K_RF_PWD_138, true);
 710
 711                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
 712                                                 AR5K_RF_PWD_137, true);
 713
 714                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
 715                                                 AR5K_RF_PWD_136, true);
 716
 717                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4],
 718                                                 AR5K_RF_PWD_132, true);
 719
 720                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5],
 721                                                 AR5K_RF_PWD_131, true);
 722
 723                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6],
 724                                                 AR5K_RF_PWD_130, true);
 725
 726                         /* We programmed gain_F parameters, switch back
 727                          * to active state */
 728                         ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
 729                 }
 730
 731                 /* Bank 6/7 setup */
 732
 733                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
 734                                                 AR5K_RF_XPD_SEL, true);
 735
 736                 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {
 737                         /* Rev. 1 supports only one xpd */
 738                         ath5k_hw_rfb_op(ah, rf_regs,
 739                                                 ee->ee_x_gain[ee_mode],
 740                                                 AR5K_RF_XPD_GAIN, true);
 741
 742                 } else {
 743                         u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
 744                         if (ee->ee_pd_gains[ee_mode] > 1) {
 745                                 ath5k_hw_rfb_op(ah, rf_regs,
 746                                                 pdg_curve_to_idx[0],
 747                                                 AR5K_RF_PD_GAIN_LO, true);
 748                                 ath5k_hw_rfb_op(ah, rf_regs,
 749                                                 pdg_curve_to_idx[1],
 750                                                 AR5K_RF_PD_GAIN_HI, true);
 751                         } else {
 752                                 ath5k_hw_rfb_op(ah, rf_regs,
 753                                                 pdg_curve_to_idx[0],
 754                                                 AR5K_RF_PD_GAIN_LO, true);
 755                                 ath5k_hw_rfb_op(ah, rf_regs,
 756                                                 pdg_curve_to_idx[0],
 757                                                 AR5K_RF_PD_GAIN_HI, true);
 758                         }
 759
 760                         /* Lower synth voltage on Rev 2 */
 761                         ath5k_hw_rfb_op(ah, rf_regs, 2,
 762                                         AR5K_RF_HIGH_VC_CP, true);
 763
 764                         ath5k_hw_rfb_op(ah, rf_regs, 2,
 765                                         AR5K_RF_MID_VC_CP, true);
 766
 767                         ath5k_hw_rfb_op(ah, rf_regs, 2,
 768                                         AR5K_RF_LOW_VC_CP, true);
 769
 770                         ath5k_hw_rfb_op(ah, rf_regs, 2,
 771                                         AR5K_RF_PUSH_UP, true);
 772
 773                         /* Decrease power consumption on 5213+ BaseBand */
 774                         if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
 775                                 ath5k_hw_rfb_op(ah, rf_regs, 1,
 776                                                 AR5K_RF_PAD2GND, true);
 777
 778                                 ath5k_hw_rfb_op(ah, rf_regs, 1,
 779                                                 AR5K_RF_XB2_LVL, true);
 780
 781                                 ath5k_hw_rfb_op(ah, rf_regs, 1,
 782                                                 AR5K_RF_XB5_LVL, true);
 783
 784                                 ath5k_hw_rfb_op(ah, rf_regs, 1,
 785                                                 AR5K_RF_PWD_167, true);
 786
 787                                 ath5k_hw_rfb_op(ah, rf_regs, 1,
 788                                                 AR5K_RF_PWD_166, true);
 789                         }
 790                 }
 791
 792                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
 793                                                 AR5K_RF_GAIN_I, true);
 794
 795                 /* TODO: Half/quarter channel support */
 796
 797         }
 798
 799         if (ah->ah_radio == AR5K_RF5413 &&
 800         channel->hw_value & CHANNEL_2GHZ) {
 801
 802                 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE,
 803                                                                         true);
 804
 805                 /* Set optimum value for early revisions (on pci-e chips) */
 806                 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 &&
 807                 ah->ah_mac_srev < AR5K_SREV_AR5413)
 808                         ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3),
 809                                                 AR5K_RF_PWD_ICLOBUF_2G, true);
 810
 811         }
 812
 813         /* Write RF banks on hw */
 814         for (i = 0; i < ah->ah_rf_banks_size; i++) {
 815                 AR5K_REG_WAIT(i);
 816                 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register);
 817         }
 818
 819         return 0;
 820 }
 821
 822
 823 /**************************\
 824   PHY/RF channel functions
 825 \**************************/
 826
 827 /*
 828  * Check if a channel is supported
 829  */
 830 bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
 831 {
 832         /* Check if the channel is in our supported range */
 833         if (flags & CHANNEL_2GHZ) {
 834                 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
 835                     (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
 836                         return true;
 837         } else if (flags & CHANNEL_5GHZ)
 838                 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
 839                     (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
 840                         return true;
 841
 842         return false;
 843 }
 844
 845 /*
 846  * Convertion needed for RF5110
 847  */
 848 static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
 849 {
 850         u32 athchan;
 851
 852         /*
 853          * Convert IEEE channel/MHz to an internal channel value used
 854          * by the AR5210 chipset. This has not been verified with
 855          * newer chipsets like the AR5212A who have a completely
 856          * different RF/PHY part.
 857          */
 858         athchan = (ath5k_hw_bitswap(
 859                         (ieee80211_frequency_to_channel(
 860                                 channel->center_freq) - 24) / 2, 5)
 861                                 << 1) | (1 << 6) | 0x1;
 862         return athchan;
 863 }
 864
 865 /*
 866  * Set channel on RF5110
 867  */
 868 static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
 869                 struct ieee80211_channel *channel)
 870 {
 871         u32 data;
 872
 873         /*
 874          * Set the channel and wait
 875          */
 876         data = ath5k_hw_rf5110_chan2athchan(channel);
 877         ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
 878         ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
 879         mdelay(1);
 880
 881         return 0;
 882 }
 883
 884 /*
 885  * Convertion needed for 5111
 886  */
 887 static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
 888                 struct ath5k_athchan_2ghz *athchan)
 889 {
 890         int channel;
 891
 892         /* Cast this value to catch negative channel numbers (>= -19) */
 893         channel = (int)ieee;
 894
 895         /*
 896          * Map 2GHz IEEE channel to 5GHz Atheros channel
 897          */
 898         if (channel <= 13) {
 899                 athchan->a2_athchan = 115 + channel;
 900                 athchan->a2_flags = 0x46;
 901         } else if (channel == 14) {
 902                 athchan->a2_athchan = 124;
 903                 athchan->a2_flags = 0x44;
 904         } else if (channel >= 15 && channel <= 26) {
 905                 athchan->a2_athchan = ((channel - 14) * 4) + 132;
 906                 athchan->a2_flags = 0x46;
 907         } else
 908                 return -EINVAL;
 909
 910         return 0;
 911 }
 912
 913 /*
 914  * Set channel on 5111
 915  */
 916 static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
 917                 struct ieee80211_channel *channel)
 918 {
 919         struct ath5k_athchan_2ghz ath5k_channel_2ghz;
 920         unsigned int ath5k_channel =
 921                 ieee80211_frequency_to_channel(channel->center_freq);
 922         u32 data0, data1, clock;
 923         int ret;
 924
 925         /*
 926          * Set the channel on the RF5111 radio
 927          */
 928         data0 = data1 = 0;
 929
 930         if (channel->hw_value & CHANNEL_2GHZ) {
 931                 /* Map 2GHz channel to 5GHz Atheros channel ID */
 932                 ret = ath5k_hw_rf5111_chan2athchan(
 933                         ieee80211_frequency_to_channel(channel->center_freq),
 934                         &ath5k_channel_2ghz);
 935                 if (ret)
 936                         return ret;
 937
 938                 ath5k_channel = ath5k_channel_2ghz.a2_athchan;
 939                 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
 940                     << 5) | (1 << 4);
 941         }
 942
 943         if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
 944                 clock = 1;
 945                 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
 946                         (clock << 1) | (1 << 10) | 1;
 947         } else {
 948                 clock = 0;
 949                 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
 950                         << 2) | (clock << 1) | (1 << 10) | 1;
 951         }
 952
 953         ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
 954                         AR5K_RF_BUFFER);
 955         ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
 956                         AR5K_RF_BUFFER_CONTROL_3);
 957
 958         return 0;
 959 }
 960
 961 /*
 962  * Set channel on 5112 and newer
 963  */
 964 static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
 965                 struct ieee80211_channel *channel)
 966 {
 967         u32 data, data0, data1, data2;
 968         u16 c;
 969
 970         data = data0 = data1 = data2 = 0;
 971         c = channel->center_freq;
 972
 973         if (c < 4800) {
 974                 if (!((c - 2224) % 5)) {
 975                         data0 = ((2 * (c - 704)) - 3040) / 10;
 976                         data1 = 1;
 977                 } else if (!((c - 2192) % 5)) {
 978                         data0 = ((2 * (c - 672)) - 3040) / 10;
 979                         data1 = 0;
 980                 } else
 981                         return -EINVAL;
 982
 983                 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
 984         } else if ((c - (c % 5)) != 2 || c > 5435) {
 985                 if (!(c % 20) && c >= 5120) {
 986                         data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
 987                         data2 = ath5k_hw_bitswap(3, 2);
 988                 } else if (!(c % 10)) {
 989                         data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
 990                         data2 = ath5k_hw_bitswap(2, 2);
 991                 } else if (!(c % 5)) {
 992                         data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
 993                         data2 = ath5k_hw_bitswap(1, 2);
 994                 } else
 995                         return -EINVAL;
 996         } else {
 997                 data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
 998                 data2 = ath5k_hw_bitswap(0, 2);
 999         }
1000
1001         data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
1002
1003         ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1004         ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1005
1006         return 0;
1007 }
1008
1009 /*
1010  * Set the channel on the RF2425
1011  */
1012 static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
1013                 struct ieee80211_channel *channel)
1014 {
1015         u32 data, data0, data2;
1016         u16 c;
1017
1018         data = data0 = data2 = 0;
1019         c = channel->center_freq;
1020
1021         if (c < 4800) {
1022                 data0 = ath5k_hw_bitswap((c - 2272), 8);
1023                 data2 = 0;
1024         /* ? 5GHz ? */
1025         } else if ((c - (c % 5)) != 2 || c > 5435) {
1026                 if (!(c % 20) && c < 5120)
1027                         data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1028                 else if (!(c % 10))
1029                         data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1030                 else if (!(c % 5))
1031                         data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1032                 else
1033                         return -EINVAL;
1034                 data2 = ath5k_hw_bitswap(1, 2);
1035         } else {
1036                 data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
1037                 data2 = ath5k_hw_bitswap(0, 2);
1038         }
1039
1040         data = (data0 << 4) | data2 << 2 | 0x1001;
1041
1042         ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1043         ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1044
1045         return 0;
1046 }
1047
1048 /*
1049  * Set a channel on the radio chip
1050  */
1051 int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel)
1052 {
1053         int ret;
1054         /*
1055          * Check bounds supported by the PHY (we don't care about regultory
1056          * restrictions at this point). Note: hw_value already has the band
1057          * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
1058          * of the band by that */
1059         if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
1060                 ATH5K_ERR(ah->ah_sc,
1061                         "channel frequency (%u MHz) out of supported "
1062                         "band range\n",
1063                         channel->center_freq);
1064                         return -EINVAL;
1065         }
1066
1067         /*
1068          * Set the channel and wait
1069          */
1070         switch (ah->ah_radio) {
1071         case AR5K_RF5110:
1072                 ret = ath5k_hw_rf5110_channel(ah, channel);
1073                 break;
1074         case AR5K_RF5111:
1075                 ret = ath5k_hw_rf5111_channel(ah, channel);
1076                 break;
1077         case AR5K_RF2425:
1078                 ret = ath5k_hw_rf2425_channel(ah, channel);
1079                 break;
1080         default:
1081                 ret = ath5k_hw_rf5112_channel(ah, channel);
1082                 break;
1083         }
1084
1085         if (ret)
1086                 return ret;
1087
1088         /* Set JAPAN setting for channel 14 */
1089         if (channel->center_freq == 2484) {
1090                 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1091                                 AR5K_PHY_CCKTXCTL_JAPAN);
1092         } else {
1093                 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1094                                 AR5K_PHY_CCKTXCTL_WORLD);
1095         }
1096
1097         ah->ah_current_channel = channel;
1098         ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false;
1099
1100         return 0;
1101 }
1102
1103 /*****************\
1104   PHY calibration
1105 \*****************/
1106
1107 void
1108 ath5k_hw_calibration_poll(struct ath5k_hw *ah)
1109 {
1110         /* Calibration interval in jiffies */
1111         unsigned long cal_intval;
1112
1113         cal_intval = msecs_to_jiffies(ah->ah_cal_intval * 1000);
1114
1115         /* Initialize timestamp if needed */
1116         if (!ah->ah_cal_tstamp)
1117                 ah->ah_cal_tstamp = jiffies;
1118
1119         /* For now we always do full calibration
1120          * Mark software interrupt mask and fire software
1121          * interrupt (bit gets auto-cleared) */
1122         if (time_is_before_eq_jiffies(ah->ah_cal_tstamp + cal_intval)) {
1123                 ah->ah_cal_tstamp = jiffies;
1124                 ah->ah_swi_mask = AR5K_SWI_FULL_CALIBRATION;
1125                 AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI);
1126         }
1127 }
1128
1129 static int sign_extend(int val, const int nbits)
1130 {
1131         int order = BIT(nbits-1);
1132         return (val ^ order) - order;
1133 }
1134
1135 static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah)
1136 {
1137         s32 val;
1138
1139         val = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
1140         return sign_extend(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 9);
1141 }
1142
1143 void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah)
1144 {
1145         int i;
1146
1147         ah->ah_nfcal_hist.index = 0;
1148         for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++)
1149                 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1150 }
1151
1152 static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor)
1153 {
1154         struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist;
1155         hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX-1);
1156         hist->nfval[hist->index] = noise_floor;
1157 }
1158
1159 static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah)
1160 {
1161         s16 sort[ATH5K_NF_CAL_HIST_MAX];
1162         s16 tmp;
1163         int i, j;
1164
1165         memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort));
1166         for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) {
1167                 for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) {
1168                         if (sort[j] > sort[j-1]) {
1169                                 tmp = sort[j];
1170                                 sort[j] = sort[j-1];
1171                                 sort[j-1] = tmp;
1172                         }
1173                 }
1174         }
1175         for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) {
1176                 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1177                         "cal %d:%d\n", i, sort[i]);
1178         }
1179         return sort[(ATH5K_NF_CAL_HIST_MAX-1) / 2];
1180 }
1181
1182 /*
1183  * When we tell the hardware to perform a noise floor calibration
1184  * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically
1185  * sample-and-hold the minimum noise level seen at the antennas.
1186  * This value is then stored in a ring buffer of recently measured
1187  * noise floor values so we have a moving window of the last few
1188  * samples.
1189  *
1190  * The median of the values in the history is then loaded into the
1191  * hardware for its own use for RSSI and CCA measurements.
1192  */
1193 void ath5k_hw_update_noise_floor(struct ath5k_hw *ah)
1194 {
1195         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1196         u32 val;
1197         s16 nf, threshold;
1198         u8 ee_mode;
1199
1200         /* keep last value if calibration hasn't completed */
1201         if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) {
1202                 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1203                         "NF did not complete in calibration window\n");
1204
1205                 return;
1206         }
1207
1208         switch (ah->ah_current_channel->hw_value & CHANNEL_MODES) {
1209         case CHANNEL_A:
1210         case CHANNEL_T:
1211         case CHANNEL_XR:
1212                 ee_mode = AR5K_EEPROM_MODE_11A;
1213                 break;
1214         case CHANNEL_G:
1215         case CHANNEL_TG:
1216                 ee_mode = AR5K_EEPROM_MODE_11G;
1217                 break;
1218         default:
1219         case CHANNEL_B:
1220                 ee_mode = AR5K_EEPROM_MODE_11B;
1221                 break;
1222         }
1223
1224
1225         /* completed NF calibration, test threshold */
1226         nf = ath5k_hw_read_measured_noise_floor(ah);
1227         threshold = ee->ee_noise_floor_thr[ee_mode];
1228
1229         if (nf > threshold) {
1230                 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1231                         "noise floor failure detected; "
1232                         "read %d, threshold %d\n",
1233                         nf, threshold);
1234
1235                 nf = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1236         }
1237
1238         ath5k_hw_update_nfcal_hist(ah, nf);
1239         nf = ath5k_hw_get_median_noise_floor(ah);
1240
1241         /* load noise floor (in .5 dBm) so the hardware will use it */
1242         val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M;
1243         val |= (nf * 2) & AR5K_PHY_NF_M;
1244         ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1245
1246         AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1247                 ~(AR5K_PHY_AGCCTL_NF_EN | AR5K_PHY_AGCCTL_NF_NOUPDATE));
1248
1249         ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1250                 0, false);
1251
1252         /*
1253          * Load a high max CCA Power value (-50 dBm in .5 dBm units)
1254          * so that we're not capped by the median we just loaded.
1255          * This will be used as the initial value for the next noise
1256          * floor calibration.
1257          */
1258         val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M);
1259         ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1260         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1261                 AR5K_PHY_AGCCTL_NF_EN |
1262                 AR5K_PHY_AGCCTL_NF_NOUPDATE |
1263                 AR5K_PHY_AGCCTL_NF);
1264
1265         ah->ah_noise_floor = nf;
1266
1267         ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1268                 "noise floor calibrated: %d\n", nf);
1269 }
1270
1271 /*
1272  * Perform a PHY calibration on RF5110
1273  * -Fix BPSK/QAM Constellation (I/Q correction)
1274  * -Calculate Noise Floor
1275  */
1276 static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
1277                 struct ieee80211_channel *channel)
1278 {
1279         u32 phy_sig, phy_agc, phy_sat, beacon;
1280         int ret;
1281
1282         /*
1283          * Disable beacons and RX/TX queues, wait
1284          */
1285         AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
1286                 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
1287         beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
1288         ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
1289
1290         mdelay(2);
1291
1292         /*
1293          * Set the channel (with AGC turned off)
1294          */
1295         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1296         udelay(10);
1297         ret = ath5k_hw_channel(ah, channel);
1298
1299         /*
1300          * Activate PHY and wait
1301          */
1302         ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1303         mdelay(1);
1304
1305         AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1306
1307         if (ret)
1308                 return ret;
1309
1310         /*
1311          * Calibrate the radio chip
1312          */
1313
1314         /* Remember normal state */
1315         phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
1316         phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
1317         phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
1318
1319         /* Update radio registers */
1320         ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
1321                 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
1322
1323         ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
1324                         AR5K_PHY_AGCCOARSE_LO)) |
1325                 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
1326                 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
1327
1328         ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
1329                         AR5K_PHY_ADCSAT_THR)) |
1330                 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
1331                 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
1332
1333         udelay(20);
1334
1335         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1336         udelay(10);
1337         ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
1338         AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1339
1340         mdelay(1);
1341
1342         /*
1343          * Enable calibration and wait until completion
1344          */
1345         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
1346
1347         ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1348                         AR5K_PHY_AGCCTL_CAL, 0, false);
1349
1350         /* Reset to normal state */
1351         ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
1352         ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
1353         ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
1354
1355         if (ret) {
1356                 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
1357                                 channel->center_freq);
1358                 return ret;
1359         }
1360
1361         ath5k_hw_update_noise_floor(ah);
1362
1363         /*
1364          * Re-enable RX/TX and beacons
1365          */
1366         AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
1367                 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
1368         ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
1369
1370         return 0;
1371 }
1372
1373 /*
1374  * Perform a PHY calibration on RF5111/5112 and newer chips
1375  */
1376 static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah,
1377                 struct ieee80211_channel *channel)
1378 {
1379         u32 i_pwr, q_pwr;
1380         s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
1381         int i;
1382         ATH5K_TRACE(ah->ah_sc);
1383
1384         if (!ah->ah_calibration ||
1385                 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
1386                 goto done;
1387
1388         /* Calibration has finished, get the results and re-run */
1389         for (i = 0; i <= 10; i++) {
1390                 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
1391                 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
1392                 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
1393         }
1394
1395         i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
1396         q_coffd = q_pwr >> 7;
1397
1398         /* No correction */
1399         if (i_coffd == 0 || q_coffd == 0)
1400                 goto done;
1401
1402         i_coff = ((-iq_corr) / i_coffd);
1403
1404         /* Boundary check */
1405         if (i_coff > 31)
1406                 i_coff = 31;
1407         if (i_coff < -32)
1408                 i_coff = -32;
1409
1410         q_coff = (((s32)i_pwr / q_coffd) - 128);
1411
1412         /* Boundary check */
1413         if (q_coff > 15)
1414                 q_coff = 15;
1415         if (q_coff < -16)
1416                 q_coff = -16;
1417
1418         /* Commit new I/Q value */
1419         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE |
1420                 ((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S));
1421
1422         /* Re-enable calibration -if we don't we'll commit
1423          * the same values again and again */
1424         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
1425                         AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
1426         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN);
1427
1428 done:
1429
1430         /* TODO: Separate noise floor calibration from I/Q calibration
1431          * since noise floor calibration interrupts rx path while I/Q
1432          * calibration doesn't. We don't need to run noise floor calibration
1433          * as often as I/Q calibration.*/
1434         ath5k_hw_update_noise_floor(ah);
1435
1436         /* Initiate a gain_F calibration */
1437         ath5k_hw_request_rfgain_probe(ah);
1438
1439         return 0;
1440 }
1441
1442 /*
1443  * Perform a PHY calibration
1444  */
1445 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1446                 struct ieee80211_channel *channel)
1447 {
1448         int ret;
1449
1450         if (ah->ah_radio == AR5K_RF5110)
1451                 ret = ath5k_hw_rf5110_calibrate(ah, channel);
1452         else
1453                 ret = ath5k_hw_rf511x_calibrate(ah, channel);
1454
1455         return ret;
1456 }
1457
1458 /***************************\
1459 * Spur mitigation functions *
1460 \***************************/
1461
1462 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
1463                                 struct ieee80211_channel *channel)
1464 {
1465         u8 refclk_freq;
1466
1467         if ((ah->ah_radio == AR5K_RF5112) ||
1468         (ah->ah_radio == AR5K_RF5413) ||
1469         (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
1470                 refclk_freq = 40;
1471         else
1472                 refclk_freq = 32;
1473
1474         if ((channel->center_freq % refclk_freq != 0) &&
1475         ((channel->center_freq % refclk_freq < 10) ||
1476         (channel->center_freq % refclk_freq > 22)))
1477                 return true;
1478         else
1479                 return false;
1480 }
1481
1482 void
1483 ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
1484                                 struct ieee80211_channel *channel)
1485 {
1486         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1487         u32 mag_mask[4] = {0, 0, 0, 0};
1488         u32 pilot_mask[2] = {0, 0};
1489         /* Note: fbin values are scaled up by 2 */
1490         u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window;
1491         s32 spur_delta_phase, spur_freq_sigma_delta;
1492         s32 spur_offset, num_symbols_x16;
1493         u8 num_symbol_offsets, i, freq_band;
1494
1495         /* Convert current frequency to fbin value (the same way channels
1496          * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale
1497          * up by 2 so we can compare it later */
1498         if (channel->hw_value & CHANNEL_2GHZ) {
1499                 chan_fbin = (channel->center_freq - 2300) * 10;
1500                 freq_band = AR5K_EEPROM_BAND_2GHZ;
1501         } else {
1502                 chan_fbin = (channel->center_freq - 4900) * 10;
1503                 freq_band = AR5K_EEPROM_BAND_5GHZ;
1504         }
1505
1506         /* Check if any spur_chan_fbin from EEPROM is
1507          * within our current channel's spur detection range */
1508         spur_chan_fbin = AR5K_EEPROM_NO_SPUR;
1509         spur_detection_window = AR5K_SPUR_CHAN_WIDTH;
1510         /* XXX: Half/Quarter channels ?*/
1511         if (channel->hw_value & CHANNEL_TURBO)
1512                 spur_detection_window *= 2;
1513
1514         for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
1515                 spur_chan_fbin = ee->ee_spur_chans[i][freq_band];
1516
1517                 /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag
1518                  * so it's zero if we got nothing from EEPROM */
1519                 if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) {
1520                         spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1521                         break;
1522                 }
1523
1524                 if ((chan_fbin - spur_detection_window <=
1525                 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) &&
1526                 (chan_fbin + spur_detection_window >=
1527                 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) {
1528                         spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1529                         break;
1530                 }
1531         }
1532
1533         /* We need to enable spur filter for this channel */
1534         if (spur_chan_fbin) {
1535                 spur_offset = spur_chan_fbin - chan_fbin;
1536                 /*
1537                  * Calculate deltas:
1538                  * spur_freq_sigma_delta -> spur_offset / sample_freq << 21
1539                  * spur_delta_phase -> spur_offset / chip_freq << 11
1540                  * Note: Both values have 100KHz resolution
1541                  */
1542                 /* XXX: Half/Quarter rate channels ? */
1543                 switch (channel->hw_value) {
1544                 case CHANNEL_A:
1545                         /* Both sample_freq and chip_freq are 40MHz */
1546                         spur_delta_phase = (spur_offset << 17) / 25;
1547                         spur_freq_sigma_delta = (spur_delta_phase >> 10);
1548                         symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1549                         break;
1550                 case CHANNEL_G:
1551                         /* sample_freq -> 40MHz chip_freq -> 44MHz
1552                          * (for b compatibility) */
1553                         spur_freq_sigma_delta = (spur_offset << 8) / 55;
1554                         spur_delta_phase = (spur_offset << 17) / 25;
1555                         symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1556                         break;
1557                 case CHANNEL_T:
1558                 case CHANNEL_TG:
1559                         /* Both sample_freq and chip_freq are 80MHz */
1560                         spur_delta_phase = (spur_offset << 16) / 25;
1561                         spur_freq_sigma_delta = (spur_delta_phase >> 10);
1562                         symbol_width = AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz;
1563                         break;
1564                 default:
1565                         return;
1566                 }
1567
1568                 /* Calculate pilot and magnitude masks */
1569
1570                 /* Scale up spur_offset by 1000 to switch to 100HZ resolution
1571                  * and divide by symbol_width to find how many symbols we have
1572                  * Note: number of symbols is scaled up by 16 */
1573                 num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width;
1574
1575                 /* Spur is on a symbol if num_symbols_x16 % 16 is zero */
1576                 if (!(num_symbols_x16 & 0xF))
1577                         /* _X_ */
1578                         num_symbol_offsets = 3;
1579                 else
1580                         /* _xx_ */
1581                         num_symbol_offsets = 4;
1582
1583                 for (i = 0; i < num_symbol_offsets; i++) {
1584
1585                         /* Calculate pilot mask */
1586                         s32 curr_sym_off =
1587                                 (num_symbols_x16 / 16) + i + 25;
1588
1589                         /* Pilot magnitude mask seems to be a way to
1590                          * declare the boundaries for our detection
1591                          * window or something, it's 2 for the middle
1592                          * value(s) where the symbol is expected to be
1593                          * and 1 on the boundary values */
1594                         u8 plt_mag_map =
1595                                 (i == 0 || i == (num_symbol_offsets - 1))
1596                                                                 ? 1 : 2;
1597
1598                         if (curr_sym_off >= 0 && curr_sym_off <= 32) {
1599                                 if (curr_sym_off <= 25)
1600                                         pilot_mask[0] |= 1 << curr_sym_off;
1601                                 else if (curr_sym_off >= 27)
1602                                         pilot_mask[0] |= 1 << (curr_sym_off - 1);
1603                         } else if (curr_sym_off >= 33 && curr_sym_off <= 52)
1604                                 pilot_mask[1] |= 1 << (curr_sym_off - 33);
1605
1606                         /* Calculate magnitude mask (for viterbi decoder) */
1607                         if (curr_sym_off >= -1 && curr_sym_off <= 14)
1608                                 mag_mask[0] |=
1609                                         plt_mag_map << (curr_sym_off + 1) * 2;
1610                         else if (curr_sym_off >= 15 && curr_sym_off <= 30)
1611                                 mag_mask[1] |=
1612                                         plt_mag_map << (curr_sym_off - 15) * 2;
1613                         else if (curr_sym_off >= 31 && curr_sym_off <= 46)
1614                                 mag_mask[2] |=
1615                                         plt_mag_map << (curr_sym_off - 31) * 2;
1616                         else if (curr_sym_off >= 46 && curr_sym_off <= 53)
1617                                 mag_mask[3] |=
1618                                         plt_mag_map << (curr_sym_off - 47) * 2;
1619
1620                 }
1621
1622                 /* Write settings on hw to enable spur filter */
1623                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1624                                         AR5K_PHY_BIN_MASK_CTL_RATE, 0xff);
1625                 /* XXX: Self correlator also ? */
1626                 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
1627                                         AR5K_PHY_IQ_PILOT_MASK_EN |
1628                                         AR5K_PHY_IQ_CHAN_MASK_EN |
1629                                         AR5K_PHY_IQ_SPUR_FILT_EN);
1630
1631                 /* Set delta phase and freq sigma delta */
1632                 ath5k_hw_reg_write(ah,
1633                                 AR5K_REG_SM(spur_delta_phase,
1634                                         AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) |
1635                                 AR5K_REG_SM(spur_freq_sigma_delta,
1636                                 AR5K_PHY_TIMING_11_SPUR_FREQ_SD) |
1637                                 AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC,
1638                                 AR5K_PHY_TIMING_11);
1639
1640                 /* Write pilot masks */
1641                 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7);
1642                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1643                                         AR5K_PHY_TIMING_8_PILOT_MASK_2,
1644                                         pilot_mask[1]);
1645
1646                 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9);
1647                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1648                                         AR5K_PHY_TIMING_10_PILOT_MASK_2,
1649                                         pilot_mask[1]);
1650
1651                 /* Write magnitude masks */
1652                 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1);
1653                 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2);
1654                 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3);
1655                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1656                                         AR5K_PHY_BIN_MASK_CTL_MASK_4,
1657                                         mag_mask[3]);
1658
1659                 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1);
1660                 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2);
1661                 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3);
1662                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1663                                         AR5K_PHY_BIN_MASK2_4_MASK_4,
1664                                         mag_mask[3]);
1665
1666         } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) &
1667         AR5K_PHY_IQ_SPUR_FILT_EN) {
1668                 /* Clean up spur mitigation settings and disable fliter */
1669                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1670                                         AR5K_PHY_BIN_MASK_CTL_RATE, 0);
1671                 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ,
1672                                         AR5K_PHY_IQ_PILOT_MASK_EN |
1673                                         AR5K_PHY_IQ_CHAN_MASK_EN |
1674                                         AR5K_PHY_IQ_SPUR_FILT_EN);
1675                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11);
1676
1677                 /* Clear pilot masks */
1678                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7);
1679                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1680                                         AR5K_PHY_TIMING_8_PILOT_MASK_2,
1681                                         0);
1682
1683                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9);
1684                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1685                                         AR5K_PHY_TIMING_10_PILOT_MASK_2,
1686                                         0);
1687
1688                 /* Clear magnitude masks */
1689                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1);
1690                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2);
1691                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3);
1692                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1693                                         AR5K_PHY_BIN_MASK_CTL_MASK_4,
1694                                         0);
1695
1696                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1);
1697                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2);
1698                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3);
1699                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1700                                         AR5K_PHY_BIN_MASK2_4_MASK_4,
1701                                         0);
1702         }
1703 }
1704
1705 /********************\
1706   Misc PHY functions
1707 \********************/
1708
1709 int ath5k_hw_phy_disable(struct ath5k_hw *ah)
1710 {
1711         ATH5K_TRACE(ah->ah_sc);
1712         /*Just a try M.F.*/
1713         ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
1714
1715         return 0;
1716 }
1717
1718 /*
1719  * Get the PHY Chip revision
1720  */
1721 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
1722 {
1723         unsigned int i;
1724         u32 srev;
1725         u16 ret;
1726
1727         ATH5K_TRACE(ah->ah_sc);
1728
1729         /*
1730          * Set the radio chip access register
1731          */
1732         switch (chan) {
1733         case CHANNEL_2GHZ:
1734                 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
1735                 break;
1736         case CHANNEL_5GHZ:
1737                 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1738                 break;
1739         default:
1740                 return 0;
1741         }
1742
1743         mdelay(2);
1744
1745         /* ...wait until PHY is ready and read the selected radio revision */
1746         ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
1747
1748         for (i = 0; i < 8; i++)
1749                 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
1750
1751         if (ah->ah_version == AR5K_AR5210) {
1752                 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
1753                 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
1754         } else {
1755                 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
1756                 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
1757                                 ((srev & 0x0f) << 4), 8);
1758         }
1759
1760         /* Reset to the 5GHz mode */
1761         ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1762
1763         return ret;
1764 }
1765
1766 /*****************\
1767 * Antenna control *
1768 \*****************/
1769
1770 void /*TODO:Boundary check*/
1771 ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant)
1772 {
1773         ATH5K_TRACE(ah->ah_sc);
1774
1775         if (ah->ah_version != AR5K_AR5210)
1776                 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA);
1777 }
1778
1779 unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah)
1780 {
1781         ATH5K_TRACE(ah->ah_sc);
1782
1783         if (ah->ah_version != AR5K_AR5210)
1784                 return ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA) & 0x7;
1785
1786         return false; /*XXX: What do we return for 5210 ?*/
1787 }
1788
1789 /*
1790  * Enable/disable fast rx antenna diversity
1791  */
1792 static void
1793 ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable)
1794 {
1795         switch (ee_mode) {
1796         case AR5K_EEPROM_MODE_11G:
1797                 /* XXX: This is set to
1798                  * disabled on initvals !!! */
1799         case AR5K_EEPROM_MODE_11A:
1800                 if (enable)
1801                         AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL,
1802                                         AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1803                 else
1804                         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1805                                         AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1806                 break;
1807         case AR5K_EEPROM_MODE_11B:
1808                 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1809                                         AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1810                 break;
1811         default:
1812                 return;
1813         }
1814
1815         if (enable) {
1816                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1817                                 AR5K_PHY_RESTART_DIV_GC, 0xc);
1818
1819                 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1820                                         AR5K_PHY_FAST_ANT_DIV_EN);
1821         } else {
1822                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1823                                 AR5K_PHY_RESTART_DIV_GC, 0x8);
1824
1825                 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1826                                         AR5K_PHY_FAST_ANT_DIV_EN);
1827         }
1828 }
1829
1830 /*
1831  * Set antenna operating mode
1832  */
1833 void
1834 ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
1835 {
1836         struct ieee80211_channel *channel = ah->ah_current_channel;
1837         bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div;
1838         bool use_def_for_sg;
1839         u8 def_ant, tx_ant, ee_mode;
1840         u32 sta_id1 = 0;
1841
1842         def_ant = ah->ah_def_ant;
1843
1844         ATH5K_TRACE(ah->ah_sc);
1845
1846         switch (channel->hw_value & CHANNEL_MODES) {
1847         case CHANNEL_A:
1848         case CHANNEL_T:
1849         case CHANNEL_XR:
1850                 ee_mode = AR5K_EEPROM_MODE_11A;
1851                 break;
1852         case CHANNEL_G:
1853         case CHANNEL_TG:
1854                 ee_mode = AR5K_EEPROM_MODE_11G;
1855                 break;
1856         case CHANNEL_B:
1857                 ee_mode = AR5K_EEPROM_MODE_11B;
1858                 break;
1859         default:
1860                 ATH5K_ERR(ah->ah_sc,
1861                         "invalid channel: %d\n", channel->center_freq);
1862                 return;
1863         }
1864
1865         switch (ant_mode) {
1866         case AR5K_ANTMODE_DEFAULT:
1867                 tx_ant = 0;
1868                 use_def_for_tx = false;
1869                 update_def_on_tx = false;
1870                 use_def_for_rts = false;
1871                 use_def_for_sg = false;
1872                 fast_div = true;
1873                 break;
1874         case AR5K_ANTMODE_FIXED_A:
1875                 def_ant = 1;
1876                 tx_ant = 0;
1877                 use_def_for_tx = true;
1878                 update_def_on_tx = false;
1879                 use_def_for_rts = true;
1880                 use_def_for_sg = true;
1881                 fast_div = false;
1882                 break;
1883         case AR5K_ANTMODE_FIXED_B:
1884                 def_ant = 2;
1885                 tx_ant = 0;
1886                 use_def_for_tx = true;
1887                 update_def_on_tx = false;
1888                 use_def_for_rts = true;
1889                 use_def_for_sg = true;
1890                 fast_div = false;
1891                 break;
1892         case AR5K_ANTMODE_SINGLE_AP:
1893                 def_ant = 1;    /* updated on tx */
1894                 tx_ant = 0;
1895                 use_def_for_tx = true;
1896                 update_def_on_tx = true;
1897                 use_def_for_rts = true;
1898                 use_def_for_sg = true;
1899                 fast_div = true;
1900                 break;
1901         case AR5K_ANTMODE_SECTOR_AP:
1902                 tx_ant = 1;     /* variable */
1903                 use_def_for_tx = false;
1904                 update_def_on_tx = false;
1905                 use_def_for_rts = true;
1906                 use_def_for_sg = false;
1907                 fast_div = false;
1908                 break;
1909         case AR5K_ANTMODE_SECTOR_STA:
1910                 tx_ant = 1;     /* variable */
1911                 use_def_for_tx = true;
1912                 update_def_on_tx = false;
1913                 use_def_for_rts = true;
1914                 use_def_for_sg = false;
1915                 fast_div = true;
1916                 break;
1917         case AR5K_ANTMODE_DEBUG:
1918                 def_ant = 1;
1919                 tx_ant = 2;
1920                 use_def_for_tx = false;
1921                 update_def_on_tx = false;
1922                 use_def_for_rts = false;
1923                 use_def_for_sg = false;
1924                 fast_div = false;
1925                 break;
1926         default:
1927                 return;
1928         }
1929
1930         ah->ah_tx_ant = tx_ant;
1931         ah->ah_ant_mode = ant_mode;
1932
1933         sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0;
1934         sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0;
1935         sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0;
1936         sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0;
1937
1938         AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS);
1939
1940         if (sta_id1)
1941                 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1);
1942
1943         /* Note: set diversity before default antenna
1944          * because it won't work correctly */
1945         ath5k_hw_set_fast_div(ah, ee_mode, fast_div);
1946         ath5k_hw_set_def_antenna(ah, def_ant);
1947 }
1948
1949
1950 /****************\
1951 * TX power setup *
1952 \****************/
1953
1954 /*
1955  * Helper functions
1956  */
1957
1958 /*
1959  * Do linear interpolation between two given (x, y) points
1960  */
1961 static s16
1962 ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right,
1963                                         s16 y_left, s16 y_right)
1964 {
1965         s16 ratio, result;
1966
1967         /* Avoid divide by zero and skip interpolation
1968          * if we have the same point */
1969         if ((x_left == x_right) || (y_left == y_right))
1970                 return y_left;
1971
1972         /*
1973          * Since we use ints and not fps, we need to scale up in
1974          * order to get a sane ratio value (or else we 'll eg. get
1975          * always 1 instead of 1.25, 1.75 etc). We scale up by 100
1976          * to have some accuracy both for 0.5 and 0.25 steps.
1977          */
1978         ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left));
1979
1980         /* Now scale down to be in range */
1981         result = y_left + (ratio * (target - x_left) / 100);
1982
1983         return result;
1984 }
1985
1986 /*
1987  * Find vertical boundary (min pwr) for the linear PCDAC curve.
1988  *
1989  * Since we have the top of the curve and we draw the line below
1990  * until we reach 1 (1 pcdac step) we need to know which point
1991  * (x value) that is so that we don't go below y axis and have negative
1992  * pcdac values when creating the curve, or fill the table with zeroes.
1993  */
1994 static s16
1995 ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR,
1996                                 const s16 *pwrL, const s16 *pwrR)
1997 {
1998         s8 tmp;
1999         s16 min_pwrL, min_pwrR;
2000         s16 pwr_i;
2001
2002         /* Some vendors write the same pcdac value twice !!! */
2003         if (stepL[0] == stepL[1] || stepR[0] == stepR[1])
2004                 return max(pwrL[0], pwrR[0]);
2005
2006         if (pwrL[0] == pwrL[1])
2007                 min_pwrL = pwrL[0];
2008         else {
2009                 pwr_i = pwrL[0];
2010                 do {
2011                         pwr_i--;
2012                         tmp = (s8) ath5k_get_interpolated_value(pwr_i,
2013                                                         pwrL[0], pwrL[1],
2014                                                         stepL[0], stepL[1]);
2015                 } while (tmp > 1);
2016
2017                 min_pwrL = pwr_i;
2018         }
2019
2020         if (pwrR[0] == pwrR[1])
2021                 min_pwrR = pwrR[0];
2022         else {
2023                 pwr_i = pwrR[0];
2024                 do {
2025                         pwr_i--;
2026                         tmp = (s8) ath5k_get_interpolated_value(pwr_i,
2027                                                         pwrR[0], pwrR[1],
2028                                                         stepR[0], stepR[1]);
2029                 } while (tmp > 1);
2030
2031                 min_pwrR = pwr_i;
2032         }
2033
2034         /* Keep the right boundary so that it works for both curves */
2035         return max(min_pwrL, min_pwrR);
2036 }
2037
2038 /*
2039  * Interpolate (pwr,vpd) points to create a Power to PDADC or a
2040  * Power to PCDAC curve.
2041  *
2042  * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC
2043  * steps (offsets) on y axis. Power can go up to 31.5dB and max
2044  * PCDAC/PDADC step for each curve is 64 but we can write more than
2045  * one curves on hw so we can go up to 128 (which is the max step we
2046  * can write on the final table).
2047  *
2048  * We write y values (PCDAC/PDADC steps) on hw.
2049  */
2050 static void
2051 ath5k_create_power_curve(s16 pmin, s16 pmax,
2052                         const s16 *pwr, const u8 *vpd,
2053                         u8 num_points,
2054                         u8 *vpd_table, u8 type)
2055 {
2056         u8 idx[2] = { 0, 1 };
2057         s16 pwr_i = 2*pmin;
2058         int i;
2059
2060         if (num_points < 2)
2061                 return;
2062
2063         /* We want the whole line, so adjust boundaries
2064          * to cover the entire power range. Note that
2065          * power values are already 0.25dB so no need
2066          * to multiply pwr_i by 2 */
2067         if (type == AR5K_PWRTABLE_LINEAR_PCDAC) {
2068                 pwr_i = pmin;
2069                 pmin = 0;
2070                 pmax = 63;
2071         }
2072
2073         /* Find surrounding turning points (TPs)
2074          * and interpolate between them */
2075         for (i = 0; (i <= (u16) (pmax - pmin)) &&
2076         (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2077
2078                 /* We passed the right TP, move to the next set of TPs
2079                  * if we pass the last TP, extrapolate above using the last
2080                  * two TPs for ratio */
2081                 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) {
2082                         idx[0]++;
2083                         idx[1]++;
2084                 }
2085
2086                 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i,
2087                                                 pwr[idx[0]], pwr[idx[1]],
2088                                                 vpd[idx[0]], vpd[idx[1]]);
2089
2090                 /* Increase by 0.5dB
2091                  * (0.25 dB units) */
2092                 pwr_i += 2;
2093         }
2094 }
2095
2096 /*
2097  * Get the surrounding per-channel power calibration piers
2098  * for a given frequency so that we can interpolate between
2099  * them and come up with an apropriate dataset for our current
2100  * channel.
2101  */
2102 static void
2103 ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah,
2104                         struct ieee80211_channel *channel,
2105                         struct ath5k_chan_pcal_info **pcinfo_l,
2106                         struct ath5k_chan_pcal_info **pcinfo_r)
2107 {
2108         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2109         struct ath5k_chan_pcal_info *pcinfo;
2110         u8 idx_l, idx_r;
2111         u8 mode, max, i;
2112         u32 target = channel->center_freq;
2113
2114         idx_l = 0;
2115         idx_r = 0;
2116
2117         if (!(channel->hw_value & CHANNEL_OFDM)) {
2118                 pcinfo = ee->ee_pwr_cal_b;
2119                 mode = AR5K_EEPROM_MODE_11B;
2120         } else if (channel->hw_value & CHANNEL_2GHZ) {
2121                 pcinfo = ee->ee_pwr_cal_g;
2122                 mode = AR5K_EEPROM_MODE_11G;
2123         } else {
2124                 pcinfo = ee->ee_pwr_cal_a;
2125                 mode = AR5K_EEPROM_MODE_11A;
2126         }
2127         max = ee->ee_n_piers[mode] - 1;
2128
2129         /* Frequency is below our calibrated
2130          * range. Use the lowest power curve
2131          * we have */
2132         if (target < pcinfo[0].freq) {
2133                 idx_l = idx_r = 0;
2134                 goto done;
2135         }
2136
2137         /* Frequency is above our calibrated
2138          * range. Use the highest power curve
2139          * we have */
2140         if (target > pcinfo[max].freq) {
2141                 idx_l = idx_r = max;
2142                 goto done;
2143         }
2144
2145         /* Frequency is inside our calibrated
2146          * channel range. Pick the surrounding
2147          * calibration piers so that we can
2148          * interpolate */
2149         for (i = 0; i <= max; i++) {
2150
2151                 /* Frequency matches one of our calibration
2152                  * piers, no need to interpolate, just use
2153                  * that calibration pier */
2154                 if (pcinfo[i].freq == target) {
2155                         idx_l = idx_r = i;
2156                         goto done;
2157                 }
2158
2159                 /* We found a calibration pier that's above
2160                  * frequency, use this pier and the previous
2161                  * one to interpolate */
2162                 if (target < pcinfo[i].freq) {
2163                         idx_r = i;
2164                         idx_l = idx_r - 1;
2165                         goto done;
2166                 }
2167         }
2168
2169 done:
2170         *pcinfo_l = &pcinfo[idx_l];
2171         *pcinfo_r = &pcinfo[idx_r];
2172
2173         return;
2174 }
2175
2176 /*
2177  * Get the surrounding per-rate power calibration data
2178  * for a given frequency and interpolate between power
2179  * values to set max target power supported by hw for
2180  * each rate.
2181  */
2182 static void
2183 ath5k_get_rate_pcal_data(struct ath5k_hw *ah,
2184                         struct ieee80211_channel *channel,
2185                         struct ath5k_rate_pcal_info *rates)
2186 {
2187         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2188         struct ath5k_rate_pcal_info *rpinfo;
2189         u8 idx_l, idx_r;
2190         u8 mode, max, i;
2191         u32 target = channel->center_freq;
2192
2193         idx_l = 0;
2194         idx_r = 0;
2195
2196         if (!(channel->hw_value & CHANNEL_OFDM)) {
2197                 rpinfo = ee->ee_rate_tpwr_b;
2198                 mode = AR5K_EEPROM_MODE_11B;
2199         } else if (channel->hw_value & CHANNEL_2GHZ) {
2200                 rpinfo = ee->ee_rate_tpwr_g;
2201                 mode = AR5K_EEPROM_MODE_11G;
2202         } else {
2203                 rpinfo = ee->ee_rate_tpwr_a;
2204                 mode = AR5K_EEPROM_MODE_11A;
2205         }
2206         max = ee->ee_rate_target_pwr_num[mode] - 1;
2207
2208         /* Get the surrounding calibration
2209          * piers - same as above */
2210         if (target < rpinfo[0].freq) {
2211                 idx_l = idx_r = 0;
2212                 goto done;
2213         }
2214
2215         if (target > rpinfo[max].freq) {
2216                 idx_l = idx_r = max;
2217                 goto done;
2218         }
2219
2220         for (i = 0; i <= max; i++) {
2221
2222                 if (rpinfo[i].freq == target) {
2223                         idx_l = idx_r = i;
2224                         goto done;
2225                 }
2226
2227                 if (target < rpinfo[i].freq) {
2228                         idx_r = i;
2229                         idx_l = idx_r - 1;
2230                         goto done;
2231                 }
2232         }
2233
2234 done:
2235         /* Now interpolate power value, based on the frequency */
2236         rates->freq = target;
2237
2238         rates->target_power_6to24 =
2239                 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2240                                         rpinfo[idx_r].freq,
2241                                         rpinfo[idx_l].target_power_6to24,
2242                                         rpinfo[idx_r].target_power_6to24);
2243
2244         rates->target_power_36 =
2245                 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2246                                         rpinfo[idx_r].freq,
2247                                         rpinfo[idx_l].target_power_36,
2248                                         rpinfo[idx_r].target_power_36);
2249
2250         rates->target_power_48 =
2251                 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2252                                         rpinfo[idx_r].freq,
2253                                         rpinfo[idx_l].target_power_48,
2254                                         rpinfo[idx_r].target_power_48);
2255
2256         rates->target_power_54 =
2257                 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2258                                         rpinfo[idx_r].freq,
2259                                         rpinfo[idx_l].target_power_54,
2260                                         rpinfo[idx_r].target_power_54);
2261 }
2262
2263 /*
2264  * Get the max edge power for this channel if
2265  * we have such data from EEPROM's Conformance Test
2266  * Limits (CTL), and limit max power if needed.
2267  */
2268 static void
2269 ath5k_get_max_ctl_power(struct ath5k_hw *ah,
2270                         struct ieee80211_channel *channel)
2271 {
2272         struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2273         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2274         struct ath5k_edge_power *rep = ee->ee_ctl_pwr;
2275         u8 *ctl_val = ee->ee_ctl;
2276         s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4;
2277         s16 edge_pwr = 0;
2278         u8 rep_idx;
2279         u8 i, ctl_mode;
2280         u8 ctl_idx = 0xFF;
2281         u32 target = channel->center_freq;
2282
2283         ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band);
2284
2285         switch (channel->hw_value & CHANNEL_MODES) {
2286         case CHANNEL_A:
2287                 ctl_mode |= AR5K_CTL_11A;
2288                 break;
2289         case CHANNEL_G:
2290                 ctl_mode |= AR5K_CTL_11G;
2291                 break;
2292         case CHANNEL_B:
2293                 ctl_mode |= AR5K_CTL_11B;
2294                 break;
2295         case CHANNEL_T:
2296                 ctl_mode |= AR5K_CTL_TURBO;
2297                 break;
2298         case CHANNEL_TG:
2299                 ctl_mode |= AR5K_CTL_TURBOG;
2300                 break;
2301         case CHANNEL_XR:
2302                 /* Fall through */
2303         default:
2304                 return;
2305         }
2306
2307         for (i = 0; i < ee->ee_ctls; i++) {
2308                 if (ctl_val[i] == ctl_mode) {
2309                         ctl_idx = i;
2310                         break;
2311                 }
2312         }
2313
2314         /* If we have a CTL dataset available grab it and find the
2315          * edge power for our frequency */
2316         if (ctl_idx == 0xFF)
2317                 return;
2318
2319         /* Edge powers are sorted by frequency from lower
2320          * to higher. Each CTL corresponds to 8 edge power
2321          * measurements. */
2322         rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES;
2323
2324         /* Don't do boundaries check because we
2325          * might have more that one bands defined
2326          * for this mode */
2327
2328         /* Get the edge power that's closer to our
2329          * frequency */
2330         for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) {
2331                 rep_idx += i;
2332                 if (target <= rep[rep_idx].freq)
2333                         edge_pwr = (s16) rep[rep_idx].edge;
2334         }
2335
2336         if (edge_pwr)
2337                 ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr);
2338 }
2339
2340
2341 /*
2342  * Power to PCDAC table functions
2343  */
2344
2345 /*
2346  * Fill Power to PCDAC table on RF5111
2347  *
2348  * No further processing is needed for RF5111, the only thing we have to
2349  * do is fill the values below and above calibration range since eeprom data
2350  * may not cover the entire PCDAC table.
2351  */
2352 static void
2353 ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min,
2354                                                         s16 *table_max)
2355 {
2356         u8      *pcdac_out = ah->ah_txpower.txp_pd_table;
2357         u8      *pcdac_tmp = ah->ah_txpower.tmpL[0];
2358         u8      pcdac_0, pcdac_n, pcdac_i, pwr_idx, i;
2359         s16     min_pwr, max_pwr;
2360
2361         /* Get table boundaries */
2362         min_pwr = table_min[0];
2363         pcdac_0 = pcdac_tmp[0];
2364
2365         max_pwr = table_max[0];
2366         pcdac_n = pcdac_tmp[table_max[0] - table_min[0]];
2367
2368         /* Extrapolate below minimum using pcdac_0 */
2369         pcdac_i = 0;
2370         for (i = 0; i < min_pwr; i++)
2371                 pcdac_out[pcdac_i++] = pcdac_0;
2372
2373         /* Copy values from pcdac_tmp */
2374         pwr_idx = min_pwr;
2375         for (i = 0 ; pwr_idx <= max_pwr &&
2376         pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) {
2377                 pcdac_out[pcdac_i++] = pcdac_tmp[i];
2378                 pwr_idx++;
2379         }
2380
2381         /* Extrapolate above maximum */
2382         while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE)
2383                 pcdac_out[pcdac_i++] = pcdac_n;
2384
2385 }
2386
2387 /*
2388  * Combine available XPD Curves and fill Linear Power to PCDAC table
2389  * on RF5112
2390  *
2391  * RFX112 can have up to 2 curves (one for low txpower range and one for
2392  * higher txpower range). We need to put them both on pcdac_out and place
2393  * them in the correct location. In case we only have one curve available
2394  * just fit it on pcdac_out (it's supposed to cover the entire range of
2395  * available pwr levels since it's always the higher power curve). Extrapolate
2396  * below and above final table if needed.
2397  */
2398 static void
2399 ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
2400                                                 s16 *table_max, u8 pdcurves)
2401 {
2402         u8      *pcdac_out = ah->ah_txpower.txp_pd_table;
2403         u8      *pcdac_low_pwr;
2404         u8      *pcdac_high_pwr;
2405         u8      *pcdac_tmp;
2406         u8      pwr;
2407         s16     max_pwr_idx;
2408         s16     min_pwr_idx;
2409         s16     mid_pwr_idx = 0;
2410         /* Edge flag turs on the 7nth bit on the PCDAC
2411          * to delcare the higher power curve (force values
2412          * to be greater than 64). If we only have one curve
2413          * we don't need to set this, if we have 2 curves and
2414          * fill the table backwards this can also be used to
2415          * switch from higher power curve to lower power curve */
2416         u8      edge_flag;
2417         int     i;
2418
2419         /* When we have only one curve available
2420          * that's the higher power curve. If we have
2421          * two curves the first is the high power curve
2422          * and the next is the low power curve. */
2423         if (pdcurves > 1) {
2424                 pcdac_low_pwr = ah->ah_txpower.tmpL[1];
2425                 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2426                 mid_pwr_idx = table_max[1] - table_min[1] - 1;
2427                 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2428
2429                 /* If table size goes beyond 31.5dB, keep the
2430                  * upper 31.5dB range when setting tx power.
2431                  * Note: 126 = 31.5 dB in quarter dB steps */
2432                 if (table_max[0] - table_min[1] > 126)
2433                         min_pwr_idx = table_max[0] - 126;
2434                 else
2435                         min_pwr_idx = table_min[1];
2436
2437                 /* Since we fill table backwards
2438                  * start from high power curve */
2439                 pcdac_tmp = pcdac_high_pwr;
2440
2441                 edge_flag = 0x40;
2442 #if 0
2443                 /* If both min and max power limits are in lower
2444                  * power curve's range, only use the low power curve.
2445                  * TODO: min/max levels are related to target
2446                  * power values requested from driver/user
2447                  * XXX: Is this really needed ? */
2448                 if (min_pwr < table_max[1] &&
2449                 max_pwr < table_max[1]) {
2450                         edge_flag = 0;
2451                         pcdac_tmp = pcdac_low_pwr;
2452                         max_pwr_idx = (table_max[1] - table_min[1])/2;
2453                 }
2454 #endif
2455         } else {
2456                 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */
2457                 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2458                 min_pwr_idx = table_min[0];
2459                 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2460                 pcdac_tmp = pcdac_high_pwr;
2461                 edge_flag = 0;
2462         }
2463
2464         /* This is used when setting tx power*/
2465         ah->ah_txpower.txp_min_idx = min_pwr_idx/2;
2466
2467         /* Fill Power to PCDAC table backwards */
2468         pwr = max_pwr_idx;
2469         for (i = 63; i >= 0; i--) {
2470                 /* Entering lower power range, reset
2471                  * edge flag and set pcdac_tmp to lower
2472                  * power curve.*/
2473                 if (edge_flag == 0x40 &&
2474                 (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) {
2475                         edge_flag = 0x00;
2476                         pcdac_tmp = pcdac_low_pwr;
2477                         pwr = mid_pwr_idx/2;
2478                 }
2479
2480                 /* Don't go below 1, extrapolate below if we have
2481                  * already swithced to the lower power curve -or
2482                  * we only have one curve and edge_flag is zero
2483                  * anyway */
2484                 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) {
2485                         while (i >= 0) {
2486                                 pcdac_out[i] = pcdac_out[i + 1];
2487                                 i--;
2488                         }
2489                         break;
2490                 }
2491
2492                 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag;
2493
2494                 /* Extrapolate above if pcdac is greater than
2495                  * 126 -this can happen because we OR pcdac_out
2496                  * value with edge_flag on high power curve */
2497                 if (pcdac_out[i] > 126)
2498                         pcdac_out[i] = 126;
2499
2500                 /* Decrease by a 0.5dB step */
2501                 pwr--;
2502         }
2503 }
2504
2505 /* Write PCDAC values on hw */
2506 static void
2507 ath5k_setup_pcdac_table(struct ath5k_hw *ah)
2508 {
2509         u8      *pcdac_out = ah->ah_txpower.txp_pd_table;
2510         int     i;
2511
2512         /*
2513          * Write TX power values
2514          */
2515         for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2516                 ath5k_hw_reg_write(ah,
2517                         (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) |
2518                         (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16),
2519                         AR5K_PHY_PCDAC_TXPOWER(i));
2520         }
2521 }
2522
2523
2524 /*
2525  * Power to PDADC table functions
2526  */
2527
2528 /*
2529  * Set the gain boundaries and create final Power to PDADC table
2530  *
2531  * We can have up to 4 pd curves, we need to do a simmilar process
2532  * as we do for RF5112. This time we don't have an edge_flag but we
2533  * set the gain boundaries on a separate register.
2534  */
2535 static void
2536 ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah,
2537                         s16 *pwr_min, s16 *pwr_max, u8 pdcurves)
2538 {
2539         u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS];
2540         u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2541         u8 *pdadc_tmp;
2542         s16 pdadc_0;
2543         u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size;
2544         u8 pd_gain_overlap;
2545
2546         /* Note: Register value is initialized on initvals
2547          * there is no feedback from hw.
2548          * XXX: What about pd_gain_overlap from EEPROM ? */
2549         pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) &
2550                 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP;
2551
2552         /* Create final PDADC table */
2553         for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) {
2554                 pdadc_tmp = ah->ah_txpower.tmpL[pdg];
2555
2556                 if (pdg == pdcurves - 1)
2557                         /* 2 dB boundary stretch for last
2558                          * (higher power) curve */
2559                         gain_boundaries[pdg] = pwr_max[pdg] + 4;
2560                 else
2561                         /* Set gain boundary in the middle
2562                          * between this curve and the next one */
2563                         gain_boundaries[pdg] =
2564                                 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2;
2565
2566                 /* Sanity check in case our 2 db stretch got out of
2567                  * range. */
2568                 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER)
2569                         gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER;
2570
2571                 /* For the first curve (lower power)
2572                  * start from 0 dB */
2573                 if (pdg == 0)
2574                         pdadc_0 = 0;
2575                 else
2576                         /* For the other curves use the gain overlap */
2577                         pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) -
2578                                                         pd_gain_overlap;
2579
2580                 /* Force each power step to be at least 0.5 dB */
2581                 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1)
2582                         pwr_step = pdadc_tmp[1] - pdadc_tmp[0];
2583                 else
2584                         pwr_step = 1;
2585
2586                 /* If pdadc_0 is negative, we need to extrapolate
2587                  * below this pdgain by a number of pwr_steps */
2588                 while ((pdadc_0 < 0) && (pdadc_i < 128)) {
2589                         s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step;
2590                         pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp;
2591                         pdadc_0++;
2592                 }
2593
2594                 /* Set last pwr level, using gain boundaries */
2595                 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg];
2596                 /* Limit it to be inside pwr range */
2597                 table_size = pwr_max[pdg] - pwr_min[pdg];
2598                 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size;
2599
2600                 /* Fill pdadc_out table */
2601                 while (pdadc_0 < max_idx)
2602                         pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++];
2603
2604                 /* Need to extrapolate above this pdgain? */
2605                 if (pdadc_n <= max_idx)
2606                         continue;
2607
2608                 /* Force each power step to be at least 0.5 dB */
2609                 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1)
2610                         pwr_step = pdadc_tmp[table_size - 1] -
2611                                                 pdadc_tmp[table_size - 2];
2612                 else
2613                         pwr_step = 1;
2614
2615                 /* Extrapolate above */
2616                 while ((pdadc_0 < (s16) pdadc_n) &&
2617                 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) {
2618                         s16 tmp = pdadc_tmp[table_size - 1] +
2619                                         (pdadc_0 - max_idx) * pwr_step;
2620                         pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp;
2621                         pdadc_0++;
2622                 }
2623         }
2624
2625         while (pdg < AR5K_EEPROM_N_PD_GAINS) {
2626                 gain_boundaries[pdg] = gain_boundaries[pdg - 1];
2627                 pdg++;
2628         }
2629
2630         while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) {
2631                 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1];
2632                 pdadc_i++;
2633         }
2634
2635         /* Set gain boundaries */
2636         ath5k_hw_reg_write(ah,
2637                 AR5K_REG_SM(pd_gain_overlap,
2638                         AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) |
2639                 AR5K_REG_SM(gain_boundaries[0],
2640                         AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) |
2641                 AR5K_REG_SM(gain_boundaries[1],
2642                         AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) |
2643                 AR5K_REG_SM(gain_boundaries[2],
2644                         AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) |
2645                 AR5K_REG_SM(gain_boundaries[3],
2646                         AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4),
2647                 AR5K_PHY_TPC_RG5);
2648
2649         /* Used for setting rate power table */
2650         ah->ah_txpower.txp_min_idx = pwr_min[0];
2651
2652 }
2653
2654 /* Write PDADC values on hw */
2655 static void
2656 ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah,
2657                         u8 pdcurves, u8 *pdg_to_idx)
2658 {
2659         u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2660         u32 reg;
2661         u8 i;
2662
2663         /* Select the right pdgain curves */
2664
2665         /* Clear current settings */
2666         reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1);
2667         reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 |
2668                 AR5K_PHY_TPC_RG1_PDGAIN_2 |
2669                 AR5K_PHY_TPC_RG1_PDGAIN_3 |
2670                 AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2671
2672         /*
2673          * Use pd_gains curve from eeprom
2674          *
2675          * This overrides the default setting from initvals
2676          * in case some vendors (e.g. Zcomax) don't use the default
2677          * curves. If we don't honor their settings we 'll get a
2678          * 5dB (1 * gain overlap ?) drop.
2679          */
2680         reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2681
2682         switch (pdcurves) {
2683         case 3:
2684                 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3);
2685                 /* Fall through */
2686         case 2:
2687                 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2);
2688                 /* Fall through */
2689         case 1:
2690                 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1);
2691                 break;
2692         }
2693         ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1);
2694
2695         /*
2696          * Write TX power values
2697          */
2698         for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2699                 ath5k_hw_reg_write(ah,
2700                         ((pdadc_out[4*i + 0] & 0xff) << 0) |
2701                         ((pdadc_out[4*i + 1] & 0xff) << 8) |
2702                         ((pdadc_out[4*i + 2] & 0xff) << 16) |
2703                         ((pdadc_out[4*i + 3] & 0xff) << 24),
2704                         AR5K_PHY_PDADC_TXPOWER(i));
2705         }
2706 }
2707
2708
2709 /*
2710  * Common code for PCDAC/PDADC tables
2711  */
2712
2713 /*
2714  * This is the main function that uses all of the above
2715  * to set PCDAC/PDADC table on hw for the current channel.
2716  * This table is used for tx power calibration on the basband,
2717  * without it we get weird tx power levels and in some cases
2718  * distorted spectral mask
2719  */
2720 static int
2721 ath5k_setup_channel_powertable(struct ath5k_hw *ah,
2722                         struct ieee80211_channel *channel,
2723                         u8 ee_mode, u8 type)
2724 {
2725         struct ath5k_pdgain_info *pdg_L, *pdg_R;
2726         struct ath5k_chan_pcal_info *pcinfo_L;
2727         struct ath5k_chan_pcal_info *pcinfo_R;
2728         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2729         u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
2730         s16 table_min[AR5K_EEPROM_N_PD_GAINS];
2731         s16 table_max[AR5K_EEPROM_N_PD_GAINS];
2732         u8 *tmpL;
2733         u8 *tmpR;
2734         u32 target = channel->center_freq;
2735         int pdg, i;
2736
2737         /* Get surounding freq piers for this channel */
2738         ath5k_get_chan_pcal_surrounding_piers(ah, channel,
2739                                                 &pcinfo_L,
2740                                                 &pcinfo_R);
2741
2742         /* Loop over pd gain curves on
2743          * surounding freq piers by index */
2744         for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) {
2745
2746                 /* Fill curves in reverse order
2747                  * from lower power (max gain)
2748                  * to higher power. Use curve -> idx
2749                  * backmapping we did on eeprom init */
2750                 u8 idx = pdg_curve_to_idx[pdg];
2751
2752                 /* Grab the needed curves by index */
2753                 pdg_L = &pcinfo_L->pd_curves[idx];
2754                 pdg_R = &pcinfo_R->pd_curves[idx];
2755
2756                 /* Initialize the temp tables */
2757                 tmpL = ah->ah_txpower.tmpL[pdg];
2758                 tmpR = ah->ah_txpower.tmpR[pdg];
2759
2760                 /* Set curve's x boundaries and create
2761                  * curves so that they cover the same
2762                  * range (if we don't do that one table
2763                  * will have values on some range and the
2764                  * other one won't have any so interpolation
2765                  * will fail) */
2766                 table_min[pdg] = min(pdg_L->pd_pwr[0],
2767                                         pdg_R->pd_pwr[0]) / 2;
2768
2769                 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2770                                 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2;
2771
2772                 /* Now create the curves on surrounding channels
2773                  * and interpolate if needed to get the final
2774                  * curve for this gain on this channel */
2775                 switch (type) {
2776                 case AR5K_PWRTABLE_LINEAR_PCDAC:
2777                         /* Override min/max so that we don't loose
2778                          * accuracy (don't divide by 2) */
2779                         table_min[pdg] = min(pdg_L->pd_pwr[0],
2780                                                 pdg_R->pd_pwr[0]);
2781
2782                         table_max[pdg] =
2783                                 max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2784                                         pdg_R->pd_pwr[pdg_R->pd_points - 1]);
2785
2786                         /* Override minimum so that we don't get
2787                          * out of bounds while extrapolating
2788                          * below. Don't do this when we have 2
2789                          * curves and we are on the high power curve
2790                          * because table_min is ok in this case */
2791                         if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) {
2792
2793                                 table_min[pdg] =
2794                                         ath5k_get_linear_pcdac_min(pdg_L->pd_step,
2795                                                                 pdg_R->pd_step,
2796                                                                 pdg_L->pd_pwr,
2797                                                                 pdg_R->pd_pwr);
2798
2799                                 /* Don't go too low because we will
2800                                  * miss the upper part of the curve.
2801                                  * Note: 126 = 31.5dB (max power supported)
2802                                  * in 0.25dB units */
2803                                 if (table_max[pdg] - table_min[pdg] > 126)
2804                                         table_min[pdg] = table_max[pdg] - 126;
2805                         }
2806
2807                         /* Fall through */
2808                 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2809                 case AR5K_PWRTABLE_PWR_TO_PDADC:
2810
2811                         ath5k_create_power_curve(table_min[pdg],
2812                                                 table_max[pdg],
2813                                                 pdg_L->pd_pwr,
2814                                                 pdg_L->pd_step,
2815                                                 pdg_L->pd_points, tmpL, type);
2816
2817                         /* We are in a calibration
2818                          * pier, no need to interpolate
2819                          * between freq piers */
2820                         if (pcinfo_L == pcinfo_R)
2821                                 continue;
2822
2823                         ath5k_create_power_curve(table_min[pdg],
2824                                                 table_max[pdg],
2825                                                 pdg_R->pd_pwr,
2826                                                 pdg_R->pd_step,
2827                                                 pdg_R->pd_points, tmpR, type);
2828                         break;
2829                 default:
2830                         return -EINVAL;
2831                 }
2832
2833                 /* Interpolate between curves
2834                  * of surounding freq piers to
2835                  * get the final curve for this
2836                  * pd gain. Re-use tmpL for interpolation
2837                  * output */
2838                 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) &&
2839                 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2840                         tmpL[i] = (u8) ath5k_get_interpolated_value(target,
2841                                                         (s16) pcinfo_L->freq,
2842                                                         (s16) pcinfo_R->freq,
2843                                                         (s16) tmpL[i],
2844                                                         (s16) tmpR[i]);
2845                 }
2846         }
2847
2848         /* Now we have a set of curves for this
2849          * channel on tmpL (x range is table_max - table_min
2850          * and y values are tmpL[pdg][]) sorted in the same
2851          * order as EEPROM (because we've used the backmapping).
2852          * So for RF5112 it's from higher power to lower power
2853          * and for RF2413 it's from lower power to higher power.
2854          * For RF5111 we only have one curve. */
2855
2856         /* Fill min and max power levels for this
2857          * channel by interpolating the values on
2858          * surounding channels to complete the dataset */
2859         ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target,
2860                                         (s16) pcinfo_L->freq,
2861                                         (s16) pcinfo_R->freq,
2862                                         pcinfo_L->min_pwr, pcinfo_R->min_pwr);
2863
2864         ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target,
2865                                         (s16) pcinfo_L->freq,
2866                                         (s16) pcinfo_R->freq,
2867                                         pcinfo_L->max_pwr, pcinfo_R->max_pwr);
2868
2869         /* We are ready to go, fill PCDAC/PDADC
2870          * table and write settings on hardware */
2871         switch (type) {
2872         case AR5K_PWRTABLE_LINEAR_PCDAC:
2873                 /* For RF5112 we can have one or two curves
2874                  * and each curve covers a certain power lvl
2875                  * range so we need to do some more processing */
2876                 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max,
2877                                                 ee->ee_pd_gains[ee_mode]);
2878
2879                 /* Set txp.offset so that we can
2880                  * match max power value with max
2881                  * table index */
2882                 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2);
2883
2884                 /* Write settings on hw */
2885                 ath5k_setup_pcdac_table(ah);
2886                 break;
2887         case AR5K_PWRTABLE_PWR_TO_PCDAC:
2888                 /* We are done for RF5111 since it has only
2889                  * one curve, just fit the curve on the table */
2890                 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max);
2891
2892                 /* No rate powertable adjustment for RF5111 */
2893                 ah->ah_txpower.txp_min_idx = 0;
2894                 ah->ah_txpower.txp_offset = 0;
2895
2896                 /* Write settings on hw */
2897                 ath5k_setup_pcdac_table(ah);
2898                 break;
2899         case AR5K_PWRTABLE_PWR_TO_PDADC:
2900                 /* Set PDADC boundaries and fill
2901                  * final PDADC table */
2902                 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max,
2903                                                 ee->ee_pd_gains[ee_mode]);
2904
2905                 /* Write settings on hw */
2906                 ath5k_setup_pwr_to_pdadc_table(ah, pdg, pdg_curve_to_idx);
2907
2908                 /* Set txp.offset, note that table_min
2909                  * can be negative */
2910                 ah->ah_txpower.txp_offset = table_min[0];
2911                 break;
2912         default:
2913                 return -EINVAL;
2914         }
2915
2916         return 0;
2917 }
2918
2919
2920 /*
2921  * Per-rate tx power setting
2922  *
2923  * This is the code that sets the desired tx power (below
2924  * maximum) on hw for each rate (we also have TPC that sets
2925  * power per packet). We do that by providing an index on the
2926  * PCDAC/PDADC table we set up.
2927  */
2928
2929 /*
2930  * Set rate power table
2931  *
2932  * For now we only limit txpower based on maximum tx power
2933  * supported by hw (what's inside rate_info). We need to limit
2934  * this even more, based on regulatory domain etc.
2935  *
2936  * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps)
2937  * and is indexed as follows:
2938  * rates[0] - rates[7] -> OFDM rates
2939  * rates[8] - rates[14] -> CCK rates
2940  * rates[15] -> XR rates (they all have the same power)
2941  */
2942 static void
2943 ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
2944                         struct ath5k_rate_pcal_info *rate_info,
2945                         u8 ee_mode)
2946 {
2947         unsigned int i;
2948         u16 *rates;
2949
2950         /* max_pwr is power level we got from driver/user in 0.5dB
2951          * units, switch to 0.25dB units so we can compare */
2952         max_pwr *= 2;
2953         max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2;
2954
2955         /* apply rate limits */
2956         rates = ah->ah_txpower.txp_rates_power_table;
2957
2958         /* OFDM rates 6 to 24Mb/s */
2959         for (i = 0; i < 5; i++)
2960                 rates[i] = min(max_pwr, rate_info->target_power_6to24);
2961
2962         /* Rest OFDM rates */
2963         rates[5] = min(rates[0], rate_info->target_power_36);
2964         rates[6] = min(rates[0], rate_info->target_power_48);
2965         rates[7] = min(rates[0], rate_info->target_power_54);
2966
2967         /* CCK rates */
2968         /* 1L */
2969         rates[8] = min(rates[0], rate_info->target_power_6to24);
2970         /* 2L */
2971         rates[9] = min(rates[0], rate_info->target_power_36);
2972         /* 2S */
2973         rates[10] = min(rates[0], rate_info->target_power_36);
2974         /* 5L */
2975         rates[11] = min(rates[0], rate_info->target_power_48);
2976         /* 5S */
2977         rates[12] = min(rates[0], rate_info->target_power_48);
2978         /* 11L */
2979         rates[13] = min(rates[0], rate_info->target_power_54);
2980         /* 11S */
2981         rates[14] = min(rates[0], rate_info->target_power_54);
2982
2983         /* XR rates */
2984         rates[15] = min(rates[0], rate_info->target_power_6to24);
2985
2986         /* CCK rates have different peak to average ratio
2987          * so we have to tweak their power so that gainf
2988          * correction works ok. For this we use OFDM to
2989          * CCK delta from eeprom */
2990         if ((ee_mode == AR5K_EEPROM_MODE_11G) &&
2991         (ah->ah_phy_revision < AR5K_SREV_PHY_5212A))
2992                 for (i = 8; i <= 15; i++)
2993                         rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta;
2994
2995         /* Now that we have all rates setup use table offset to
2996          * match the power range set by user with the power indices
2997          * on PCDAC/PDADC table */
2998         for (i = 0; i < 16; i++) {
2999                 rates[i] += ah->ah_txpower.txp_offset;
3000                 /* Don't get out of bounds */
3001                 if (rates[i] > 63)
3002                         rates[i] = 63;
3003         }
3004
3005         /* Min/max in 0.25dB units */
3006         ah->ah_txpower.txp_min_pwr = 2 * rates[7];
3007         ah->ah_txpower.txp_max_pwr = 2 * rates[0];
3008         ah->ah_txpower.txp_ofdm = rates[7];
3009 }
3010
3011
3012 /*
3013  * Set transmition power
3014  */
3015 int
3016 ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
3017                 u8 ee_mode, u8 txpower)
3018 {
3019         struct ath5k_rate_pcal_info rate_info;
3020         u8 type;
3021         int ret;
3022
3023         ATH5K_TRACE(ah->ah_sc);
3024         if (txpower > AR5K_TUNE_MAX_TXPOWER) {
3025                 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower);
3026                 return -EINVAL;
3027         }
3028
3029         /* Reset TX power values */
3030         memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
3031         ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
3032         ah->ah_txpower.txp_min_pwr = 0;
3033         ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER;
3034
3035         /* Initialize TX power table */
3036         switch (ah->ah_radio) {
3037         case AR5K_RF5111:
3038                 type = AR5K_PWRTABLE_PWR_TO_PCDAC;
3039                 break;
3040         case AR5K_RF5112:
3041                 type = AR5K_PWRTABLE_LINEAR_PCDAC;
3042                 break;
3043         case AR5K_RF2413:
3044         case AR5K_RF5413:
3045         case AR5K_RF2316:
3046         case AR5K_RF2317:
3047         case AR5K_RF2425:
3048                 type = AR5K_PWRTABLE_PWR_TO_PDADC;
3049                 break;
3050         default:
3051                 return -EINVAL;
3052         }
3053
3054         /* FIXME: Only on channel/mode change */
3055         ret = ath5k_setup_channel_powertable(ah, channel, ee_mode, type);
3056         if (ret)
3057                 return ret;
3058
3059         /* Limit max power if we have a CTL available */
3060         ath5k_get_max_ctl_power(ah, channel);
3061
3062         /* FIXME: Tx power limit for this regdomain
3063          * XXX: Mac80211/CRDA will do that anyway ? */
3064
3065         /* FIXME: Antenna reduction stuff */
3066
3067         /* FIXME: Limit power on turbo modes */
3068
3069         /* FIXME: TPC scale reduction */
3070
3071         /* Get surounding channels for per-rate power table
3072          * calibration */
3073         ath5k_get_rate_pcal_data(ah, channel, &rate_info);
3074
3075         /* Setup rate power table */
3076         ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode);
3077
3078         /* Write rate power table on hw */
3079         ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
3080                 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
3081                 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
3082
3083         ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
3084                 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
3085                 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
3086
3087         ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
3088                 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
3089                 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
3090
3091         ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
3092                 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
3093                 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
3094
3095         /* FIXME: TPC support */
3096         if (ah->ah_txpower.txp_tpc) {
3097                 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
3098                         AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
3099
3100                 ath5k_hw_reg_write(ah,
3101                         AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) |
3102                         AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) |
3103                         AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP),
3104                         AR5K_TPC);
3105         } else {
3106                 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
3107                         AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
3108         }
3109
3110         return 0;
3111 }
3112
3113 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
3114 {
3115         /*Just a try M.F.*/
3116         struct ieee80211_channel *channel = ah->ah_current_channel;
3117         u8 ee_mode;
3118
3119         ATH5K_TRACE(ah->ah_sc);
3120
3121         switch (channel->hw_value & CHANNEL_MODES) {
3122         case CHANNEL_A:
3123         case CHANNEL_T:
3124         case CHANNEL_XR:
3125                 ee_mode = AR5K_EEPROM_MODE_11A;
3126                 break;
3127         case CHANNEL_G:
3128         case CHANNEL_TG:
3129                 ee_mode = AR5K_EEPROM_MODE_11G;
3130                 break;
3131         case CHANNEL_B:
3132                 ee_mode = AR5K_EEPROM_MODE_11B;
3133                 break;
3134         default:
3135                 ATH5K_ERR(ah->ah_sc,
3136                         "invalid channel: %d\n", channel->center_freq);
3137                 return -EINVAL;
3138         }
3139
3140         ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
3141                 "changing txpower to %d\n", txpower);
3142
3143         return ath5k_hw_txpower(ah, channel, ee_mode, txpower);
3144 }
3145
3146 #undef _ATH5K_PHY