EXYNOS5: Add support for FIMD and DP
authorAjay Kumar <ajaykumar.rs@samsung.com>
Tue, 8 Jan 2013 20:42:26 +0000 (20:42 +0000)
committerMinkyu Kang <mk7.kang@samsung.com>
Thu, 10 Jan 2013 01:19:47 +0000 (10:19 +0900)
Add panel_info structure required by LCD driver
and DP panel platdata for SMDK5250.
Add GPIO configuration for LCD.
Enable FIMD and DP support on SMDK5250.
DP Panel size: 2560x1600.
We use 16BPP resolution to get LCD console.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chomium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
arch/arm/include/asm/arch-exynos/dp_info.h
board/samsung/smdk5250/smdk5250.c
include/configs/exynos5250-dt.h

index 3569498..102b709 100644 (file)
@@ -211,4 +211,6 @@ unsigned int exynos_init_dp(void)
 }
 #endif
 
+void exynos_set_dp_platform_data(struct exynos_dp_platform_data *pd);
+
 #endif /* _DP_INFO_H */
index d80f75d..9c4bf9b 100644 (file)
 #include <fdtdec.h>
 #include <asm/io.h>
 #include <i2c.h>
+#include <lcd.h>
 #include <netdev.h>
 #include <spi.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/pinmux.h>
+#include <asm/arch/power.h>
 #include <asm/arch/sromc.h>
+#include <asm/arch/dp_info.h>
 #include <power/pmic.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -277,3 +280,97 @@ int board_early_init_f(void)
        return err;
 }
 #endif
+
+void cfg_lcd_gpio(void)
+{
+       struct exynos5_gpio_part1 *gpio1 =
+               (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+
+       /* For Backlight */
+       s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
+       s5p_gpio_set_value(&gpio1->b2, 0, 1);
+
+       /* LCD power on */
+       s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
+       s5p_gpio_set_value(&gpio1->x1, 5, 1);
+
+       /* Set Hotplug detect for DP */
+       s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
+}
+
+vidinfo_t panel_info = {
+       .vl_freq        = 60,
+       .vl_col         = 2560,
+       .vl_row         = 1600,
+       .vl_width       = 2560,
+       .vl_height      = 1600,
+       .vl_clkp        = CONFIG_SYS_LOW,
+       .vl_hsp         = CONFIG_SYS_LOW,
+       .vl_vsp         = CONFIG_SYS_LOW,
+       .vl_dp          = CONFIG_SYS_LOW,
+       .vl_bpix        = 4,    /* LCD_BPP = 2^4, for output conosle on LCD */
+
+       /* wDP panel timing infomation */
+       .vl_hspw        = 32,
+       .vl_hbpd        = 80,
+       .vl_hfpd        = 48,
+
+       .vl_vspw        = 6,
+       .vl_vbpd        = 37,
+       .vl_vfpd        = 3,
+       .vl_cmd_allow_len = 0xf,
+
+       .win_id         = 3,
+       .cfg_gpio       = cfg_lcd_gpio,
+       .backlight_on   = NULL,
+       .lcd_power_on   = NULL,
+       .reset_lcd      = NULL,
+       .dual_lcd_enabled = 0,
+
+       .init_delay     = 0,
+       .power_on_delay = 0,
+       .reset_delay    = 0,
+       .interface_mode = FIMD_RGB_INTERFACE,
+       .dp_enabled     = 1,
+};
+
+static struct edp_device_info edp_info = {
+       .disp_info = {
+               .h_res = 2560,
+               .h_sync_width = 32,
+               .h_back_porch = 80,
+               .h_front_porch = 48,
+               .v_res = 1600,
+               .v_sync_width  = 6,
+               .v_back_porch = 37,
+               .v_front_porch = 3,
+               .v_sync_rate = 60,
+       },
+       .lt_info = {
+               .lt_status = DP_LT_NONE,
+       },
+       .video_info = {
+               .master_mode = 0,
+               .bist_mode = DP_DISABLE,
+               .bist_pattern = NO_PATTERN,
+               .h_sync_polarity = 0,
+               .v_sync_polarity = 0,
+               .interlaced = 0,
+               .color_space = COLOR_RGB,
+               .dynamic_range = VESA,
+               .ycbcr_coeff = COLOR_YCBCR601,
+               .color_depth = COLOR_8,
+       },
+};
+
+static struct exynos_dp_platform_data dp_platform_data = {
+       .phy_enable     = set_dp_phy_ctrl,
+       .edp_dev_info   = &edp_info,
+};
+
+void init_panel_info(vidinfo_t *vid)
+{
+       vid->rgb_mode   = MODE_RGB_P,
+
+       exynos_set_dp_platform_data(&dp_platform_data);
+}
index 59182f4..07bca1d 100644 (file)
 #define CONFIG_SHA1
 #define CONFIG_SHA256
 
+/* Display */
+#define CONFIG_LCD
+#define CONFIG_EXYNOS_FB
+#define CONFIG_EXYNOS_DP
+#define LCD_XRES                       2560
+#define LCD_YRES                       1600
+#define LCD_BPP                        LCD_COLOR16
+
 #endif /* __CONFIG_H */