omap5: Add minimal support for omap5430.
authorSricharan <r.sricharan@ti.com>
Tue, 15 Nov 2011 14:49:55 +0000 (09:49 -0500)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Tue, 15 Nov 2011 21:25:50 +0000 (22:25 +0100)
This patch adds the minimal support for OMAP5. The platform and machine
specific headers and sources updated for OMAP5430.

OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP architecture.
It's a dual core SOC with GIC used for interrupt handling and SCU for cache
coherency.

Also moved some part of code from the basic platform support that can be made
common for OMAP4/5. Rest is kept out seperately. The same approach is followed
for clocks and emif support in the subsequent patches.

Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
35 files changed:
MAINTAINERS
arch/arm/cpu/armv7/omap-common/clocks-common.c
arch/arm/cpu/armv7/omap-common/emif-common.c
arch/arm/cpu/armv7/omap-common/hwinit-common.c
arch/arm/cpu/armv7/omap-common/lowlevel_init.S
arch/arm/cpu/armv7/omap4/Makefile
arch/arm/cpu/armv7/omap4/hwinit.c [new file with mode: 0644]
arch/arm/cpu/armv7/omap4/omap4_mux_data.h [deleted file]
arch/arm/cpu/armv7/omap4/sys_info.c [deleted file]
arch/arm/cpu/armv7/omap5/Makefile [new file with mode: 0644]
arch/arm/cpu/armv7/omap5/config.mk [new file with mode: 0644]
arch/arm/cpu/armv7/omap5/hwinit.c [new file with mode: 0644]
arch/arm/include/asm/arch-omap4/omap.h [moved from arch/arm/include/asm/arch-omap4/omap4.h with 88% similarity]
arch/arm/include/asm/arch-omap4/sys_proto.h
arch/arm/include/asm/arch-omap5/cpu.h [new file with mode: 0644]
arch/arm/include/asm/arch-omap5/gpio.h [new file with mode: 0644]
arch/arm/include/asm/arch-omap5/i2c.h [new file with mode: 0644]
arch/arm/include/asm/arch-omap5/mmc_host_def.h [new file with mode: 0644]
arch/arm/include/asm/arch-omap5/mux_omap5.h [new file with mode: 0644]
arch/arm/include/asm/arch-omap5/omap.h [new file with mode: 0644]
arch/arm/include/asm/arch-omap5/sys_proto.h [new file with mode: 0644]
arch/arm/include/asm/armv7.h
arch/arm/include/asm/mach-types.h
arch/arm/include/asm/omap_common.h
board/ti/omap5_evm/Makefile [new file with mode: 0644]
board/ti/omap5_evm/evm.c [new file with mode: 0644]
board/ti/omap5_evm/mux_data.h [new file with mode: 0644]
board/ti/panda/Makefile
board/ti/panda/panda.c
board/ti/panda/panda_mux_data.h
board/ti/sdp4430/Makefile
board/ti/sdp4430/sdp.c
board/ti/sdp4430/sdp4430_mux_data.h
include/configs/omap4_common.h
spl/Makefile

index bf4c7e9..61a5336 100644 (file)
@@ -845,6 +845,7 @@ Aneesh V <aneesh@ti.com>
 
        omap4_panda     ARM ARMV7 (OMAP4xx SoC)
        omap4_sdp4430   ARM ARMV7 (OMAP4xx SoC)
+       omap5_evm       ARM ARMV7 (OMAP5xx Soc)
 
 Marek Vasut <marek.vasut@gmail.com>
 
index 095ba39..9f5200d 100644 (file)
@@ -925,7 +925,7 @@ void setup_clocks_for_console(void)
 
 void prcm_init(void)
 {
-       switch (omap4_hw_init_context()) {
+       switch (omap_hw_init_context()) {
        case OMAP_INIT_CONTEXT_SPL:
        case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
        case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
index 94c8bed..03b45c6 100644 (file)
@@ -1212,7 +1212,7 @@ void sdram_init(void)
 
        debug(">>sdram_init()\n");
 
-       if (omap4_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
+       if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
                return;
 
        in_sdram = running_from_sdram();
@@ -1237,7 +1237,7 @@ void sdram_init(void)
 
        /* Do some testing after the init */
        if (!in_sdram) {
-               size_prog = omap4_sdram_size();
+               size_prog = omap_sdram_size();
                size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
                                                size_prog);
                /* Compare with the size programmed */
index 8e765cf..2ab16bf 100644 (file)
@@ -1,6 +1,6 @@
 /*
  *
- * Common functions for OMAP4 based boards
+ * Common functions for OMAP4/5 based boards
  *
  * (C) Copyright 2010
  * Texas Instruments, <www.ti.com>
  * MA 02111-1307 USA
  */
 #include <common.h>
-#include <asm/armv7.h>
-#include <asm/arch/cpu.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/sizes.h>
 #include <asm/arch/emif.h>
-#include <asm/arch/gpio.h>
-#include "../omap4/omap4_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
-
-static const struct gpio_bank gpio_bank_44xx[6] = {
-       { (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX },
-       { (void *)OMAP44XX_GPIO2_BASE, METHOD_GPIO_24XX },
-       { (void *)OMAP44XX_GPIO3_BASE, METHOD_GPIO_24XX },
-       { (void *)OMAP44XX_GPIO4_BASE, METHOD_GPIO_24XX },
-       { (void *)OMAP44XX_GPIO5_BASE, METHOD_GPIO_24XX },
-       { (void *)OMAP44XX_GPIO6_BASE, METHOD_GPIO_24XX },
-};
-
-const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
-
 #ifdef CONFIG_SPL_BUILD
 /*
  * We use static variables because global data is not ready yet.
@@ -58,78 +41,17 @@ const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
  * We would not typically need to save these parameters in regular
  * U-Boot. This is needed only in SPL at the moment.
  */
-u32 omap4_boot_device = BOOT_DEVICE_MMC1;
-u32 omap4_boot_mode = MMCSD_MODE_FAT;
+u32 omap_bootdevice = BOOT_DEVICE_MMC1;
+u32 omap_bootmode = MMCSD_MODE_FAT;
 
 u32 omap_boot_device(void)
 {
-       return omap4_boot_device;
+       return omap_bootdevice;
 }
 
 u32 omap_boot_mode(void)
 {
-       return omap4_boot_mode;
-}
-
-/*
- * Some tuning of IOs for optimal power and performance
- */
-static void do_io_settings(void)
-{
-       u32 lpddr2io;
-       struct control_lpddr2io_regs *lpddr2io_regs =
-               (struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
-       struct omap4_sys_ctrl_regs *const ctrl =
-               (struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
-
-       u32 omap4_rev = omap_revision();
-
-       if (omap4_rev == OMAP4430_ES1_0)
-               lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
-       else if (omap4_rev == OMAP4430_ES2_0)
-               lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
-       else
-               lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
-
-       /* EMIF1 */
-       writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);
-       writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);
-       /* No pull for GR10 as per hw team's recommendation */
-       writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
-               &lpddr2io_regs->control_lpddr2io1_2);
-       writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io1_3);
-
-       /* EMIF2 */
-       writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);
-       writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);
-       /* No pull for GR10 as per hw team's recommendation */
-       writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
-               &lpddr2io_regs->control_lpddr2io2_2);
-       writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io2_3);
-
-       /*
-        * Some of these settings (TRIM values) come from eFuse and are
-        * in turn programmed in the eFuse at manufacturing time after
-        * calibration of the device. Do the software over-ride only if
-        * the device is not correctly trimmed
-        */
-       if (!(readl(&ctrl->control_std_fuse_opp_bgap) & 0xFFFF)) {
-
-               writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
-                       &ctrl->control_ldosram_iva_voltage_ctrl);
-
-               writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
-                       &ctrl->control_ldosram_mpu_voltage_ctrl);
-
-               writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
-                       &ctrl->control_ldosram_core_voltage_ctrl);
-       }
-
-       if (!readl(&ctrl->control_efuse_1))
-               writel(CONTROL_EFUSE_1_OVERRIDE, &ctrl->control_efuse_1);
-
-       if (!readl(&ctrl->control_efuse_2))
-               writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2);
+       return omap_bootmode;
 }
 #endif
 
@@ -142,26 +64,9 @@ void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
                writew(pad->val, base + pad->offset);
 }
 
-static void set_muxconf_regs_essential(void)
-{
-       do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
-                  sizeof(core_padconf_array_essential) /
-                  sizeof(struct pad_conf_entry));
-
-       do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
-                  sizeof(wkup_padconf_array_essential) /
-                  sizeof(struct pad_conf_entry));
-
-       if (omap_revision() >= OMAP4460_ES1_0)
-               do_set_mux(CONTROL_PADCONF_WKUP,
-                                wkup_padconf_array_essential_4460,
-                                sizeof(wkup_padconf_array_essential_4460) /
-                                sizeof(struct pad_conf_entry));
-}
-
 static void set_mux_conf_regs(void)
 {
-       switch (omap4_hw_init_context()) {
+       switch (omap_hw_init_context()) {
        case OMAP_INIT_CONTEXT_SPL:
                set_muxconf_regs_essential();
                break;
@@ -176,7 +81,7 @@ static void set_mux_conf_regs(void)
        }
 }
 
-static u32 cortex_a9_rev(void)
+u32 cortex_rev(void)
 {
 
        unsigned int rev;
@@ -187,65 +92,14 @@ static u32 cortex_a9_rev(void)
        return rev;
 }
 
-static void init_omap4_revision(void)
+void omap_rev_string(char *omap_rev_string)
 {
-       /*
-        * For some of the ES2/ES1 boards ID_CODE is not reliable:
-        * Also, ES1 and ES2 have different ARM revisions
-        * So use ARM revision for identification
-        */
-       unsigned int arm_rev = cortex_a9_rev();
+       u32 omap_rev = omap_revision();
+       u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16;
+       u32 major_rev = (omap_rev & 0x00000F00) >> 8;
+       u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
 
-       switch (arm_rev) {
-       case MIDR_CORTEX_A9_R0P1:
-               *omap4_revision = OMAP4430_ES1_0;
-               break;
-       case MIDR_CORTEX_A9_R1P2:
-               switch (readl(CONTROL_ID_CODE)) {
-               case OMAP4430_CONTROL_ID_CODE_ES2_0:
-                       *omap4_revision = OMAP4430_ES2_0;
-                       break;
-               case OMAP4430_CONTROL_ID_CODE_ES2_1:
-                       *omap4_revision = OMAP4430_ES2_1;
-                       break;
-               case OMAP4430_CONTROL_ID_CODE_ES2_2:
-                       *omap4_revision = OMAP4430_ES2_2;
-                       break;
-               default:
-                       *omap4_revision = OMAP4430_ES2_0;
-                       break;
-               }
-               break;
-       case MIDR_CORTEX_A9_R1P3:
-               *omap4_revision = OMAP4430_ES2_3;
-               break;
-       case MIDR_CORTEX_A9_R2P10:
-               switch (readl(CONTROL_ID_CODE)) {
-               case OMAP4460_CONTROL_ID_CODE_ES1_0:
-                       *omap4_revision = OMAP4460_ES1_0;
-                       break;
-               case OMAP4460_CONTROL_ID_CODE_ES1_1:
-                       *omap4_revision = OMAP4460_ES1_1;
-                       break;
-               default:
-                       *omap4_revision = OMAP4460_ES1_0;
-                       break;
-               }
-               break;
-       default:
-               *omap4_revision = OMAP4430_SILICON_ID_INVALID;
-               break;
-       }
-}
-
-void omap_rev_string(char *omap4_rev_string)
-{
-       u32 omap4_rev = omap_revision();
-       u32 omap4_variant = (omap4_rev & 0xFFFF0000) >> 16;
-       u32 major_rev = (omap4_rev & 0x00000F00) >> 8;
-       u32 minor_rev = (omap4_rev & 0x000000F0) >> 4;
-
-       sprintf(omap4_rev_string, "OMAP%x ES%x.%x", omap4_variant, major_rev,
+       sprintf(omap_rev_string, "OMAP%x ES%x.%x", omap_variant, major_rev,
                minor_rev);
 }
 
@@ -265,7 +119,7 @@ void omap_rev_string(char *omap4_rev_string)
  */
 void s_init(void)
 {
-       init_omap4_revision();
+       init_omap_revision();
        watchdog_init();
        set_mux_conf_regs();
 #ifdef CONFIG_SPL_BUILD
@@ -312,7 +166,7 @@ void watchdog_init(void)
  * This is needed because the size of memory installed may be
  * different on different versions of the board
  */
-u32 omap4_sdram_size(void)
+u32 omap_sdram_size(void)
 {
        u32 section, i, total_size = 0, size, addr;
        for (i = 0; i < 4; i++) {
@@ -339,8 +193,7 @@ u32 omap4_sdram_size(void)
 int dram_init(void)
 {
        sdram_init();
-       gd->ram_size = omap4_sdram_size();
-
+       gd->ram_size = omap_sdram_size();
        return 0;
 }
 
@@ -363,18 +216,26 @@ int arch_cpu_init(void)
        return 0;
 }
 
-#ifndef CONFIG_SYS_L2CACHE_OFF
-void v7_outer_cache_enable(void)
+/*
+ *  get_device_type(): tell if GP/HS/EMU/TST
+ */
+u32 get_device_type(void)
 {
-       set_pl310_ctrl_reg(1);
+       return 0;
 }
 
-void v7_outer_cache_disable(void)
+/*
+ * Print CPU information
+ */
+int print_cpuinfo(void)
 {
-       set_pl310_ctrl_reg(0);
-}
-#endif
+       char rev_string_buffer[50];
+
+       omap_rev_string(rev_string_buffer);
+       printf("CPU  : %s\n", rev_string_buffer);
 
+       return 0;
+}
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
 {
index 91525ec..6873298 100644 (file)
@@ -26,7 +26,7 @@
  * MA 02111-1307 USA
  */
 
-#include <asm/arch/omap4.h>
+#include <asm/arch/omap.h>
 #ifdef CONFIG_SPL_BUILD
 .global save_boot_params
 save_boot_params:
@@ -43,17 +43,17 @@ save_boot_params:
        cmp     r2, r0
        blt     1f
 
-       /* Store the boot device in omap4_boot_device */
+       /* Store the boot device in omap_boot_device */
        ldr     r2, [r0, #BOOT_DEVICE_OFFSET]   @ r1 <- value of boot device
        and     r2, #BOOT_DEVICE_MASK
-       ldr     r3, =omap4_boot_device
-       str     r2, [r3]                        @ omap4_boot_device <- r1
+       ldr     r3, =omap_bootdevice
+       str     r2, [r3]                        @ omap_boot_device <- r1
 
-       /* Store the boot mode (raw/FAT) in omap4_boot_mode */
+       /* Store the boot mode (raw/FAT) in omap_boot_mode */
        ldr     r2, [r0, #DEV_DESC_PTR_OFFSET]  @ get the device descriptor ptr
        ldr     r2, [r2, #DEV_DATA_PTR_OFFSET]  @ get the pDeviceData ptr
        ldr     r2, [r2, #BOOT_MODE_OFFSET]     @ get the boot mode
-       ldr     r3, =omap4_boot_mode
+       ldr     r3, =omap_bootmode
        str     r2, [r3]
 1:
        bx      lr
index d912729..606538b 100644 (file)
@@ -26,10 +26,7 @@ include $(TOPDIR)/config.mk
 LIB    =  $(obj)lib$(SOC).o
 
 COBJS  += sdram_elpida.o
-
-ifndef CONFIG_SPL_BUILD
-COBJS  += sys_info.o
-endif
+COBJS  += hwinit.o
 
 SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c
new file mode 100644 (file)
index 0000000..78b3cab
--- /dev/null
@@ -0,0 +1,167 @@
+/*
+ *
+ * Common functions for OMAP4 based boards
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *     Aneesh V        <aneesh@ti.com>
+ *     Steve Sakoman   <steve@sakoman.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/armv7.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/sizes.h>
+#include <asm/arch/emif.h>
+#include <asm/arch/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
+
+static const struct gpio_bank gpio_bank_44xx[6] = {
+       { (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX },
+       { (void *)OMAP44XX_GPIO2_BASE, METHOD_GPIO_24XX },
+       { (void *)OMAP44XX_GPIO3_BASE, METHOD_GPIO_24XX },
+       { (void *)OMAP44XX_GPIO4_BASE, METHOD_GPIO_24XX },
+       { (void *)OMAP44XX_GPIO5_BASE, METHOD_GPIO_24XX },
+       { (void *)OMAP44XX_GPIO6_BASE, METHOD_GPIO_24XX },
+};
+
+const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
+
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Some tuning of IOs for optimal power and performance
+ */
+void do_io_settings(void)
+{
+       u32 lpddr2io;
+       struct control_lpddr2io_regs *lpddr2io_regs =
+               (struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
+       struct omap4_sys_ctrl_regs *const ctrl =
+               (struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
+
+       u32 omap4_rev = omap_revision();
+
+       if (omap4_rev == OMAP4430_ES1_0)
+               lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
+       else if (omap4_rev == OMAP4430_ES2_0)
+               lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
+       else
+               lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
+
+       /* EMIF1 */
+       writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);
+       writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);
+       /* No pull for GR10 as per hw team's recommendation */
+       writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
+               &lpddr2io_regs->control_lpddr2io1_2);
+       writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io1_3);
+
+       /* EMIF2 */
+       writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);
+       writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);
+       /* No pull for GR10 as per hw team's recommendation */
+       writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
+               &lpddr2io_regs->control_lpddr2io2_2);
+       writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io2_3);
+
+       /*
+        * Some of these settings (TRIM values) come from eFuse and are
+        * in turn programmed in the eFuse at manufacturing time after
+        * calibration of the device. Do the software over-ride only if
+        * the device is not correctly trimmed
+        */
+       if (!(readl(&ctrl->control_std_fuse_opp_bgap) & 0xFFFF)) {
+
+               writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
+                       &ctrl->control_ldosram_iva_voltage_ctrl);
+
+               writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
+                       &ctrl->control_ldosram_mpu_voltage_ctrl);
+
+               writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
+                       &ctrl->control_ldosram_core_voltage_ctrl);
+       }
+
+       if (!readl(&ctrl->control_efuse_1))
+               writel(CONTROL_EFUSE_1_OVERRIDE, &ctrl->control_efuse_1);
+
+       if (!readl(&ctrl->control_efuse_2))
+               writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2);
+}
+#endif
+
+void init_omap_revision(void)
+{
+       /*
+        * For some of the ES2/ES1 boards ID_CODE is not reliable:
+        * Also, ES1 and ES2 have different ARM revisions
+        * So use ARM revision for identification
+        */
+       unsigned int arm_rev = cortex_rev();
+
+       switch (arm_rev) {
+       case MIDR_CORTEX_A9_R0P1:
+               *omap4_revision = OMAP4430_ES1_0;
+               break;
+       case MIDR_CORTEX_A9_R1P2:
+               switch (readl(CONTROL_ID_CODE)) {
+               case OMAP4_CONTROL_ID_CODE_ES2_0:
+                       *omap4_revision = OMAP4430_ES2_0;
+                       break;
+               case OMAP4_CONTROL_ID_CODE_ES2_1:
+                       *omap4_revision = OMAP4430_ES2_1;
+                       break;
+               case OMAP4_CONTROL_ID_CODE_ES2_2:
+                       *omap4_revision = OMAP4430_ES2_2;
+                       break;
+               default:
+                       *omap4_revision = OMAP4430_ES2_0;
+                       break;
+               }
+               break;
+       case MIDR_CORTEX_A9_R1P3:
+               *omap4_revision = OMAP4430_ES2_3;
+               break;
+       case MIDR_CORTEX_A9_R2P10:
+               *omap4_revision = OMAP4460_ES1_0;
+               break;
+       default:
+               *omap4_revision = OMAP4430_SILICON_ID_INVALID;
+               break;
+       }
+}
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+void v7_outer_cache_enable(void)
+{
+       set_pl310_ctrl_reg(1);
+}
+
+void v7_outer_cache_disable(void)
+{
+       set_pl310_ctrl_reg(0);
+}
+#endif
diff --git a/arch/arm/cpu/armv7/omap4/omap4_mux_data.h b/arch/arm/cpu/armv7/omap4/omap4_mux_data.h
deleted file mode 100644 (file)
index b940391..0000000
+++ /dev/null
@@ -1,83 +0,0 @@
- /*
- * (C) Copyright 2010
- * Texas Instruments Incorporated, <www.ti.com>
- *
- *     Balaji Krishnamoorthy   <balajitk@ti.com>
- *     Aneesh V                <aneesh@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _OMAP4_MUX_DATA_H_
-#define _OMAP4_MUX_DATA_H_
-
-#include <asm/arch/mux_omap4.h>
-
-const struct pad_conf_entry core_padconf_array_essential[] = {
-
-{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
-{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
-{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
-{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
-{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
-{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
-{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
-{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
-{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},    /* sdmmc2_clk */
-{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
-{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},        /* sdmmc1_clk */
-{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
-{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
-{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
-{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
-{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
-{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
-{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
-{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
-{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
-{I2C1_SCL, (PTU | IEN | M0)},                          /* i2c1_scl */
-{I2C1_SDA, (PTU | IEN | M0)},                          /* i2c1_sda */
-{I2C2_SCL, (PTU | IEN | M0)},                          /* i2c2_scl */
-{I2C2_SDA, (PTU | IEN | M0)},                          /* i2c2_sda */
-{I2C3_SCL, (PTU | IEN | M0)},                          /* i2c3_scl */
-{I2C3_SDA, (PTU | IEN | M0)},                          /* i2c3_sda */
-{I2C4_SCL, (PTU | IEN | M0)},                          /* i2c4_scl */
-{I2C4_SDA, (PTU | IEN | M0)},                          /* i2c4_sda */
-{UART3_CTS_RCTX, (PTU | IEN | M0)},                    /* uart3_tx */
-{UART3_RTS_SD, (M0)},                                  /* uart3_rts_sd */
-{UART3_RX_IRRX, (IEN | M0)},                           /* uart3_rx */
-{UART3_TX_IRTX, (M0)}                                  /* uart3_tx */
-
-};
-
-const struct pad_conf_entry wkup_padconf_array_essential[] = {
-
-{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
-{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
-{PAD1_SYS_32K, (IEN | M0)}      /* sys_32k */
-
-};
-
-const struct pad_conf_entry wkup_padconf_array_essential_4460[] = {
-
-{PAD1_FREF_CLK4_REQ, (M3)},     /* gpio_wk7, TPS */
-
-};
-
-
-#endif  /* _OMAP4_MUX_DATA_H_ */
diff --git a/arch/arm/cpu/armv7/omap4/sys_info.c b/arch/arm/cpu/armv7/omap4/sys_info.c
deleted file mode 100644 (file)
index b9e5765..0000000
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- *     Aneesh V        <aneesh@ti.com>
- *     Steve Sakoman   <steve@sakoman.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-
-/*
- *  get_device_type(): tell if GP/HS/EMU/TST
- */
-u32 get_device_type(void)
-{
-       return 0;
-}
-
-/*
- * get_board_rev() - get board revision
- */
-u32 get_board_rev(void)
-{
-       return 0x20;
-}
-
-/*
- * Print CPU information
- */
-int print_cpuinfo(void)
-{
-
-       puts("CPU  : OMAP4430\n");
-
-       return 0;
-}
diff --git a/arch/arm/cpu/armv7/omap5/Makefile b/arch/arm/cpu/armv7/omap5/Makefile
new file mode 100644 (file)
index 0000000..f8ca9ac
--- /dev/null
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2000-2010
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    =  $(obj)lib$(SOC).o
+
+COBJS  += hwinit.o
+COBJS  += clocks.o
+COBJS  += emif.o
+COBJS  += sdram_elpida.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all:    $(obj).depend $(LIB)
+
+$(LIB):        $(OBJS)
+       $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/omap5/config.mk b/arch/arm/cpu/armv7/omap5/config.mk
new file mode 100644 (file)
index 0000000..639f699
--- /dev/null
@@ -0,0 +1,28 @@
+#
+# Copyright 2011 Linaro Limited
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# Aneesh V <annesh@ti.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+ifdef CONFIG_SPL_BUILD
+ALL-y  += $(OBJTREE)/MLO
+else
+ALL-y  += $(obj)u-boot.img
+endif
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
new file mode 100644 (file)
index 0000000..fa8e390
--- /dev/null
@@ -0,0 +1,78 @@
+/*
+ *
+ * Functions for omap5 based boards.
+ *
+ * (C) Copyright 2011
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *     Aneesh V        <aneesh@ti.com>
+ *     Steve Sakoman   <steve@sakoman.com>
+ *     Sricharan       <r.sricharan@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/armv7.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/sizes.h>
+#include <asm/utils.h>
+#include <asm/arch/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 *const omap5_revision = (u32 *)OMAP5_SRAM_SCRATCH_OMAP5_REV;
+
+static struct gpio_bank gpio_bank_54xx[6] = {
+       { (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
+       { (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX },
+       { (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX },
+       { (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX },
+       { (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX },
+       { (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX },
+};
+
+const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
+
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Some tuning of IOs for optimal power and performance
+ */
+void do_io_settings(void)
+{
+}
+#endif
+
+void init_omap_revision(void)
+{
+       /*
+        * For some of the ES2/ES1 boards ID_CODE is not reliable:
+        * Also, ES1 and ES2 have different ARM revisions
+        * So use ARM revision for identification
+        */
+       unsigned int rev = cortex_rev();
+
+       switch (rev) {
+       case MIDR_CORTEX_A15_R0P0:
+               *omap5_revision = OMAP5430_ES1_0;
+       default:
+               *omap5_revision = OMAP5430_SILICON_ID_INVALID;
+       }
+}
similarity index 88%
rename from arch/arm/include/asm/arch-omap4/omap4.h
rename to arch/arm/include/asm/arch-omap4/omap.h
index 61ebb3d..0ade896 100644 (file)
@@ -44,7 +44,8 @@
 
 #define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000
 #define OMAP44XX_DRAM_ADDR_SPACE_END   0xD0000000
-
+#define DRAM_ADDR_SPACE_START  OMAP44XX_DRAM_ADDR_SPACE_START
+#define DRAM_ADDR_SPACE_END    OMAP44XX_DRAM_ADDR_SPACE_END
 
 /* CONTROL */
 #define CTRL_BASE              (OMAP44XX_L4_CORE_BASE + 0x2000)
 /* CONTROL_ID_CODE */
 #define CONTROL_ID_CODE                0x4A002204
 
-/* 4430 */
-#define OMAP4430_CONTROL_ID_CODE_ES1_0 0x0B85202F
-#define OMAP4430_CONTROL_ID_CODE_ES2_0 0x1B85202F
-#define OMAP4430_CONTROL_ID_CODE_ES2_1 0x3B95C02F
-#define OMAP4430_CONTROL_ID_CODE_ES2_2 0x4B95C02F
-#define OMAP4430_CONTROL_ID_CODE_ES2_3 0x6B95C02F
-
-/* 4460 */
-#define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F
-#define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F
+#define OMAP4_CONTROL_ID_CODE_ES1_0    0x0B85202F
+#define OMAP4_CONTROL_ID_CODE_ES2_0    0x1B85202F
+#define OMAP4_CONTROL_ID_CODE_ES2_1    0x3B95C02F
+#define OMAP4_CONTROL_ID_CODE_ES2_2    0x4B95C02F
+#define OMAP4_CONTROL_ID_CODE_ES2_3    0x6B95C02F
 
 /* UART */
 #define UART1_BASE             (OMAP44XX_L4_PER_BASE + 0x6a000)
@@ -151,7 +147,7 @@ struct omap4_sys_ctrl_regs {
        unsigned int control_ldosram_mpu_voltage_ctrl;  /* 0x4A002324 */
        unsigned int control_ldosram_core_voltage_ctrl; /* 0x4A002328 */
        unsigned int pad3[260277];
-       unsigned int control_pbiaslite;                 /* 0x4A100600 */
+       unsigned int control_pbiaslite;                 /* 0x4A100600 */
        unsigned int pad4[63];
        unsigned int control_efuse_1;                   /* 0x4A100700 */
        unsigned int control_efuse_2;                   /* 0x4A100704 */
@@ -188,16 +184,6 @@ struct control_lpddr2io_regs {
 #define OMAP4_SRAM_SCRATCH_EMIF_T_DEN  (SRAM_SCRATCH_SPACE_ADDR + 0x10)
 #define OMAP4_SRAM_SCRATCH_SPACE_END   (SRAM_SCRATCH_SPACE_ADDR + 0x14)
 
-/* Silicon revisions */
-#define OMAP4430_SILICON_ID_INVALID    0xFFFFFFFF
-#define OMAP4430_ES1_0 0x44300100
-#define OMAP4430_ES2_0 0x44300200
-#define OMAP4430_ES2_1 0x44300210
-#define OMAP4430_ES2_2 0x44300220
-#define OMAP4430_ES2_3 0x44300230
-#define OMAP4460_ES1_0 0x44600100
-#define OMAP4460_ES1_1 0x44600110
-
 /* ROM code defines */
 /* Boot device */
 #define BOOT_DEVICE_MASK       0xFF
index 1aacbb1..4f23687 100644 (file)
@@ -21,7 +21,7 @@
 #ifndef _SYS_PROTO_H_
 #define _SYS_PROTO_H_
 
-#include <asm/arch/omap4.h>
+#include <asm/arch/omap.h>
 #include <asm/arch/clocks.h>
 #include <asm/io.h>
 #include <asm/omap_common.h>
@@ -38,11 +38,13 @@ void gpmc_init(void);
 void watchdog_init(void);
 u32 get_device_type(void);
 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
+void set_muxconf_regs_essential(void);
 void set_muxconf_regs_non_essential(void);
 void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
 void set_pl310_ctrl_reg(u32 val);
+void omap_rev_string(char *omap_rev_string);
 void setup_clocks_for_console(void);
 void prcm_init(void);
 void bypass_dpll(u32 *const base);
@@ -51,7 +53,10 @@ u32 get_sys_clk_freq(void);
 u32 omap4_ddr_clk(void);
 void cancel_out(u32 *num, u32 *den, u32 den_limit);
 void sdram_init(void);
-u32 omap4_sdram_size(void);
+u32 omap_sdram_size(void);
+u32 cortex_rev(void);
+void init_omap_revision(void);
+void do_io_settings(void);
 
 static inline u32 running_from_sdram(void)
 {
@@ -86,7 +91,7 @@ static inline u8 uboot_loaded_by_spl(void)
  * This function finds this context.
  * Defining as inline may help in compiling out unused functions in SPL
  */
-static inline u32 omap4_hw_init_context(void)
+static inline u32 omap_hw_init_context(void)
 {
 #ifdef CONFIG_SPL_BUILD
        return OMAP_INIT_CONTEXT_SPL;
diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h
new file mode 100644 (file)
index 0000000..0697a73
--- /dev/null
@@ -0,0 +1,175 @@
+/*
+ * (C) Copyright 2006-2010
+ * Texas Instruments, <www.ti.com>
+ *
+ *     Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _CPU_H
+#define _CPU_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct gpmc_cs {
+       u32 config1;            /* 0x00 */
+       u32 config2;            /* 0x04 */
+       u32 config3;            /* 0x08 */
+       u32 config4;            /* 0x0C */
+       u32 config5;            /* 0x10 */
+       u32 config6;            /* 0x14 */
+       u32 config7;            /* 0x18 */
+       u32 nand_cmd;           /* 0x1C */
+       u32 nand_adr;           /* 0x20 */
+       u32 nand_dat;           /* 0x24 */
+       u8 res[8];              /* blow up to 0x30 byte */
+};
+
+struct gpmc {
+       u8 res1[0x10];
+       u32 sysconfig;          /* 0x10 */
+       u8 res2[0x4];
+       u32 irqstatus;          /* 0x18 */
+       u32 irqenable;          /* 0x1C */
+       u8 res3[0x20];
+       u32 timeout_control;    /* 0x40 */
+       u8 res4[0xC];
+       u32 config;             /* 0x50 */
+       u32 status;             /* 0x54 */
+       u8 res5[0x8];   /* 0x58 */
+       struct gpmc_cs cs[8];   /* 0x60, 0x90, .. */
+       u8 res6[0x14];          /* 0x1E0 */
+       u32 ecc_config;         /* 0x1F4 */
+       u32 ecc_control;        /* 0x1F8 */
+       u32 ecc_size_config;    /* 0x1FC */
+       u32 ecc1_result;        /* 0x200 */
+       u32 ecc2_result;        /* 0x204 */
+       u32 ecc3_result;        /* 0x208 */
+       u32 ecc4_result;        /* 0x20C */
+       u32 ecc5_result;        /* 0x210 */
+       u32 ecc6_result;        /* 0x214 */
+       u32 ecc7_result;        /* 0x218 */
+       u32 ecc8_result;        /* 0x21C */
+       u32 ecc9_result;        /* 0x220 */
+};
+
+/* Used for board specific gpmc initialization */
+extern struct gpmc *gpmc_cfg;
+
+struct gptimer {
+       u32 tidr;               /* 0x00 r */
+       u8 res1[0xc];
+       u32 tiocp_cfg;          /* 0x10 rw */
+       u8 res2[0x10];
+       u32 tisr_raw;           /* 0x24 r */
+       u32 tisr;               /* 0x28 rw */
+       u32 tier;               /* 0x2c rw */
+       u32 ticr;               /* 0x30 rw */
+       u32 twer;               /* 0x34 rw */
+       u32 tclr;               /* 0x38 rw */
+       u32 tcrr;               /* 0x3c rw */
+       u32 tldr;               /* 0x40 rw */
+       u32 ttgr;               /* 0x44 rw */
+       u32 twpc;               /* 0x48 r */
+       u32 tmar;               /* 0x4c rw */
+       u32 tcar1;              /* 0x50 r */
+       u32 tcicr;              /* 0x54 rw */
+       u32 tcar2;              /* 0x58 r */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+/* enable sys_clk NO-prescale /1 */
+#define GPT_EN                 ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
+
+/* Watchdog */
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct watchdog {
+       u8 res1[0x34];
+       u32 wwps;               /* 0x34 r */
+       u8 res2[0x10];
+       u32 wspr;               /* 0x48 rw */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+#define WD_UNLOCK1             0xAAAA
+#define WD_UNLOCK2             0x5555
+
+#define SYSCLKDIV_1            (0x1 << 6)
+#define SYSCLKDIV_2            (0x1 << 7)
+
+#define CLKSEL_GPT1            (0x1 << 0)
+
+#define EN_GPT1                        (0x1 << 0)
+#define EN_32KSYNC             (0x1 << 2)
+
+#define ST_WDT2                        (0x1 << 5)
+
+#define RESETDONE              (0x1 << 0)
+
+#define TCLR_ST                        (0x1 << 0)
+#define TCLR_AR                        (0x1 << 1)
+#define TCLR_PRE               (0x1 << 5)
+
+/* GPMC BASE */
+#define GPMC_BASE              (OMAP54XX_GPMC_BASE)
+
+/* I2C base */
+#define I2C_BASE1              (OMAP54XX_L4_PER_BASE + 0x70000)
+#define I2C_BASE2              (OMAP54XX_L4_PER_BASE + 0x72000)
+#define I2C_BASE3              (OMAP54XX_L4_PER_BASE + 0x60000)
+
+/* MUSB base */
+#define MUSB_BASE              (OMAP54XX_L4_CORE_BASE + 0xAB000)
+
+/* OMAP4 GPIO registers */
+#define OMAP_GPIO_REVISION             0x0000
+#define OMAP_GPIO_SYSCONFIG            0x0010
+#define OMAP_GPIO_SYSSTATUS            0x0114
+#define OMAP_GPIO_IRQSTATUS1           0x0118
+#define OMAP_GPIO_IRQSTATUS2           0x0128
+#define OMAP_GPIO_IRQENABLE2           0x012c
+#define OMAP_GPIO_IRQENABLE1           0x011c
+#define OMAP_GPIO_WAKE_EN              0x0120
+#define OMAP_GPIO_CTRL                 0x0130
+#define OMAP_GPIO_OE                   0x0134
+#define OMAP_GPIO_DATAIN               0x0138
+#define OMAP_GPIO_DATAOUT              0x013c
+#define OMAP_GPIO_LEVELDETECT0         0x0140
+#define OMAP_GPIO_LEVELDETECT1         0x0144
+#define OMAP_GPIO_RISINGDETECT         0x0148
+#define OMAP_GPIO_FALLINGDETECT                0x014c
+#define OMAP_GPIO_DEBOUNCE_EN          0x0150
+#define OMAP_GPIO_DEBOUNCE_VAL         0x0154
+#define OMAP_GPIO_CLEARIRQENABLE1      0x0160
+#define OMAP_GPIO_SETIRQENABLE1                0x0164
+#define OMAP_GPIO_CLEARWKUENA          0x0180
+#define OMAP_GPIO_SETWKUENA            0x0184
+#define OMAP_GPIO_CLEARDATAOUT         0x0190
+#define OMAP_GPIO_SETDATAOUT           0x0194
+
+#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-omap5/gpio.h b/arch/arm/include/asm/arch-omap5/gpio.h
new file mode 100644 (file)
index 0000000..c14dff0
--- /dev/null
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * This work is derived from the linux 2.6.27 kernel source
+ * To fetch, use the kernel repository
+ * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
+ * Use the v2.6.27 tag.
+ *
+ * Below is the original's header including its copyright
+ *
+ *  linux/arch/arm/plat-omap/gpio.c
+ *
+ * Support functions for OMAP GPIO
+ *
+ * Copyright (C) 2003-2005 Nokia Corporation
+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef _GPIO_OMAP5_H
+#define _GPIO_OMAP5_H
+
+#include <asm/omap_gpio.h>
+
+#define OMAP54XX_GPIO1_BASE            0x4Ae10000
+#define OMAP54XX_GPIO2_BASE            0x48055000
+#define OMAP54XX_GPIO3_BASE            0x48057000
+#define OMAP54XX_GPIO4_BASE            0x48059000
+#define OMAP54XX_GPIO5_BASE            0x4805B000
+#define OMAP54XX_GPIO6_BASE            0x4805D000
+
+#endif /* _GPIO_OMAP5_H */
diff --git a/arch/arm/include/asm/arch-omap5/i2c.h b/arch/arm/include/asm/arch-omap5/i2c.h
new file mode 100644 (file)
index 0000000..68be03b
--- /dev/null
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2004-2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _OMAP5_I2C_H_
+#define _OMAP5_I2C_H_
+
+#define I2C_BUS_MAX    3
+#define I2C_DEFAULT_BASE       I2C_BASE1
+
+struct i2c {
+       unsigned short revnb_lo;        /* 0x00 */
+       unsigned short res1;
+       unsigned short revnb_hi;        /* 0x04 */
+       unsigned short res2[13];
+       unsigned short sysc;            /* 0x20 */
+       unsigned short res3;
+       unsigned short irqstatus_raw;   /* 0x24 */
+       unsigned short res4;
+       unsigned short stat;            /* 0x28 */
+       unsigned short res5;
+       unsigned short ie;              /* 0x2C */
+       unsigned short res6;
+       unsigned short irqenable_clr;   /* 0x30 */
+       unsigned short res7;
+       unsigned short iv;              /* 0x34 */
+       unsigned short res8[45];
+       unsigned short syss;            /* 0x90 */
+       unsigned short res9;
+       unsigned short buf;             /* 0x94 */
+       unsigned short res10;
+       unsigned short cnt;             /* 0x98 */
+       unsigned short res11;
+       unsigned short data;            /* 0x9C */
+       unsigned short res13;
+       unsigned short res14;           /* 0xA0 */
+       unsigned short res15;
+       unsigned short con;             /* 0xA4 */
+       unsigned short res16;
+       unsigned short oa;              /* 0xA8 */
+       unsigned short res17;
+       unsigned short sa;              /* 0xAC */
+       unsigned short res18;
+       unsigned short psc;             /* 0xB0 */
+       unsigned short res19;
+       unsigned short scll;            /* 0xB4 */
+       unsigned short res20;
+       unsigned short sclh;            /* 0xB8 */
+       unsigned short res21;
+       unsigned short systest;         /* 0xBC */
+       unsigned short res22;
+       unsigned short bufstat;         /* 0xC0 */
+       unsigned short res23;
+};
+
+#endif /* _OMAP5_I2C_H_ */
diff --git a/arch/arm/include/asm/arch-omap5/mmc_host_def.h b/arch/arm/include/asm/arch-omap5/mmc_host_def.h
new file mode 100644 (file)
index 0000000..74439c9
--- /dev/null
@@ -0,0 +1,174 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef MMC_HOST_DEF_H
+#define MMC_HOST_DEF_H
+
+/*
+ * OMAP HSMMC register definitions
+ */
+
+#define OMAP_HSMMC1_BASE       0x4809C100
+#define OMAP_HSMMC2_BASE       0x480B4100
+#define OMAP_HSMMC3_BASE       0x480AD100
+
+struct hsmmc {
+       unsigned char res1[0x10];
+       unsigned int sysconfig;         /* 0x10 */
+       unsigned int sysstatus;         /* 0x14 */
+       unsigned char res2[0x14];
+       unsigned int con;               /* 0x2C */
+       unsigned char res3[0xD4];
+       unsigned int blk;               /* 0x104 */
+       unsigned int arg;               /* 0x108 */
+       unsigned int cmd;               /* 0x10C */
+       unsigned int rsp10;             /* 0x110 */
+       unsigned int rsp32;             /* 0x114 */
+       unsigned int rsp54;             /* 0x118 */
+       unsigned int rsp76;             /* 0x11C */
+       unsigned int data;              /* 0x120 */
+       unsigned int pstate;            /* 0x124 */
+       unsigned int hctl;              /* 0x128 */
+       unsigned int sysctl;            /* 0x12C */
+       unsigned int stat;              /* 0x130 */
+       unsigned int ie;                /* 0x134 */
+       unsigned char res4[0x8];
+       unsigned int capa;              /* 0x140 */
+};
+
+/*
+ * OMAP HS MMC Bit definitions
+ */
+#define MMC_SOFTRESET                  (0x1 << 1)
+#define RESETDONE                      (0x1 << 0)
+#define NOOPENDRAIN                    (0x0 << 0)
+#define OPENDRAIN                      (0x1 << 0)
+#define OD                             (0x1 << 0)
+#define INIT_NOINIT                    (0x0 << 1)
+#define INIT_INITSTREAM                        (0x1 << 1)
+#define HR_NOHOSTRESP                  (0x0 << 2)
+#define STR_BLOCK                      (0x0 << 3)
+#define MODE_FUNC                      (0x0 << 4)
+#define DW8_1_4BITMODE                 (0x0 << 5)
+#define MIT_CTO                                (0x0 << 6)
+#define CDP_ACTIVEHIGH                 (0x0 << 7)
+#define WPP_ACTIVEHIGH                 (0x0 << 8)
+#define RESERVED_MASK                  (0x3 << 9)
+#define CTPL_MMC_SD                    (0x0 << 11)
+#define BLEN_512BYTESLEN               (0x200 << 0)
+#define NBLK_STPCNT                    (0x0 << 16)
+#define DE_DISABLE                     (0x0 << 0)
+#define BCE_DISABLE                    (0x0 << 1)
+#define BCE_ENABLE                     (0x1 << 1)
+#define ACEN_DISABLE                   (0x0 << 2)
+#define DDIR_OFFSET                    (4)
+#define DDIR_MASK                      (0x1 << 4)
+#define DDIR_WRITE                     (0x0 << 4)
+#define DDIR_READ                      (0x1 << 4)
+#define MSBS_SGLEBLK                   (0x0 << 5)
+#define MSBS_MULTIBLK                  (0x1 << 5)
+#define RSP_TYPE_OFFSET                        (16)
+#define RSP_TYPE_MASK                  (0x3 << 16)
+#define RSP_TYPE_NORSP                 (0x0 << 16)
+#define RSP_TYPE_LGHT136               (0x1 << 16)
+#define RSP_TYPE_LGHT48                        (0x2 << 16)
+#define RSP_TYPE_LGHT48B               (0x3 << 16)
+#define CCCE_NOCHECK                   (0x0 << 19)
+#define CCCE_CHECK                     (0x1 << 19)
+#define CICE_NOCHECK                   (0x0 << 20)
+#define CICE_CHECK                     (0x1 << 20)
+#define DP_OFFSET                      (21)
+#define DP_MASK                                (0x1 << 21)
+#define DP_NO_DATA                     (0x0 << 21)
+#define DP_DATA                                (0x1 << 21)
+#define CMD_TYPE_NORMAL                        (0x0 << 22)
+#define INDEX_OFFSET                   (24)
+#define INDEX_MASK                     (0x3f << 24)
+#define INDEX(i)                       (i << 24)
+#define DATI_MASK                      (0x1 << 1)
+#define DATI_CMDDIS                    (0x1 << 1)
+#define DTW_1_BITMODE                  (0x0 << 1)
+#define DTW_4_BITMODE                  (0x1 << 1)
+#define DTW_8_BITMODE                   (0x1 << 5) /* CON[DW8]*/
+#define SDBP_PWROFF                    (0x0 << 8)
+#define SDBP_PWRON                     (0x1 << 8)
+#define SDVS_1V8                       (0x5 << 9)
+#define SDVS_3V0                       (0x6 << 9)
+#define ICE_MASK                       (0x1 << 0)
+#define ICE_STOP                       (0x0 << 0)
+#define ICS_MASK                       (0x1 << 1)
+#define ICS_NOTREADY                   (0x0 << 1)
+#define ICE_OSCILLATE                  (0x1 << 0)
+#define CEN_MASK                       (0x1 << 2)
+#define CEN_DISABLE                    (0x0 << 2)
+#define CEN_ENABLE                     (0x1 << 2)
+#define CLKD_OFFSET                    (6)
+#define CLKD_MASK                      (0x3FF << 6)
+#define DTO_MASK                       (0xF << 16)
+#define DTO_15THDTO                    (0xE << 16)
+#define SOFTRESETALL                   (0x1 << 24)
+#define CC_MASK                                (0x1 << 0)
+#define TC_MASK                                (0x1 << 1)
+#define BWR_MASK                       (0x1 << 4)
+#define BRR_MASK                       (0x1 << 5)
+#define ERRI_MASK                      (0x1 << 15)
+#define IE_CC                          (0x01 << 0)
+#define IE_TC                          (0x01 << 1)
+#define IE_BWR                         (0x01 << 4)
+#define IE_BRR                         (0x01 << 5)
+#define IE_CTO                         (0x01 << 16)
+#define IE_CCRC                                (0x01 << 17)
+#define IE_CEB                         (0x01 << 18)
+#define IE_CIE                         (0x01 << 19)
+#define IE_DTO                         (0x01 << 20)
+#define IE_DCRC                                (0x01 << 21)
+#define IE_DEB                         (0x01 << 22)
+#define IE_CERR                                (0x01 << 28)
+#define IE_BADA                                (0x01 << 29)
+
+#define VS30_3V0SUP                    (1 << 25)
+#define VS18_1V8SUP                    (1 << 26)
+
+/* Driver definitions */
+#define MMCSD_SECTOR_SIZE              512
+#define MMC_CARD                       0
+#define SD_CARD                                1
+#define BYTE_MODE                      0
+#define SECTOR_MODE                    1
+#define CLK_INITSEQ                    0
+#define CLK_400KHZ                     1
+#define CLK_MISC                       2
+
+#define RSP_TYPE_NONE  (RSP_TYPE_NORSP   | CCCE_NOCHECK | CICE_NOCHECK)
+#define MMC_CMD0       (INDEX(0)  | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
+
+/* Clock Configurations and Macros */
+#define MMC_CLOCK_REFERENCE    96 /* MHz */
+
+#define mmc_reg_out(addr, mask, val)\
+       writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
+
+int omap_mmc_init(int dev_index);
+
+#endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-omap5/mux_omap5.h b/arch/arm/include/asm/arch-omap5/mux_omap5.h
new file mode 100644 (file)
index 0000000..b8c2185
--- /dev/null
@@ -0,0 +1,344 @@
+/*
+ * (C) Copyright 2004-2009
+ * Texas Instruments Incorporated
+ * Richard Woodruff            <r-woodruff2@ti.com>
+ * Aneesh V                    <aneesh@ti.com>
+ * Balaji Krishnamoorthy       <balajitk@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _MUX_OMAP5_H_
+#define _MUX_OMAP5_H_
+
+#include <asm/types.h>
+
+struct pad_conf_entry {
+
+       u16 offset;
+
+       u16 val;
+
+} __attribute__ ((__packed__));
+
+#ifdef CONFIG_OFF_PADCONF
+#define OFF_PD          (1 << 12)
+#define OFF_PU          (3 << 12)
+#define OFF_OUT_PTD     (0 << 10)
+#define OFF_OUT_PTU     (2 << 10)
+#define OFF_IN          (1 << 10)
+#define OFF_OUT         (0 << 10)
+#define OFF_EN          (1 << 9)
+#else
+#define OFF_PD          (0 << 12)
+#define OFF_PU          (0 << 12)
+#define OFF_OUT_PTD     (0 << 10)
+#define OFF_OUT_PTU     (0 << 10)
+#define OFF_IN          (0 << 10)
+#define OFF_OUT         (0 << 10)
+#define OFF_EN          (0 << 9)
+#endif
+
+#define IEN             (1 << 8)
+#define IDIS            (0 << 8)
+#define PTU             (3 << 3)
+#define PTD             (1 << 3)
+#define EN              (1 << 3)
+#define DIS             (0 << 3)
+
+#define M0              0
+#define M1              1
+#define M2              2
+#define M3              3
+#define M4              4
+#define M5              5
+#define M6              6
+#define M7              7
+
+#define SAFE_MODE      M7
+
+#ifdef CONFIG_OFF_PADCONF
+#define OFF_IN_PD       (OFF_PD | OFF_IN | OFF_EN)
+#define OFF_IN_PU       (OFF_PU | OFF_IN | OFF_EN)
+#define OFF_OUT_PD      (OFF_OUT_PTD | OFF_OUT | OFF_EN)
+#define OFF_OUT_PU      (OFF_OUT_PTU | OFF_OUT | OFF_EN)
+#else
+#define OFF_IN_PD       0
+#define OFF_IN_PU       0
+#define OFF_OUT_PD      0
+#define OFF_OUT_PU      0
+#endif
+
+#define CORE_REVISION          0x0000
+#define CORE_HWINFO            0x0004
+#define CORE_SYSCONFIG         0x0010
+#define GPMC_AD0               0x0040
+#define GPMC_AD1               0x0042
+#define GPMC_AD2               0x0044
+#define GPMC_AD3               0x0046
+#define GPMC_AD4               0x0048
+#define GPMC_AD5               0x004A
+#define GPMC_AD6               0x004C
+#define GPMC_AD7               0x004E
+#define GPMC_AD8               0x0050
+#define GPMC_AD9               0x0052
+#define GPMC_AD10              0x0054
+#define GPMC_AD11              0x0056
+#define GPMC_AD12              0x0058
+#define GPMC_AD13              0x005A
+#define GPMC_AD14              0x005C
+#define GPMC_AD15              0x005E
+#define GPMC_A16               0x0060
+#define GPMC_A17               0x0062
+#define GPMC_A18               0x0064
+#define GPMC_A19               0x0066
+#define GPMC_A20               0x0068
+#define GPMC_A21               0x006A
+#define GPMC_A22               0x006C
+#define GPMC_A23               0x006E
+#define GPMC_A24               0x0070
+#define GPMC_A25               0x0072
+#define GPMC_NCS0              0x0074
+#define GPMC_NCS1              0x0076
+#define GPMC_NCS2              0x0078
+#define GPMC_NCS3              0x007A
+#define GPMC_NWP               0x007C
+#define GPMC_CLK               0x007E
+#define GPMC_NADV_ALE          0x0080
+#define GPMC_NOE               0x0082
+#define GPMC_NWE               0x0084
+#define GPMC_NBE0_CLE          0x0086
+#define GPMC_NBE1              0x0088
+#define GPMC_WAIT0             0x008A
+#define GPMC_WAIT1             0x008C
+#define C2C_DATA11             0x008E
+#define C2C_DATA12             0x0090
+#define C2C_DATA13             0x0092
+#define C2C_DATA14             0x0094
+#define C2C_DATA15             0x0096
+#define HDMI_HPD               0x0098
+#define HDMI_CEC               0x009A
+#define HDMI_DDC_SCL           0x009C
+#define HDMI_DDC_SDA           0x009E
+#define CSI21_DX0              0x00A0
+#define CSI21_DY0              0x00A2
+#define CSI21_DX1              0x00A4
+#define CSI21_DY1              0x00A6
+#define CSI21_DX2              0x00A8
+#define CSI21_DY2              0x00AA
+#define CSI21_DX3              0x00AC
+#define CSI21_DY3              0x00AE
+#define CSI21_DX4              0x00B0
+#define CSI21_DY4              0x00B2
+#define CSI22_DX0              0x00B4
+#define CSI22_DY0              0x00B6
+#define CSI22_DX1              0x00B8
+#define CSI22_DY1              0x00BA
+#define CAM_SHUTTER            0x00BC
+#define CAM_STROBE             0x00BE
+#define CAM_GLOBALRESET                0x00C0
+#define USBB1_ULPITLL_CLK      0x00C2
+#define USBB1_ULPITLL_STP      0x00C4
+#define USBB1_ULPITLL_DIR      0x00C6
+#define USBB1_ULPITLL_NXT      0x00C8
+#define USBB1_ULPITLL_DAT0     0x00CA
+#define USBB1_ULPITLL_DAT1     0x00CC
+#define USBB1_ULPITLL_DAT2     0x00CE
+#define USBB1_ULPITLL_DAT3     0x00D0
+#define USBB1_ULPITLL_DAT4     0x00D2
+#define USBB1_ULPITLL_DAT5     0x00D4
+#define USBB1_ULPITLL_DAT6     0x00D6
+#define USBB1_ULPITLL_DAT7     0x00D8
+#define USBB1_HSIC_DATA                0x00DA
+#define USBB1_HSIC_STROBE      0x00DC
+#define USBC1_ICUSB_DP         0x00DE
+#define USBC1_ICUSB_DM         0x00E0
+#define SDMMC1_CLK             0x00E2
+#define SDMMC1_CMD             0x00E4
+#define SDMMC1_DAT0            0x00E6
+#define SDMMC1_DAT1            0x00E8
+#define SDMMC1_DAT2            0x00EA
+#define SDMMC1_DAT3            0x00EC
+#define SDMMC1_DAT4            0x00EE
+#define SDMMC1_DAT5            0x00F0
+#define SDMMC1_DAT6            0x00F2
+#define SDMMC1_DAT7            0x00F4
+#define ABE_MCBSP2_CLKX                0x00F6
+#define ABE_MCBSP2_DR          0x00F8
+#define ABE_MCBSP2_DX          0x00FA
+#define ABE_MCBSP2_FSX         0x00FC
+#define ABE_MCBSP1_CLKX                0x00FE
+#define ABE_MCBSP1_DR          0x0100
+#define ABE_MCBSP1_DX          0x0102
+#define ABE_MCBSP1_FSX         0x0104
+#define ABE_PDM_UL_DATA                0x0106
+#define ABE_PDM_DL_DATA                0x0108
+#define ABE_PDM_FRAME          0x010A
+#define ABE_PDM_LB_CLK         0x010C
+#define ABE_CLKS               0x010E
+#define ABE_DMIC_CLK1          0x0110
+#define ABE_DMIC_DIN1          0x0112
+#define ABE_DMIC_DIN2          0x0114
+#define ABE_DMIC_DIN3          0x0116
+#define UART2_CTS              0x0118
+#define UART2_RTS              0x011A
+#define UART2_RX               0x011C
+#define UART2_TX               0x011E
+#define HDQ_SIO                        0x0120
+#define I2C1_SCL               0x0122
+#define I2C1_SDA               0x0124
+#define I2C2_SCL               0x0126
+#define I2C2_SDA               0x0128
+#define I2C3_SCL               0x012A
+#define I2C3_SDA               0x012C
+#define I2C4_SCL               0x012E
+#define I2C4_SDA               0x0130
+#define MCSPI1_CLK             0x0132
+#define MCSPI1_SOMI            0x0134
+#define MCSPI1_SIMO            0x0136
+#define MCSPI1_CS0             0x0138
+#define MCSPI1_CS1             0x013A
+#define MCSPI1_CS2             0x013C
+#define MCSPI1_CS3             0x013E
+#define UART3_CTS_RCTX         0x0140
+#define UART3_RTS_SD           0x0142
+#define UART3_RX_IRRX          0x0144
+#define UART3_TX_IRTX          0x0146
+#define SDMMC5_CLK             0x0148
+#define SDMMC5_CMD             0x014A
+#define SDMMC5_DAT0            0x014C
+#define SDMMC5_DAT1            0x014E
+#define SDMMC5_DAT2            0x0150
+#define SDMMC5_DAT3            0x0152
+#define MCSPI4_CLK             0x0154
+#define MCSPI4_SIMO            0x0156
+#define MCSPI4_SOMI            0x0158
+#define MCSPI4_CS0             0x015A
+#define UART4_RX               0x015C
+#define UART4_TX               0x015E
+#define USBB2_ULPITLL_CLK      0x0160
+#define USBB2_ULPITLL_STP      0x0162
+#define USBB2_ULPITLL_DIR      0x0164
+#define USBB2_ULPITLL_NXT      0x0166
+#define USBB2_ULPITLL_DAT0     0x0168
+#define USBB2_ULPITLL_DAT1     0x016A
+#define USBB2_ULPITLL_DAT2     0x016C
+#define USBB2_ULPITLL_DAT3     0x016E
+#define USBB2_ULPITLL_DAT4     0x0170
+#define USBB2_ULPITLL_DAT5     0x0172
+#define USBB2_ULPITLL_DAT6     0x0174
+#define USBB2_ULPITLL_DAT7     0x0176
+#define USBB2_HSIC_DATA                0x0178
+#define USBB2_HSIC_STROBE      0x017A
+#define UNIPRO_TX0             0x017C
+#define UNIPRO_TY0             0x017E
+#define UNIPRO_TX1             0x0180
+#define UNIPRO_TY1             0x0182
+#define UNIPRO_TX2             0x0184
+#define UNIPRO_TY2             0x0186
+#define UNIPRO_RX0             0x0188
+#define UNIPRO_RY0             0x018A
+#define UNIPRO_RX1             0x018C
+#define UNIPRO_RY1             0x018E
+#define UNIPRO_RX2             0x0190
+#define UNIPRO_RY2             0x0192
+#define USBA0_OTG_CE           0x0194
+#define USBA0_OTG_DP           0x0196
+#define USBA0_OTG_DM           0x0198
+#define FREF_CLK1_OUT          0x019A
+#define FREF_CLK2_OUT          0x019C
+#define SYS_NIRQ1              0x019E
+#define SYS_NIRQ2              0x01A0
+#define SYS_BOOT0              0x01A2
+#define SYS_BOOT1              0x01A4
+#define SYS_BOOT2              0x01A6
+#define SYS_BOOT3              0x01A8
+#define SYS_BOOT4              0x01AA
+#define SYS_BOOT5              0x01AC
+#define DPM_EMU0               0x01AE
+#define DPM_EMU1               0x01B0
+#define DPM_EMU2               0x01B2
+#define DPM_EMU3               0x01B4
+#define DPM_EMU4               0x01B6
+#define DPM_EMU5               0x01B8
+#define DPM_EMU6               0x01BA
+#define DPM_EMU7               0x01BC
+#define DPM_EMU8               0x01BE
+#define DPM_EMU9               0x01C0
+#define DPM_EMU10              0x01C2
+#define DPM_EMU11              0x01C4
+#define DPM_EMU12              0x01C6
+#define DPM_EMU13              0x01C8
+#define DPM_EMU14              0x01CA
+#define DPM_EMU15              0x01CC
+#define DPM_EMU16              0x01CE
+#define DPM_EMU17              0x01D0
+#define DPM_EMU18              0x01D2
+#define DPM_EMU19              0x01D4
+#define WAKEUPEVENT_0          0x01D8
+#define WAKEUPEVENT_1          0x01DC
+#define WAKEUPEVENT_2          0x01E0
+#define WAKEUPEVENT_3          0x01E4
+#define WAKEUPEVENT_4          0x01E8
+#define WAKEUPEVENT_5          0x01EC
+#define WAKEUPEVENT_6          0x01F0
+
+#define WKUP_REVISION          0x0000
+#define WKUP_HWINFO            0x0004
+#define WKUP_SYSCONFIG         0x0010
+#define PAD0_SIM_IO            0x0040
+#define PAD1_SIM_CLK           0x0042
+#define PAD0_SIM_RESET         0x0044
+#define PAD1_SIM_CD            0x0046
+#define PAD0_SIM_PWRCTRL               0x0048
+#define PAD1_SR_SCL            0x004A
+#define PAD0_SR_SDA            0x004C
+#define PAD1_FREF_XTAL_IN              0x004E
+#define PAD0_FREF_SLICER_IN    0x0050
+#define PAD1_FREF_CLK_IOREQ    0x0052
+#define PAD0_FREF_CLK0_OUT             0x0054
+#define PAD1_FREF_CLK3_REQ             0x0056
+#define PAD0_FREF_CLK3_OUT             0x0058
+#define PAD1_FREF_CLK4_REQ             0x005A
+#define PAD0_FREF_CLK4_OUT             0x005C
+#define PAD1_SYS_32K           0x005E
+#define PAD0_SYS_NRESPWRON             0x0060
+#define PAD1_SYS_NRESWARM              0x0062
+#define PAD0_SYS_PWR_REQ               0x0064
+#define PAD1_SYS_PWRON_RESET   0x0066
+#define PAD0_SYS_BOOT6         0x0068
+#define PAD1_SYS_BOOT7         0x006A
+#define PAD0_JTAG_NTRST                0x006C
+#define PAD1_JTAG_TCK          0x006D
+#define PAD0_JTAG_RTCK         0x0070
+#define PAD1_JTAG_TMS_TMSC             0x0072
+#define PAD0_JTAG_TDI          0x0074
+#define PAD1_JTAG_TDO          0x0076
+#define PADCONF_WAKEUPEVENT_0  0x007C
+#define CONTROL_SMART1NOPMIO_PADCONF_0         0x05A0
+#define CONTROL_SMART1NOPMIO_PADCONF_1         0x05A4
+#define PADCONF_MODE           0x05A8
+#define CONTROL_XTAL_OSCILLATOR                        0x05AC
+#define CONTROL_CONTROL_I2C_2                  0x0604
+#define CONTROL_CONTROL_JTAG                   0x0608
+#define CONTROL_CONTROL_SYS                    0x060C
+#define CONTROL_SPARE_RW               0x0614
+#define CONTROL_SPARE_R                0x0618
+#define CONTROL_SPARE_R_C0             0x061C
+
+#endif /* _MUX_OMAP5_H_ */
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
new file mode 100644 (file)
index 0000000..85975de
--- /dev/null
@@ -0,0 +1,207 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Authors:
+ *     Aneesh V <aneesh@ti.com>
+ *     Sricharan R <r.sricharan@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _OMAP5_H_
+#define _OMAP5_H_
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+/*
+ * L4 Peripherals - L4 Wakeup and L4 Core now
+ */
+#define OMAP54XX_L4_CORE_BASE  0x4A000000
+#define OMAP54XX_L4_WKUP_BASE  0x4Ae00000
+#define OMAP54XX_L4_PER_BASE   0x48000000
+
+#define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000
+#define OMAP54XX_DRAM_ADDR_SPACE_END   0xD0000000
+#define DRAM_ADDR_SPACE_START  OMAP54XX_DRAM_ADDR_SPACE_START
+#define DRAM_ADDR_SPACE_END    OMAP54XX_DRAM_ADDR_SPACE_END
+
+/* CONTROL */
+#define CTRL_BASE              (OMAP54XX_L4_CORE_BASE + 0x2000)
+#define CONTROL_PADCONF_CORE   (CTRL_BASE + 0x0800)
+#define CONTROL_PADCONF_WKUP   (OMAP54XX_L4_WKUP_BASE + 0xc800)
+
+/* LPDDR2 IO regs. To be verified */
+#define LPDDR2_IO_REGS_BASE    0x4A100638
+
+/* CONTROL_ID_CODE */
+#define CONTROL_ID_CODE                (CTRL_BASE + 0x204)
+
+/* To be verified */
+#define OMAP5_CONTROL_ID_CODE_ES1_0    0x0B85202F
+
+/* STD_FUSE_PROD_ID_1 */
+#define STD_FUSE_PROD_ID_1             (CTRL_BASE + 0x218)
+#define PROD_ID_1_SILICON_TYPE_SHIFT   16
+#define PROD_ID_1_SILICON_TYPE_MASK    (3 << 16)
+
+/* UART */
+#define UART1_BASE             (OMAP54XX_L4_PER_BASE + 0x6a000)
+#define UART2_BASE             (OMAP54XX_L4_PER_BASE + 0x6c000)
+#define UART3_BASE             (OMAP54XX_L4_PER_BASE + 0x20000)
+
+/* General Purpose Timers */
+#define GPT1_BASE              (OMAP54XX_L4_WKUP_BASE + 0x18000)
+#define GPT2_BASE              (OMAP54XX_L4_PER_BASE  + 0x32000)
+#define GPT3_BASE              (OMAP54XX_L4_PER_BASE  + 0x34000)
+
+/* Watchdog Timer2 - MPU watchdog */
+#define WDT2_BASE              (OMAP54XX_L4_WKUP_BASE + 0x14000)
+
+/* 32KTIMER */
+#define SYNC_32KTIMER_BASE     (OMAP54XX_L4_WKUP_BASE + 0x4000)
+
+/* GPMC */
+#define OMAP54XX_GPMC_BASE     0x50000000
+
+/* SYSTEM CONTROL MODULE */
+#define SYSCTRL_GENERAL_CORE_BASE      0x4A002000
+
+/*
+ * Hardware Register Details
+ */
+
+/* Watchdog Timer */
+#define WD_UNLOCK1             0xAAAA
+#define WD_UNLOCK2             0x5555
+
+/* GP Timer */
+#define TCLR_ST                        (0x1 << 0)
+#define TCLR_AR                        (0x1 << 1)
+#define TCLR_PRE               (0x1 << 5)
+
+/*
+ * PRCM
+ */
+
+/* PRM */
+#define PRM_BASE               0x4AE06000
+#define PRM_DEVICE_BASE                (PRM_BASE + 0x1B00)
+
+#define PRM_RSTCTRL            PRM_DEVICE_BASE
+#define PRM_RSTCTRL_RESET      0x01
+
+/* Control Module */
+#define LDOSRAM_ACTMODE_VSET_IN_MASK   (0x1F << 5)
+#define LDOSRAM_VOLT_CTRL_OVERRIDE     0x0401040f
+#define CONTROL_EFUSE_1_OVERRIDE       0x1C4D0110
+#define CONTROL_EFUSE_2_OVERRIDE       0x00084000
+
+/* LPDDR2 IO regs */
+#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN     0x1C1C1C1C
+#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER   0x9E9E9E9E
+#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN    0x7C7C7C7C
+#define LPDDR2IO_GR10_WD_MASK                          (3 << 17)
+#define CONTROL_LPDDR2IO_3_VAL         0xA0888C00
+
+/* CONTROL_EFUSE_2 */
+#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1           0x00ffc000
+
+#define MMC1_PWRDNZ                                    (1 << 26)
+#define MMC1_PBIASLITE_PWRDNZ                          (1 << 22)
+#define MMC1_PBIASLITE_VMODE                           (1 << 21)
+
+#ifndef __ASSEMBLY__
+
+struct s32ktimer {
+       unsigned char res[0x10];
+       unsigned int s32k_cr;   /* 0x10 */
+};
+
+struct omap4_sys_ctrl_regs {
+       unsigned int pad1[129];
+       unsigned int control_id_code;                   /* 0x4A002204 */
+       unsigned int pad11[22];
+       unsigned int control_std_fuse_opp_bgap;         /* 0x4a002260 */
+       unsigned int pad2[47];
+       unsigned int control_ldosram_iva_voltage_ctrl;  /* 0x4A002320 */
+       unsigned int control_ldosram_mpu_voltage_ctrl;  /* 0x4A002324 */
+       unsigned int control_ldosram_core_voltage_ctrl; /* 0x4A002328 */
+       unsigned int pad3[260277];
+       unsigned int control_pbiaslite;                 /* 0x4A100600 */
+       unsigned int pad4[63];
+       unsigned int control_efuse_1;                   /* 0x4A100700 */
+       unsigned int control_efuse_2;                   /* 0x4A100704 */
+};
+
+struct control_lpddr2io_regs {
+       unsigned int control_lpddr2io1_0;
+       unsigned int control_lpddr2io1_1;
+       unsigned int control_lpddr2io1_2;
+       unsigned int control_lpddr2io1_3;
+       unsigned int control_lpddr2io2_0;
+       unsigned int control_lpddr2io2_1;
+       unsigned int control_lpddr2io2_2;
+       unsigned int control_lpddr2io2_3;
+};
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Non-secure SRAM Addresses
+ * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
+ * at 0x40304000(EMU base) so that our code works for both EMU and GP
+ */
+#define NON_SECURE_SRAM_START  0x40304000
+#define NON_SECURE_SRAM_END    0x40320000      /* Not inclusive */
+/* base address for indirect vectors (internal boot mode) */
+#define SRAM_ROM_VECT_BASE     0x4031F000
+/* Temporary SRAM stack used while low level init is done */
+#define LOW_LEVEL_SRAM_STACK   NON_SECURE_SRAM_END
+
+#define SRAM_SCRATCH_SPACE_ADDR                NON_SECURE_SRAM_START
+/*
+ * SRAM scratch space entries
+ */
+#define OMAP5_SRAM_SCRATCH_OMAP5_REV   SRAM_SCRATCH_SPACE_ADDR
+#define OMAP5_SRAM_SCRATCH_EMIF_SIZE   (SRAM_SCRATCH_SPACE_ADDR + 0x4)
+#define OMAP5_SRAM_SCRATCH_EMIF_T_NUM  (SRAM_SCRATCH_SPACE_ADDR + 0xC)
+#define OMAP5_SRAM_SCRATCH_EMIF_T_DEN  (SRAM_SCRATCH_SPACE_ADDR + 0x10)
+#define OMAP5_SRAM_SCRATCH_SPACE_END   (SRAM_SCRATCH_SPACE_ADDR + 0x14)
+
+/* Silicon revisions */
+#define OMAP4430_SILICON_ID_INVALID    0xFFFFFFFF
+#define OMAP4430_ES1_0 0x44300100
+#define OMAP4430_ES2_0 0x44300200
+#define OMAP4430_ES2_1 0x44300210
+#define OMAP4430_ES2_2 0x44300220
+#define OMAP4430_ES2_3 0x44300230
+#define OMAP4460_ES1_0 0x44600100
+#define OMAP4460_ES1_1 0x44600110
+
+/* ROM code defines */
+/* Boot device */
+#define BOOT_DEVICE_MASK       0xFF
+#define BOOT_DEVICE_OFFSET     0x8
+#define DEV_DESC_PTR_OFFSET    0x4
+#define DEV_DATA_PTR_OFFSET    0x18
+#define BOOT_MODE_OFFSET       0x8
+
+#endif
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
new file mode 100644 (file)
index 0000000..fdca765
--- /dev/null
@@ -0,0 +1,121 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+#include <asm/arch/omap.h>
+#include <asm/io.h>
+#include <asm/arch/clocks.h>
+#include <asm/omap_common.h>
+#include <asm/arch/mux_omap5.h>
+
+struct omap_sysinfo {
+       char *board_string;
+};
+extern const struct omap_sysinfo sysinfo;
+
+extern struct omap5_prcm_regs *const prcm;
+
+void gpmc_init(void);
+void watchdog_init(void);
+u32 get_device_type(void);
+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
+void set_muxconf_regs_essential(void);
+void set_muxconf_regs_non_essential(void);
+void sr32(void *, u32, u32, u32);
+u32 wait_on_value(u32, u32, void *, u32);
+void sdelay(unsigned long);
+void omap_rev_string(char *omap_rev_string);
+void setup_clocks_for_console(void);
+void prcm_init(void);
+void bypass_dpll(u32 *const base);
+void freq_update_core(void);
+u32 get_sys_clk_freq(void);
+u32 omap5_ddr_clk(void);
+void cancel_out(u32 *num, u32 *den, u32 den_limit);
+void sdram_init(void);
+u32 omap_sdram_size(void);
+u32 cortex_rev(void);
+void init_omap_revision(void);
+void do_io_settings(void);
+
+/*
+ * This is used to verify if the configuration header
+ * was executed by Romcode prior to control of transfer
+ * to the bootloader. SPL is responsible for saving and
+ * passing this to the u-boot.
+ */
+extern struct omap_boot_parameters boot_params;
+
+static inline u32 running_from_sdram(void)
+{
+       u32 pc;
+       asm volatile ("mov %0, pc" : "=r" (pc));
+       return ((pc >= OMAP54XX_DRAM_ADDR_SPACE_START) &&
+           (pc < OMAP54XX_DRAM_ADDR_SPACE_END));
+}
+
+static inline u8 uboot_loaded_by_spl(void)
+{
+       /*
+        * Configuration Header is not supported yet, so u-boot init running
+        * from SDRAM implies that it was loaded by SPL. When this situation
+        * changes one of these approaches could be taken:
+        * i.  Pass a magic from SPL to U-Boot and U-Boot save it at a known
+        *     location.
+        * ii. Check the OPP. CH can support only 50% OPP while SPL initializes
+        *     the DPLLs at 100% OPP.
+        */
+       return running_from_sdram();
+}
+/*
+ * The basic hardware init of OMAP(s_init()) can happen in 4
+ * different contexts:
+ *  1. SPL running from SRAM
+ *  2. U-Boot running from FLASH
+ *  3. Non-XIP U-Boot loaded to SDRAM by SPL
+ *  4. Non-XIP U-Boot loaded to SDRAM by ROM code using the
+ *     Configuration Header feature
+ *
+ * This function finds this context.
+ * Defining as inline may help in compiling out unused functions in SPL
+ */
+static inline u32 omap_hw_init_context(void)
+{
+#ifdef CONFIG_SPL_BUILD
+       return OMAP_INIT_CONTEXT_SPL;
+#else
+       if (uboot_loaded_by_spl())
+               return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL;
+       else if (running_from_sdram())
+               return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH;
+       else
+               return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR;
+#endif
+}
+
+static inline u32 omap_revision(void)
+{
+       extern u32 *const omap5_revision;
+       return *omap5_revision;
+}
+
+#endif
index 9adc563..ad9a875 100644 (file)
@@ -31,6 +31,9 @@
 #define MIDR_CORTEX_A9_R1P3    0x411FC093
 #define MIDR_CORTEX_A9_R2P10   0x412FC09A
 
+/* Cortex-A15 revisions */
+#define MIDR_CORTEX_A15_R0P0   0x410FC0F0
+
 /* CCSIDR */
 #define CCSIDR_LINE_SIZE_OFFSET                0
 #define CCSIDR_LINE_SIZE_MASK          0x7
index 2549051..2d5c3bc 100644 (file)
@@ -1104,6 +1104,7 @@ extern unsigned int __machine_arch_type;
 #define MACH_TYPE_THALES_ADC           3492
 #define MACH_TYPE_UBISYS_P9D_EVP       3493
 #define MACH_TYPE_ATDGP318             3494
+#define MACH_TYPE_OMAP5_SEVM           3777
 
 #ifdef CONFIG_ARCH_EBSA110
 # ifdef machine_arch_type
@@ -14209,6 +14210,18 @@ extern unsigned int __machine_arch_type;
 # define machine_is_atdgp318() (0)
 #endif
 
+#ifdef CONFIG_MACH_OMAP5_SEVM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type     __machine_arch_type
+# else
+#  define machine_arch_type     MACH_TYPE_OMAP5_SEVM
+# endif
+# define machine_is_omap5_sevm()      (machine_arch_type == MACH_TYPE_OMAP5_SEVM)
+#else
+# define machine_is_omap5_sevm()      (0)
+#endif
+
 /*
  * These have not yet been registered
  */
index 3f2f004..f026805 100644 (file)
 void preloader_console_init(void);
 
 /* Boot device */
-#ifdef CONFIG_OMAP44XX /* OMAP4 */
+#ifdef CONFIG_OMAP54XX
+#define BOOT_DEVICE_NONE        0
+#define BOOT_DEVICE_XIP         1
+#define BOOT_DEVICE_XIPWAIT     2
+#define BOOT_DEVICE_NAND        3
+#define BOOT_DEVICE_ONE_NAND    4
+#define BOOT_DEVICE_MMC1        5
+#define BOOT_DEVICE_MMC2        6
+#define BOOT_DEVICE_MMC3       7
+#elif defined(CONFIG_OMAP44XX) /* OMAP4 */
 #define BOOT_DEVICE_NONE       0
 #define BOOT_DEVICE_XIP                1
 #define BOOT_DEVICE_XIPWAIT    2
@@ -74,7 +83,6 @@ extern struct spl_image_info spl_image;
 u32 omap_boot_device(void);
 u32 omap_boot_mode(void);
 
-
 /* SPL common function s*/
 void spl_parse_image_header(const struct image_header *header);
 void omap_rev_string(char *omap_rev_string);
@@ -85,4 +93,22 @@ void spl_nand_load_image(void);
 /* MMC SPL functions */
 void spl_mmc_load_image(void);
 
+/*
+ * silicon revisions.
+ * Moving this to common, so that most of code can be moved to common,
+ * directories.
+ */
+
+/* omap4 */
+#define OMAP4430_SILICON_ID_INVALID    0xFFFFFFFF
+#define OMAP4430_ES1_0 0x44300100
+#define OMAP4430_ES2_0 0x44300200
+#define OMAP4430_ES2_1 0x44300210
+#define OMAP4430_ES2_2 0x44300220
+#define OMAP4430_ES2_3 0x44300230
+#define OMAP4460_ES1_0 0x44600100
+
+/* omap5 */
+#define OMAP5430_SILICON_ID_INVALID    0
+#define OMAP5430_ES1_0 0x54300100
 #endif /* _OMAP_COMMON_H_ */
diff --git a/board/ti/omap5_evm/Makefile b/board/ti/omap5_evm/Makefile
new file mode 100644 (file)
index 0000000..fa81d64
--- /dev/null
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).o
+
+COBJS  := evm.o
+
+SRCS   := $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+
+$(LIB):        $(obj).depend $(OBJS)
+       $(call cmd_link_o_target, $(OBJS))
+
+clean:
+       rm -f $(OBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/ti/omap5_evm/evm.c b/board/ti/omap5_evm/evm.c
new file mode 100644 (file)
index 0000000..ea0cb13
--- /dev/null
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ * Aneesh V       <aneesh@ti.com>
+ * Steve Sakoman  <steve@sakoman.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <twl6030.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+
+#include "mux_data.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct omap_sysinfo sysinfo = {
+       "Board: OMAP5430 EVM\n"
+};
+
+/**
+ * @brief board_init
+ *
+ * @return 0
+ */
+int board_init(void)
+{
+       gpmc_init();
+       gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM;
+       gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
+
+       return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+       return 0;
+}
+
+/**
+ * @brief misc_init_r - Configure EVM board specific configurations
+ * such as power configurations, ethernet initialization as phase2 of
+ * boot sequence
+ *
+ * @return 0
+ */
+int misc_init_r(void)
+{
+#ifdef CONFIG_TWL6030_POWER
+       twl6030_init_battery_charging();
+#endif
+       return 0;
+}
+
+void set_muxconf_regs_essential(void)
+{
+       do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
+                  sizeof(core_padconf_array_essential) /
+                  sizeof(struct pad_conf_entry));
+
+       do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
+                  sizeof(wkup_padconf_array_essential) /
+                  sizeof(struct pad_conf_entry));
+}
+
+void set_muxconf_regs_non_essential(void)
+{
+       do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
+                  sizeof(core_padconf_array_non_essential) /
+                  sizeof(struct pad_conf_entry));
+
+       do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
+                  sizeof(wkup_padconf_array_non_essential) /
+                  sizeof(struct pad_conf_entry));
+}
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+int board_mmc_init(bd_t *bis)
+{
+       omap_mmc_init(0);
+       omap_mmc_init(1);
+       return 0;
+}
+#endif
diff --git a/board/ti/omap5_evm/mux_data.h b/board/ti/omap5_evm/mux_data.h
new file mode 100644 (file)
index 0000000..f033451
--- /dev/null
@@ -0,0 +1,275 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ *     Balaji Krishnamoorthy   <balajitk@ti.com>
+ *     Aneesh V                <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _EVM5430_MUX_DATA_H
+#define _EVM5430_MUX_DATA_H
+
+#include <asm/arch/mux_omap5.h>
+
+const struct pad_conf_entry core_padconf_array_essential[] = {
+
+{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
+{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
+{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
+{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
+{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
+{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
+{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
+{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
+{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},    /* sdmmc2_clk */
+{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
+{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},        /* sdmmc1_clk */
+{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
+{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
+{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
+{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
+{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
+{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
+{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
+{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
+{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
+{I2C1_SCL, (PTU | IEN | M0)},                          /* i2c1_scl */
+{I2C1_SDA, (PTU | IEN | M0)},                          /* i2c1_sda */
+{I2C2_SCL, (PTU | IEN | M0)},                          /* i2c2_scl */
+{I2C2_SDA, (PTU | IEN | M0)},                          /* i2c2_sda */
+{I2C3_SCL, (PTU | IEN | M0)},                          /* i2c3_scl */
+{I2C3_SDA, (PTU | IEN | M0)},                          /* i2c3_sda */
+{I2C4_SCL, (PTU | IEN | M0)},                          /* i2c4_scl */
+{I2C4_SDA, (PTU | IEN | M0)},                          /* i2c4_sda */
+{UART3_CTS_RCTX, (PTU | IEN | M0)},                    /* uart3_tx */
+{UART3_RTS_SD, (M0)},                                  /* uart3_rts_sd */
+{UART3_RX_IRRX, (IEN | M0)},                           /* uart3_rx */
+{UART3_TX_IRTX, (M0)}                                  /* uart3_tx */
+
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential[] = {
+
+{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
+{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
+{PAD1_SYS_32K, (IEN | M0)}      /* sys_32k */
+
+};
+
+const struct pad_conf_entry core_padconf_array_non_essential[] = {
+       {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},        /* gpio_32 */
+       {GPMC_AD9, (PTU | IEN | M3)},                                   /* gpio_33 */
+       {GPMC_AD10, (PTU | IEN | M3)},                                  /* gpio_34 */
+       {GPMC_AD11, (PTU | IEN | M3)},                                  /* gpio_35 */
+       {GPMC_AD12, (PTU | IEN | M3)},                                  /* gpio_36 */
+       {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},        /* gpio_37 */
+       {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},        /* gpio_38 */
+       {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},        /* gpio_39 */
+       {GPMC_A16, (M3)},                                               /* gpio_40 */
+       {GPMC_A17, (PTD | M3)},                                         /* gpio_41 */
+       {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},        /* kpd_row6 */
+       {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},        /* kpd_row7 */
+       {GPMC_A20, (IEN | M3)},                                         /* gpio_44 */
+       {GPMC_A21, (M3)},                                               /* gpio_45 */
+       {GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)},                    /* kpd_col6 */
+       {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)},                    /* kpd_col7 */
+       {GPMC_A24, (PTD | M3)},                                         /* gpio_48 */
+       {GPMC_A25, (PTD | M3)},                                         /* gpio_49 */
+       {GPMC_NCS0, (M3)},                                              /* gpio_50 */
+       {GPMC_NCS1, (IEN | M3)},                                        /* gpio_51 */
+       {GPMC_NCS2, (IEN | M3)},                                        /* gpio_52 */
+       {GPMC_NCS3, (IEN | M3)},                                        /* gpio_53 */
+       {GPMC_NWP, (M3)},                                               /* gpio_54 */
+       {GPMC_CLK, (PTD | M3)},                                         /* gpio_55 */
+       {GPMC_NADV_ALE, (M3)},                                          /* gpio_56 */
+       {GPMC_NBE0_CLE, (M3)},                                          /* gpio_59 */
+       {GPMC_NBE1, (PTD | M3)},                                        /* gpio_60 */
+       {GPMC_WAIT0, (PTU | IEN | M3)},                                 /* gpio_61 */
+       {GPMC_WAIT1, (IEN | M3)},                                       /* gpio_62 */
+       {C2C_DATA11, (PTD | M3)},                                       /* gpio_100 */
+       {C2C_DATA12, (M1)},                                             /* dsi1_te0 */
+       {C2C_DATA13, (PTD | M3)},                                       /* gpio_102 */
+       {C2C_DATA14, (M1)},                                             /* dsi2_te0 */
+       {C2C_DATA15, (PTD | M3)},                                       /* gpio_104 */
+       {HDMI_HPD, (M0)},                                               /* hdmi_hpd */
+       {HDMI_CEC, (M0)},                                               /* hdmi_cec */
+       {HDMI_DDC_SCL, (PTU | M0)},                                     /* hdmi_ddc_scl */
+       {HDMI_DDC_SDA, (PTU | IEN | M0)},                               /* hdmi_ddc_sda */
+       {CSI21_DX0, (IEN | M0)},                                        /* csi21_dx0 */
+       {CSI21_DY0, (IEN | M0)},                                        /* csi21_dy0 */
+       {CSI21_DX1, (IEN | M0)},                                        /* csi21_dx1 */
+       {CSI21_DY1, (IEN | M0)},                                        /* csi21_dy1 */
+       {CSI21_DX2, (IEN | M0)},                                        /* csi21_dx2 */
+       {CSI21_DY2, (IEN | M0)},                                        /* csi21_dy2 */
+       {CSI21_DX3, (PTD | M7)},                                        /* csi21_dx3 */
+       {CSI21_DY3, (PTD | M7)},                                        /* csi21_dy3 */
+       {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},             /* csi21_dx4 */
+       {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},             /* csi21_dy4 */
+       {CSI22_DX0, (IEN | M0)},                                        /* csi22_dx0 */
+       {CSI22_DY0, (IEN | M0)},                                        /* csi22_dy0 */
+       {CSI22_DX1, (IEN | M0)},                                        /* csi22_dx1 */
+       {CSI22_DY1, (IEN | M0)},                                        /* csi22_dy1 */
+       {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},            /* cam_shutter */
+       {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},             /* cam_strobe */
+       {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},  /* gpio_83 */
+       {USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)},              /* hsi1_cawake */
+       {USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)},              /* hsi1_cadata */
+       {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)},              /* hsi1_caflag */
+       {USBB1_ULPITLL_NXT, (OFF_EN | M1)},                             /* hsi1_acready */
+       {USBB1_ULPITLL_DAT0, (OFF_EN | M1)},                            /* hsi1_acwake */
+       {USBB1_ULPITLL_DAT1, (OFF_EN | M1)},                            /* hsi1_acdata */
+       {USBB1_ULPITLL_DAT2, (OFF_EN | M1)},                            /* hsi1_acflag */
+       {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)},             /* hsi1_caready */
+       {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},    /* usbb1_ulpiphy_dat4 */
+       {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},    /* usbb1_ulpiphy_dat5 */
+       {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},    /* usbb1_ulpiphy_dat6 */
+       {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},    /* usbb1_ulpiphy_dat7 */
+       {USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},       /* usbb1_hsic_data */
+       {USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},     /* usbb1_hsic_strobe */
+       {USBC1_ICUSB_DP, (IEN | M0)},                                   /* usbc1_icusb_dp */
+       {USBC1_ICUSB_DM, (IEN | M0)},                                   /* usbc1_icusb_dm */
+       {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},       /* abe_mcbsp2_clkx */
+       {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},             /* abe_mcbsp2_dr */
+       {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},                   /* abe_mcbsp2_dx */
+       {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},        /* abe_mcbsp2_fsx */
+       {ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},       /* abe_mcbsp1_clkx */
+       {ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},             /* abe_mcbsp1_dr */
+       {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},                   /* abe_mcbsp1_dx */
+       {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},        /* abe_mcbsp1_fsx */
+       {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */
+       {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */
+       {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},   /* abe_pdm_frame */
+       {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},  /* abe_pdm_lb_clk */
+       {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},        /* abe_clks */
+       {ABE_DMIC_CLK1, (M0)},                                          /* abe_dmic_clk1 */
+       {ABE_DMIC_DIN1, (IEN | M0)},                                    /* abe_dmic_din1 */
+       {ABE_DMIC_DIN2, (IEN | M0)},                                    /* abe_dmic_din2 */
+       {ABE_DMIC_DIN3, (IEN | M0)},                                    /* abe_dmic_din3 */
+       {UART2_CTS, (PTU | IEN | M0)},                                  /* uart2_cts */
+       {UART2_RTS, (M0)},                                              /* uart2_rts */
+       {UART2_RX, (PTU | IEN | M0)},                                   /* uart2_rx */
+       {UART2_TX, (M0)},                                               /* uart2_tx */
+       {HDQ_SIO, (M3)},                                                /* gpio_127 */
+       {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},            /* mcspi1_clk */
+       {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},           /* mcspi1_somi */
+       {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},           /* mcspi1_simo */
+       {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},      /* mcspi1_cs0 */
+       {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},      /* mcspi1_cs1 */
+       {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)},                /* gpio_139 */
+       {MCSPI1_CS3, (PTU | IEN | M3)},                                 /* gpio_140 */
+       {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)},          /* sdmmc5_clk */
+       {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},      /* sdmmc5_cmd */
+       {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},     /* sdmmc5_dat0 */
+       {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},     /* sdmmc5_dat1 */
+       {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},     /* sdmmc5_dat2 */
+       {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},     /* sdmmc5_dat3 */
+       {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},            /* mcspi4_clk */
+       {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},           /* mcspi4_simo */
+       {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},           /* mcspi4_somi */
+       {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},      /* mcspi4_cs0 */
+       {UART4_RX, (IEN | M0)},                                         /* uart4_rx */
+       {UART4_TX, (M0)},                                               /* uart4_tx */
+       {USBB2_ULPITLL_CLK, (PTD | IEN | M3)},                          /* gpio_157 */
+       {USBB2_ULPITLL_STP, (IEN | M5)},                                /* dispc2_data23 */
+       {USBB2_ULPITLL_DIR, (IEN | M5)},                                /* dispc2_data22 */
+       {USBB2_ULPITLL_NXT, (IEN | M5)},                                /* dispc2_data21 */
+       {USBB2_ULPITLL_DAT0, (IEN | M5)},                               /* dispc2_data20 */
+       {USBB2_ULPITLL_DAT1, (IEN | M5)},                               /* dispc2_data19 */
+       {USBB2_ULPITLL_DAT2, (IEN | M5)},                               /* dispc2_data18 */
+       {USBB2_ULPITLL_DAT3, (IEN | M5)},                               /* dispc2_data15 */
+       {USBB2_ULPITLL_DAT4, (IEN | M5)},                               /* dispc2_data14 */
+       {USBB2_ULPITLL_DAT5, (IEN | M5)},                               /* dispc2_data13 */
+       {USBB2_ULPITLL_DAT6, (IEN | M5)},                               /* dispc2_data12 */
+       {USBB2_ULPITLL_DAT7, (IEN | M5)},                               /* dispc2_data11 */
+       {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)},           /* gpio_169 */
+       {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)},         /* gpio_170 */
+       {UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)},                  /* kpd_col0 */
+       {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)},                  /* kpd_col1 */
+       {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)},                  /* kpd_col2 */
+       {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)},                  /* kpd_col3 */
+       {UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)},                  /* kpd_col4 */
+       {UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)},                  /* kpd_col5 */
+       {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},      /* kpd_row0 */
+       {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},      /* kpd_row1 */
+       {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},      /* kpd_row2 */
+       {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},      /* kpd_row3 */
+       {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},      /* kpd_row4 */
+       {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},      /* kpd_row5 */
+       {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},     /* usba0_otg_ce */
+       {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},          /* usba0_otg_dp */
+       {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},          /* usba0_otg_dm */
+       {FREF_CLK1_OUT, (M0)},                                          /* fref_clk1_out */
+       {FREF_CLK2_OUT, (M0)},                                          /* fref_clk2_out */
+       {SYS_NIRQ1, (PTU | IEN | M0)},                                  /* sys_nirq1 */
+       {SYS_NIRQ2, (M7)},                                              /* sys_nirq2 */
+       {SYS_BOOT0, (PTU | IEN | M3)},                                  /* gpio_184 */
+       {SYS_BOOT1, (M3)},                                              /* gpio_185 */
+       {SYS_BOOT2, (PTD | IEN | M3)},                                  /* gpio_186 */
+       {SYS_BOOT3, (PTD | IEN | M3)},                                  /* gpio_187 */
+       {SYS_BOOT4, (M3)},                                              /* gpio_188 */
+       {SYS_BOOT5, (PTD | IEN | M3)},                                  /* gpio_189 */
+       {DPM_EMU0, (IEN | M0)},                                         /* dpm_emu0 */
+       {DPM_EMU1, (IEN | M0)},                                         /* dpm_emu1 */
+       {DPM_EMU2, (IEN | M0)},                                         /* dpm_emu2 */
+       {DPM_EMU3, (IEN | M5)},                                         /* dispc2_data10 */
+       {DPM_EMU4, (IEN | M5)},                                         /* dispc2_data9 */
+       {DPM_EMU5, (IEN | M5)},                                         /* dispc2_data16 */
+       {DPM_EMU6, (IEN | M5)},                                         /* dispc2_data17 */
+       {DPM_EMU7, (IEN | M5)},                                         /* dispc2_hsync */
+       {DPM_EMU8, (IEN | M5)},                                         /* dispc2_pclk */
+       {DPM_EMU9, (IEN | M5)},                                         /* dispc2_vsync */
+       {DPM_EMU10, (IEN | M5)},                                        /* dispc2_de */
+       {DPM_EMU11, (IEN | M5)},                                        /* dispc2_data8 */
+       {DPM_EMU12, (IEN | M5)},                                        /* dispc2_data7 */
+       {DPM_EMU13, (IEN | M5)},                                        /* dispc2_data6 */
+       {DPM_EMU14, (IEN | M5)},                                        /* dispc2_data5 */
+       {DPM_EMU15, (IEN | M5)},                                        /* dispc2_data4 */
+       {DPM_EMU16, (M3)},                                              /* gpio_27 */
+       {DPM_EMU17, (IEN | M5)},                                        /* dispc2_data2 */
+       {DPM_EMU18, (IEN | M5)},                                        /* dispc2_data1 */
+       {DPM_EMU19, (IEN | M5)},                                        /* dispc2_data0 */
+};
+
+const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
+       {PAD0_SIM_IO, (IEN | M0)},              /* sim_io */
+       {PAD1_SIM_CLK, (M0)},                   /* sim_clk */
+       {PAD0_SIM_RESET, (M0)},                 /* sim_reset */
+       {PAD1_SIM_CD, (PTU | IEN | M0)},        /* sim_cd */
+       {PAD0_SIM_PWRCTRL, (M0)},               /* sim_pwrctrl */
+       {PAD1_FREF_XTAL_IN, (M0)},              /* # */
+       {PAD0_FREF_SLICER_IN, (M0)},            /* fref_slicer_in */
+       {PAD1_FREF_CLK_IOREQ, (M0)},            /* fref_clk_ioreq */
+       {PAD0_FREF_CLK0_OUT, (M2)},             /* sys_drm_msecure */
+       {PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)}, /* # */
+       {PAD0_FREF_CLK3_OUT, (M0)},             /* fref_clk3_out */
+       {PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)}, /* # */
+       {PAD0_FREF_CLK4_OUT, (M0)},             /* # */
+       {PAD0_SYS_NRESPWRON, (M0)},             /* sys_nrespwron */
+       {PAD1_SYS_NRESWARM, (M0)},              /* sys_nreswarm */
+       {PAD0_SYS_PWR_REQ, (PTU | M0)},         /* sys_pwr_req */
+       {PAD1_SYS_PWRON_RESET, (M3)},           /* gpio_wk29 */
+       {PAD0_SYS_BOOT6, (IEN | M3)},           /* gpio_wk9 */
+       {PAD1_SYS_BOOT7, (IEN | M3)},           /* gpio_wk10 */
+       {PAD1_FREF_CLK3_REQ, (M3)},             /* gpio_wk30 */
+       {PAD1_FREF_CLK4_REQ, (M3)},             /* gpio_wk7 */
+       {PAD0_FREF_CLK4_OUT, (M3)},             /* gpio_wk8 */
+};
+
+#endif /* _EVM4430_MUX_DATA_H */
index ec493f5..b299e2f 100644 (file)
@@ -25,9 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(BOARD).o
 
-ifndef CONFIG_SPL_BUILD
 COBJS  := panda.o
-endif
 
 SRCS   := $(COBJS:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS))
index 97320cb..b4271fb 100644 (file)
@@ -65,6 +65,23 @@ int misc_init_r(void)
        return 0;
 }
 
+void set_muxconf_regs_essential(void)
+{
+       do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
+                  sizeof(core_padconf_array_essential) /
+                  sizeof(struct pad_conf_entry));
+
+       do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
+                  sizeof(wkup_padconf_array_essential) /
+                  sizeof(struct pad_conf_entry));
+
+       if (omap_revision() >= OMAP4460_ES1_0)
+               do_set_mux(CONTROL_PADCONF_WKUP,
+                                wkup_padconf_array_essential_4460,
+                                sizeof(wkup_padconf_array_essential_4460) /
+                                sizeof(struct pad_conf_entry));
+}
+
 void set_muxconf_regs_non_essential(void)
 {
        do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
@@ -93,10 +110,18 @@ void set_muxconf_regs_non_essential(void)
                                sizeof(struct pad_conf_entry));
 }
 
-#ifdef CONFIG_GENERIC_MMC
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
        omap_mmc_init(0);
        return 0;
 }
 #endif
+
+/*
+ * get_board_rev() - get board revision
+ */
+u32 get_board_rev(void)
+{
+       return 0x20;
+}
index 83d0c3f..c05170e 100644 (file)
 
 #include <asm/arch/mux_omap4.h>
 
+
+const struct pad_conf_entry core_padconf_array_essential[] = {
+
+{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
+{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
+{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
+{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
+{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
+{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
+{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
+{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
+{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},    /* sdmmc2_clk */
+{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
+{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},        /* sdmmc1_clk */
+{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
+{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
+{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
+{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
+{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
+{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
+{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
+{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
+{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
+{I2C1_SCL, (PTU | IEN | M0)},                          /* i2c1_scl */
+{I2C1_SDA, (PTU | IEN | M0)},                          /* i2c1_sda */
+{I2C2_SCL, (PTU | IEN | M0)},                          /* i2c2_scl */
+{I2C2_SDA, (PTU | IEN | M0)},                          /* i2c2_sda */
+{I2C3_SCL, (PTU | IEN | M0)},                          /* i2c3_scl */
+{I2C3_SDA, (PTU | IEN | M0)},                          /* i2c3_sda */
+{I2C4_SCL, (PTU | IEN | M0)},                          /* i2c4_scl */
+{I2C4_SDA, (PTU | IEN | M0)},                          /* i2c4_sda */
+{UART3_CTS_RCTX, (PTU | IEN | M0)},                    /* uart3_tx */
+{UART3_RTS_SD, (M0)},                                  /* uart3_rts_sd */
+{UART3_RX_IRRX, (IEN | M0)},                           /* uart3_rx */
+{UART3_TX_IRTX, (M0)}                                  /* uart3_tx */
+
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential[] = {
+
+{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
+{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
+{PAD1_SYS_32K, (IEN | M0)}      /* sys_32k */
+
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential_4460[] = {
+
+{PAD1_FREF_CLK4_REQ, (M3)},     /* gpio_wk7, TPS */
+
+};
+
 const struct pad_conf_entry core_padconf_array_non_essential[] = {
        {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},        /* gpio_32 */
        {GPMC_AD9, (PTU | IEN | M3)},                                   /* gpio_33 */
@@ -219,7 +271,7 @@ const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
        {PAD0_FREF_SLICER_IN, (M0)},            /* fref_slicer_in */
        {PAD1_FREF_CLK_IOREQ, (M0)},            /* fref_clk_ioreq */
        {PAD0_FREF_CLK0_OUT, (M2)},             /* sys_drm_msecure */
-       {PAD1_FREF_CLK3_REQ, M7},                                       /* safe mode */
+       {PAD1_FREF_CLK3_REQ, M7},               /* safe mode */
        {PAD0_FREF_CLK3_OUT, (M0)},             /* fref_clk3_out */
        {PAD0_FREF_CLK4_OUT, (PTU | M3)},       /* led status_2 */
        {PAD0_SYS_NRESPWRON, (M0)},             /* sys_nrespwron */
index 806fdf4..72ad3eb 100644 (file)
@@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(BOARD).o
 
+COBJS  := sdp.o
+
 ifndef CONFIG_SPL_BUILD
-COBJS  := sdp.o cmd_bat.o
+COBJS  += cmd_bat.o
 endif
 
 SRCS   := $(COBJS:.o=.c)
index a5ea682..e1b853c 100644 (file)
@@ -70,6 +70,23 @@ int misc_init_r(void)
        return 0;
 }
 
+void set_muxconf_regs_essential(void)
+{
+       do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
+                  sizeof(core_padconf_array_essential) /
+                  sizeof(struct pad_conf_entry));
+
+       do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
+                  sizeof(wkup_padconf_array_essential) /
+                  sizeof(struct pad_conf_entry));
+
+       if (omap_revision() >= OMAP4460_ES1_0)
+               do_set_mux(CONTROL_PADCONF_WKUP,
+                                wkup_padconf_array_essential_4460,
+                                sizeof(wkup_padconf_array_essential_4460) /
+                                sizeof(struct pad_conf_entry));
+}
+
 void set_muxconf_regs_non_essential(void)
 {
        do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
@@ -81,7 +98,7 @@ void set_muxconf_regs_non_essential(void)
                   sizeof(struct pad_conf_entry));
 }
 
-#ifdef CONFIG_GENERIC_MMC
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
        omap_mmc_init(0);
@@ -89,3 +106,11 @@ int board_mmc_init(bd_t *bis)
        return 0;
 }
 #endif
+
+/*
+ * get_board_rev() - get board revision
+ */
+u32 get_board_rev(void)
+{
+       return 0x20;
+}
index 06efaea..f36b663 100644 (file)
 
 #include <asm/arch/mux_omap4.h>
 
+const struct pad_conf_entry core_padconf_array_essential[] = {
+
+{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
+{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
+{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
+{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
+{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
+{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
+{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
+{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
+{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},    /* sdmmc2_clk */
+{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
+{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},        /* sdmmc1_clk */
+{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
+{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
+{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
+{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
+{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
+{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
+{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
+{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
+{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
+{I2C1_SCL, (PTU | IEN | M0)},                          /* i2c1_scl */
+{I2C1_SDA, (PTU | IEN | M0)},                          /* i2c1_sda */
+{I2C2_SCL, (PTU | IEN | M0)},                          /* i2c2_scl */
+{I2C2_SDA, (PTU | IEN | M0)},                          /* i2c2_sda */
+{I2C3_SCL, (PTU | IEN | M0)},                          /* i2c3_scl */
+{I2C3_SDA, (PTU | IEN | M0)},                          /* i2c3_sda */
+{I2C4_SCL, (PTU | IEN | M0)},                          /* i2c4_scl */
+{I2C4_SDA, (PTU | IEN | M0)},                          /* i2c4_sda */
+{UART3_CTS_RCTX, (PTU | IEN | M0)},                    /* uart3_tx */
+{UART3_RTS_SD, (M0)},                                  /* uart3_rts_sd */
+{UART3_RX_IRRX, (IEN | M0)},                           /* uart3_rx */
+{UART3_TX_IRTX, (M0)}                                  /* uart3_tx */
+
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential[] = {
+
+{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
+{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
+{PAD1_SYS_32K, (IEN | M0)}      /* sys_32k */
+
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential_4460[] = {
+
+{PAD1_FREF_CLK4_REQ, (M3)},     /* gpio_wk7, TPS */
+
+};
+
 const struct pad_conf_entry core_padconf_array_non_essential[] = {
        {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},        /* gpio_32 */
        {GPMC_AD9, (PTU | IEN | M3)},                                   /* gpio_33 */
@@ -214,7 +265,6 @@ const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
        {PAD0_FREF_CLK0_OUT, (M2)},             /* sys_drm_msecure */
        {PAD1_FREF_CLK3_REQ, (M3)},             /* gpio_wk30 - Debug led-1 */
        {PAD0_FREF_CLK3_OUT, (M0)},             /* fref_clk3_out */
-       {PAD1_FREF_CLK4_REQ, (M3)},             /* gpio_wk7 - Debug led-2 */
        {PAD0_FREF_CLK4_OUT, (M3)},             /* gpio_wk8 - Debug led-3 */
        {PAD0_SYS_NRESPWRON, (M0)},             /* sys_nrespwron */
        {PAD1_SYS_NRESWARM, (M0)},              /* sys_nreswarm */
index f535769..11a3390 100644 (file)
@@ -39,7 +39,7 @@
 
 /* Get CPU defs */
 #include <asm/arch/cpu.h>
-#include <asm/arch/omap4.h>
+#include <asm/arch/omap.h>
 
 /* Display CPU and Board Info */
 #define CONFIG_DISPLAY_CPUINFO         1
index 010cd83..6ac42a2 100644 (file)
@@ -64,6 +64,9 @@ endif
 ifeq ($(SOC),omap4)
 LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
 endif
+ifeq ($(SOC),omap5)
+LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
+endif
 
 START := $(addprefix $(SPLTREE)/,$(START))
 LIBS := $(addprefix $(SPLTREE)/,$(sort $(LIBS-y)))