ARM: 8129/1: errata: work around Cortex-A15 erratum 830321 using dummy strex
authorMark Rutland <mark.rutland@arm.com>
Fri, 15 Aug 2014 11:11:50 +0000 (12:11 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Wed, 27 Aug 2014 14:40:13 +0000 (15:40 +0100)
commit2c32c65e3726c773760038910be30cce1b4d4149
tree5882204a965a7b819f20bc8cc7ae33088d3bde88
parent85868313177700d20644263a782351262d2aff84
ARM: 8129/1: errata: work around Cortex-A15 erratum 830321 using dummy strex

On revisions of Cortex-A15 prior to r3p3, a CLREX instruction at PL1 may
falsely trigger a watchpoint exception, leading to potential data aborts
during exception return and/or livelock.

This patch resolves the issue in the following ways:

  - Replacing our uses of CLREX with a dummy STREX sequence instead (as
    we did for v6 CPUs).

  - Removing the clrex code from v7_exit_coherency_flush and derivatives,
    since this only exists as a minor performance improvement when
    non-cached exclusives are in use (Linux doesn't use these).

Benchmarking on a variety of ARM cores revealed no measurable
performance difference with this change applied, so the change is
performed unconditionally and no new Kconfig entry is added.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Cc: stable@vger.kernel.org
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/include/asm/cacheflush.h
arch/arm/kernel/entry-header.S
arch/arm/mach-exynos/mcpm-exynos.c