From: Oskar Schirmer <os@emlix.com>
Date: Wed, 4 Mar 2009 15:21:30 +0000 (+0100)
Subject: xtensa: enforce slab alignment to maximum register width
X-Git-Tag: v2.6.30-rc1~221^2~15
X-Git-Url: https://git.openpandora.org/cgi-bin/gitweb.cgi?p=pandora-kernel.git;a=commitdiff_plain;h=a81cbd2da48eacc860acf4f40ea05db790f4c7c3;hp=a81cbd2da48eacc860acf4f40ea05db790f4c7c3

xtensa: enforce slab alignment to maximum register width

XCHAL_DATA_WIDTH is the maximum register width, slab caches should be
aligned to this.

Theoretical fix as all variants have had an XCHAL_DATA_WIDTH of 4
(wordsize) for now.  But the S6000 variant will raise this to 16.

Signed-off-by: Oskar Schirmer <os@emlix.com>
Signed-off-by: Johannes Weiner <jw@emlix.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
---