From: Arnd Bergmann <arnd@arndb.de>
Date: Sun, 30 Oct 2011 22:26:28 +0000 (+0100)
Subject: Merge branches 'depends/rmk/io', 'depends/rmk/l2x0' and 'depends/rmk/gpio' into highb... 
X-Git-Tag: v3.2-rc1~88^2~2^2~9
X-Git-Url: https://git.openpandora.org/cgi-bin/gitweb.cgi?p=pandora-kernel.git;a=commitdiff_plain;h=36bc45e219f48b5ec45c5aa34bc13dbe80e10c10

Merge branches 'depends/rmk/io', 'depends/rmk/l2x0' and 'depends/rmk/gpio' into highbank/soc
---

36bc45e219f48b5ec45c5aa34bc13dbe80e10c10
diff --cc arch/arm/Kconfig
index 3146ed3f6eca,2c71a8f3535a,3269576dbfa8,05589e85c180..4792d2928fa3
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@@@@ -1271,32 -1272,6 -1271,18 -1273,6 +1272,32 @@@@@ config ARM_ERRATA_75432
    	  This workaround defines cpu_relax() as smp_mb(), preventing correctly
    	  written polling loops from denying visibility of updates to memory.
    
 + +config ARM_ERRATA_364296
 + +	bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
 + +	depends on CPU_V6 && !SMP
 + +	help
 + +	  This options enables the workaround for the 364296 ARM1136
 + +	  r0p2 erratum (possible cache data corruption with
 + +	  hit-under-miss enabled). It sets the undocumented bit 31 in
 + +	  the auxiliary control register and the FI bit in the control
 + +	  register, thus disabling hit-under-miss without putting the
 + +	  processor into full low interrupt latency mode. ARM11MPCore
 + +	  is not affected.
 + +
 +++config ARM_ERRATA_764369
 +++	bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
 +++	depends on CPU_V7 && SMP
 +++	help
 +++	  This option enables the workaround for erratum 764369
 +++	  affecting Cortex-A9 MPCore with two or more processors (all
 +++	  current revisions). Under certain timing circumstances, a data
 +++	  cache line maintenance operation by MVA targeting an Inner
 +++	  Shareable memory region may fail to proceed up to either the
 +++	  Point of Coherency or to the Point of Unification of the
 +++	  system. This workaround adds a DSB instruction before the
 +++	  relevant cache maintenance functions and sets a specific bit
 +++	  in the diagnostic control register of the SCU.
 +++
    endmenu
    
    source "arch/arm/common/Kconfig"
diff --cc arch/arm/mach-mmp/gplugd.c
index 98e25d9aaab6,c070c24255f4,98e25d9aaab6,ef738deb20b5..32776f3739f1
--- a/arch/arm/mach-mmp/gplugd.c
+++ b/arch/arm/mach-mmp/gplugd.c
@@@@@ -13,9 -13,10 -13,9 -14,9 +14,8 @@@@@
    #include <asm/mach/arch.h>
    #include <asm/mach-types.h>
    
--- #include <mach/gpio.h>
    #include <mach/pxa168.h>
    #include <mach/mfp-pxa168.h>
 - -#include <mach/mfp-gplugd.h>
    
    #include "common.h"