AD525X ANALOG DEVICES DIGITAL POTENTIOMETERS DRIVER
M: Michael Hennerich <michael.hennerich@analog.com>
-L: device-driver-devel@blackfin.uclinux.org
+L: device-drivers-devel@blackfin.uclinux.org
W: http://wiki.analog.com/AD5254
S: Supported
F: drivers/misc/ad525x_dpot.c
AD5398 CURRENT REGULATOR DRIVER (AD5398/AD5821)
M: Michael Hennerich <michael.hennerich@analog.com>
-L: device-driver-devel@blackfin.uclinux.org
+L: device-drivers-devel@blackfin.uclinux.org
W: http://wiki.analog.com/AD5398
S: Supported
F: drivers/regulator/ad5398.c
AD714X CAPACITANCE TOUCH SENSOR DRIVER (AD7142/3/7/8/7A)
M: Michael Hennerich <michael.hennerich@analog.com>
-L: device-driver-devel@blackfin.uclinux.org
+L: device-drivers-devel@blackfin.uclinux.org
W: http://wiki.analog.com/AD7142
S: Supported
F: drivers/input/misc/ad714x.c
AD7877 TOUCHSCREEN DRIVER
M: Michael Hennerich <michael.hennerich@analog.com>
-L: device-driver-devel@blackfin.uclinux.org
+L: device-drivers-devel@blackfin.uclinux.org
W: http://wiki.analog.com/AD7877
S: Supported
F: drivers/input/touchscreen/ad7877.c
AD7879 TOUCHSCREEN DRIVER (AD7879/AD7889)
M: Michael Hennerich <michael.hennerich@analog.com>
-L: device-driver-devel@blackfin.uclinux.org
+L: device-drivers-devel@blackfin.uclinux.org
W: http://wiki.analog.com/AD7879
S: Supported
F: drivers/input/touchscreen/ad7879.c
ADP5520 BACKLIGHT DRIVER WITH IO EXPANDER (ADP5520/ADP5501)
M: Michael Hennerich <michael.hennerich@analog.com>
-L: device-driver-devel@blackfin.uclinux.org
+L: device-drivers-devel@blackfin.uclinux.org
W: http://wiki.analog.com/ADP5520
S: Supported
F: drivers/mfd/adp5520.c
ADP5588 QWERTY KEYPAD AND IO EXPANDER DRIVER (ADP5588/ADP5587)
M: Michael Hennerich <michael.hennerich@analog.com>
-L: device-driver-devel@blackfin.uclinux.org
+L: device-drivers-devel@blackfin.uclinux.org
W: http://wiki.analog.com/ADP5588
S: Supported
F: drivers/input/keyboard/adp5588-keys.c
ADP8860 BACKLIGHT DRIVER (ADP8860/ADP8861/ADP8863)
M: Michael Hennerich <michael.hennerich@analog.com>
-L: device-driver-devel@blackfin.uclinux.org
+L: device-drivers-devel@blackfin.uclinux.org
W: http://wiki.analog.com/ADP8860
S: Supported
F: drivers/video/backlight/adp8860_bl.c
ADXL34X THREE-AXIS DIGITAL ACCELEROMETER DRIVER (ADXL345/ADXL346)
M: Michael Hennerich <michael.hennerich@analog.com>
-L: device-driver-devel@blackfin.uclinux.org
+L: device-drivers-devel@blackfin.uclinux.org
W: http://wiki.analog.com/ADXL345
S: Supported
F: drivers/input/misc/adxl34x.c
F: drivers/infiniband/hw/amso1100/
ANALOG DEVICES INC ASOC CODEC DRIVERS
-L: device-driver-devel@blackfin.uclinux.org
+L: device-drivers-devel@blackfin.uclinux.org
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
W: http://wiki.analog.com/
S: Supported
select HAVE_FUNCTION_TRACER
select HAVE_FUNCTION_TRACE_MCOUNT_TEST
select HAVE_IDE
+ select HAVE_IRQ_WORK
select HAVE_KERNEL_GZIP if RAMKERNEL
select HAVE_KERNEL_BZIP2 if RAMKERNEL
select HAVE_KERNEL_LZMA if RAMKERNEL
select HAVE_KERNEL_LZO if RAMKERNEL
select HAVE_OPROFILE
+ select HAVE_PERF_EVENTS
select ARCH_WANT_OPTIONAL_GPIOLIB
select HAVE_GENERIC_HARDIRQS
select GENERIC_ATOMIC64
Most people should say N here.
config DEBUG_MMRS
- bool "Generate Blackfin MMR tree"
+ tristate "Generate Blackfin MMR tree"
select DEBUG_FS
help
Create a tree of Blackfin MMRs via the debugfs tree. If
# CONFIG_LOGO_LINUX_VGA16 is not set
# CONFIG_LOGO_LINUX_CLUT224 is not set
# CONFIG_LOGO_BLACKFIN_VGA16 is not set
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_SOC=m
-CONFIG_SND_BF5XX_I2S=m
-CONFIG_SND_BF5XX_SOC_SSM2602=m
-CONFIG_SND_BF5XX_AC97=m
-CONFIG_SND_BF5XX_SOC_AD1980=m
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_SND_BF5XX_I2S=y
+CONFIG_SND_BF5XX_SOC_SSM2602=y
CONFIG_HID_A4TECH=y
CONFIG_HID_APPLE=y
CONFIG_HID_BELKIN=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_BLACKFIN_TWI=m
+CONFIG_I2C_BLACKFIN_TWI=y
CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
CONFIG_SPI=y
CONFIG_SPI_BFIN=y
# CONFIG_LOGO_LINUX_VGA16 is not set
# CONFIG_LOGO_LINUX_CLUT224 is not set
# CONFIG_LOGO_BLACKFIN_VGA16 is not set
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_SOC=m
-CONFIG_SND_BF5XX_I2S=m
-CONFIG_SND_BF5XX_SOC_SSM2602=m
-CONFIG_SND_BF5XX_AC97=m
-CONFIG_SND_BF5XX_SOC_AD1980=m
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_SND_BF5XX_I2S=y
+CONFIG_SND_BF5XX_SOC_SSM2602=y
CONFIG_HID_A4TECH=y
CONFIG_HID_APPLE=y
CONFIG_HID_BELKIN=y
CONFIG_SND_SOC=m
CONFIG_SND_BF5XX_I2S=m
CONFIG_SND_BF5XX_SOC_AD73311=m
-CONFIG_SND_BF5XX_AC97=m
-CONFIG_SND_BF5XX_SOC_AD1980=m
# CONFIG_USB_SUPPORT is not set
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_BFIN=y
CONFIG_SND_SOC=m
CONFIG_SND_BF5XX_I2S=m
CONFIG_SND_BF5XX_SOC_AD73311=m
-CONFIG_SND_BF5XX_AC97=m
-CONFIG_SND_BF5XX_SOC_AD1980=m
# CONFIG_USB_SUPPORT is not set
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_BFIN=y
#define dump_bfin_trace_buffer()
#endif
-/* init functions only */
-extern int init_arch_irq(void);
-extern void init_exception_vectors(void);
-extern void program_IAR(void);
-
-extern asmlinkage void lower_to_irq14(void);
-extern asmlinkage void bfin_return_from_exception(void);
-extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
-extern int bfin_internal_set_wake(unsigned int irq, unsigned int state);
-
extern void *l1_data_A_sram_alloc(size_t);
extern void *l1_data_B_sram_alloc(size_t);
extern void *l1_inst_sram_alloc(size_t);
--- /dev/null
+/*
+ * Blackfin Performance Monitor definitions
+ *
+ * Copyright 2005-2011 Analog Devices Inc.
+ *
+ * Licensed under the ADI BSD license or GPL-2 (or later).
+ */
+
+#ifndef __ASM_BFIN_PFMON_H__
+#define __ASM_BFIN_PFMON_H__
+
+/* PFCTL Masks */
+#define PFMON_MASK 0xff
+#define PFCEN_MASK 0x3
+#define PFCEN_DISABLE 0x0
+#define PFCEN_ENABLE_USER 0x1
+#define PFCEN_ENABLE_SUPV 0x2
+#define PFCEN_ENABLE_ALL (PFCEN_ENABLE_USER | PFCEN_ENABLE_SUPV)
+
+#define PFPWR_P 0
+#define PEMUSW0_P 2
+#define PFCEN0_P 3
+#define PFMON0_P 5
+#define PEMUSW1_P 13
+#define PFCEN1_P 14
+#define PFMON1_P 16
+#define PFCNT0_P 24
+#define PFCNT1_P 25
+
+#define PFPWR (1 << PFPWR_P)
+#define PEMUSW(n, x) ((x) << ((n) ? PEMUSW1_P : PEMUSW0_P))
+#define PEMUSW0 PEMUSW(0, 1)
+#define PEMUSW1 PEMUSW(1, 1)
+#define PFCEN(n, x) ((x) << ((n) ? PFCEN1_P : PFCEN0_P))
+#define PFCEN0 PFCEN(0, PFCEN_MASK)
+#define PFCEN1 PFCEN(1, PFCEN_MASK)
+#define PFCNT(n, x) ((x) << ((n) ? PFCNT1_P : PFCNT0_P))
+#define PFCNT0 PFCNT(0, 1)
+#define PFCNT1 PFCNT(1, 1)
+#define PFMON(n, x) ((x) << ((n) ? PFMON1_P : PFMON0_P))
+#define PFMON0 PFMON(0, PFMON_MASK)
+#define PFMON1 PFMON(1, PFMON_MASK)
+
+#endif
};
#undef __BFP
+struct bfin_snd_platform_data {
+ const unsigned short *pin_req;
+};
+
#define bfin_read_sport_rx32(base) \
({ \
struct sport_register *__mmrs = (void *)base; \
static inline void flush_icache_range(unsigned start, unsigned end)
{
-#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
- blackfin_dcache_flush_range(start, end);
+#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK)
+ if (end <= physical_mem_end)
+ blackfin_dcache_flush_range(start, end);
+#endif
+#if defined(CONFIG_BFIN_L2_WRITEBACK)
+ if (start >= L2_START && end <= L2_START + L2_LENGTH)
+ blackfin_dcache_flush_range(start, end);
#endif
/* Make sure all write buffers in the data side of the core
* the pipeline.
*/
SSYNC();
-#if defined(CONFIG_BFIN_ICACHE)
- blackfin_icache_flush_range(start, end);
- flush_icache_range_others(start, end);
+#if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE)
+ if (end <= physical_mem_end) {
+ blackfin_icache_flush_range(start, end);
+ flush_icache_range_others(start, end);
+ }
+#endif
+#if defined(CONFIG_BFIN_L2_ICACHEABLE)
+ if (start >= L2_START && end <= L2_START + L2_LENGTH) {
+ blackfin_icache_flush_range(start, end);
+ flush_icache_range_others(start, end);
+ }
#endif
}
#include <linux/percpu.h>
-struct task_struct;
-
struct blackfin_cpudata {
struct cpu cpu;
- struct task_struct *idle;
unsigned int imemctl;
unsigned int dmemctl;
};
#define bfin_read(addr) \
({ \
- sizeof(*(addr)) == 1 ? bfin_read8(addr) : \
- sizeof(*(addr)) == 2 ? bfin_read16(addr) : \
- sizeof(*(addr)) == 4 ? bfin_read32(addr) : \
- ({ BUG(); 0; }); \
+ sizeof(*(addr)) == 1 ? bfin_read8(addr) : \
+ sizeof(*(addr)) == 2 ? bfin_read16(addr) : \
+ sizeof(*(addr)) == 4 ? bfin_read32(addr) : \
+ ({ BUG(); 0; }); \
})
#define bfin_write(addr, val) \
do { \
#define bfin_write_or(addr, bits) \
do { \
- void *__addr = (void *)(addr); \
+ typeof(addr) __addr = (addr); \
bfin_write(__addr, bfin_read(__addr) | (bits)); \
} while (0)
#define bfin_write_and(addr, bits) \
do { \
- void *__addr = (void *)(addr); \
+ typeof(addr) __addr = (addr); \
bfin_write(__addr, bfin_read(__addr) & (bits)); \
} while (0)
#include <linux/types.h>
#include <linux/linkage.h>
+/* init functions only */
+extern int __init init_arch_irq(void);
+extern void init_exception_vectors(void);
+extern void __init program_IAR(void);
+#ifdef init_mach_irq
+extern void __init init_mach_irq(void);
+#else
+# define init_mach_irq()
+#endif
+
/* BASE LEVEL interrupt handler routines */
asmlinkage void evt_exception(void);
asmlinkage void trap(void);
extern int bfin_request_exception(unsigned int exception, void (*handler)(void));
extern int bfin_free_exception(unsigned int exception, void (*handler)(void));
+extern asmlinkage void lower_to_irq14(void);
+extern asmlinkage void bfin_return_from_exception(void);
+extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
+extern int bfin_internal_set_wake(unsigned int irq, unsigned int state);
+
+struct irq_data;
+extern void bfin_handle_irq(unsigned irq);
+extern void bfin_ack_noop(struct irq_data *);
+extern void bfin_internal_mask_irq(unsigned int irq);
+extern void bfin_internal_unmask_irq(unsigned int irq);
+
+struct irq_desc;
+extern void bfin_demux_mac_status_irq(unsigned int, struct irq_desc *);
+extern void bfin_demux_gpio_irq(unsigned int, struct irq_desc *);
+
#endif
asm("EXCPT 2;");
}
#define BREAK_INSTR_SIZE 2
-#define CACHE_FLUSH_IS_SAFE 1
+#ifdef CONFIG_SMP
+# define CACHE_FLUSH_IS_SAFE 0
+#else
+# define CACHE_FLUSH_IS_SAFE 1
+#endif
#define HW_INST_WATCHPOINT_NUM 6
#define HW_WATCHPOINT_NUM 8
#define TYPE_INST_WATCHPOINT 0
--- /dev/null
+#define MAX_HWEVENTS 2
extern void show_regs(struct pt_regs *);
#define arch_has_single_step() (1)
-extern void user_enable_single_step(struct task_struct *child);
-extern void user_disable_single_step(struct task_struct *child);
/* common code demands this function */
#define ptrace_disable(child) user_disable_single_step(child)
--- /dev/null
+/*
+ * Common Blackfin IRQ definitions (i.e. the CEC)
+ *
+ * Copyright 2005-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later
+ */
+
+#ifndef _MACH_COMMON_IRQ_H_
+#define _MACH_COMMON_IRQ_H_
+
+/*
+ * Core events interrupt source definitions
+ *
+ * Event Source Event Name
+ * Emulation EMU 0 (highest priority)
+ * Reset RST 1
+ * NMI NMI 2
+ * Exception EVX 3
+ * Reserved -- 4
+ * Hardware Error IVHW 5
+ * Core Timer IVTMR 6
+ * Peripherals IVG7 7
+ * Peripherals IVG8 8
+ * Peripherals IVG9 9
+ * Peripherals IVG10 10
+ * Peripherals IVG11 11
+ * Peripherals IVG12 12
+ * Peripherals IVG13 13
+ * Softirq IVG14 14
+ * System Call IVG15 15 (lowest priority)
+ */
+
+/* The ABSTRACT IRQ definitions */
+#define IRQ_EMU 0 /* Emulation */
+#define IRQ_RST 1 /* reset */
+#define IRQ_NMI 2 /* Non Maskable */
+#define IRQ_EVX 3 /* Exception */
+#define IRQ_UNUSED 4 /* - unused interrupt */
+#define IRQ_HWERR 5 /* Hardware Error */
+#define IRQ_CORETMR 6 /* Core timer */
+
+#define BFIN_IRQ(x) ((x) + 7)
+
+#define IVG7 7
+#define IVG8 8
+#define IVG9 9
+#define IVG10 10
+#define IVG11 11
+#define IVG12 12
+#define IVG13 13
+#define IVG14 14
+#define IVG15 15
+
+#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
+
+#endif
obj-$(CONFIG_STACKTRACE) += stacktrace.o
obj-$(CONFIG_DEBUG_VERBOSE) += trace.o
obj-$(CONFIG_BFIN_PSEUDODBG_INSNS) += pseudodbg.o
+obj-$(CONFIG_PERF_EVENTS) += perf_event.o
# the kgdb test puts code into L2 and without linker
# relaxation, we need to force long calls to/from it
CFLAGS_kgdb_test.o := -mlong-calls -O0
+
+obj-$(CONFIG_DEBUG_MMRS) += debug-mmrs.o
printk(KERN_INFO "Blackfin DMA Controller\n");
+
+#if ANOMALY_05000480
+ bfin_write_DMAC_TC_PER(0x0111);
+#endif
+
for (i = 0; i < MAX_DMA_CHANNELS; i++) {
atomic_set(&dma_ch[i].chan_status, 0);
dma_ch[i].regs = dma_io_base_addr[i];
#include <linux/module.h>
#include <linux/err.h>
#include <linux/proc_fs.h>
+#include <linux/seq_file.h>
#include <asm/blackfin.h>
#include <asm/gpio.h>
#include <asm/portmux.h>
#include <linux/irq.h>
+#include <asm/irq_handler.h>
#if ANOMALY_05000311 || ANOMALY_05000323
enum {
#if defined(BF533_FAMILY)
IRQ_PROG_INTB
#elif defined(BF537_FAMILY)
- IRQ_PROG_INTB, IRQ_PORTG_INTB, IRQ_MAC_TX
+ IRQ_PF_INTB_WATCH, IRQ_PORTG_INTB, IRQ_PH_INTB_MAC_TX
#elif defined(BF538_FAMILY)
IRQ_PORTF_INTB
#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
}
#if defined(CONFIG_PROC_FS)
-static int gpio_proc_read(char *buf, char **start, off_t offset,
- int len, int *unused_i, void *unused_v)
+static int gpio_proc_show(struct seq_file *m, void *v)
{
- int c, irq, gpio, outlen = 0;
+ int c, irq, gpio;
for (c = 0; c < MAX_RESOURCES; c++) {
irq = is_reserved(gpio_irq, c, 1);
gpio = is_reserved(gpio, c, 1);
if (!check_gpio(c) && (gpio || irq))
- len = sprintf(buf, "GPIO_%d: \t%s%s \t\tGPIO %s\n", c,
+ seq_printf(m, "GPIO_%d: \t%s%s \t\tGPIO %s\n", c,
get_label(c), (gpio && irq) ? " *" : "",
get_gpio_dir(c) ? "OUTPUT" : "INPUT");
else if (is_reserved(peri, c, 1))
- len = sprintf(buf, "GPIO_%d: \t%s \t\tPeripheral\n", c, get_label(c));
+ seq_printf(m, "GPIO_%d: \t%s \t\tPeripheral\n", c, get_label(c));
else
continue;
- buf += len;
- outlen += len;
}
- return outlen;
+
+ return 0;
}
+static int gpio_proc_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, gpio_proc_show, NULL);
+}
+
+static const struct file_operations gpio_proc_ops = {
+ .open = gpio_proc_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
static __init int gpio_register_proc(void)
{
struct proc_dir_entry *proc_gpio;
- proc_gpio = create_proc_entry("gpio", S_IRUGO, NULL);
- if (proc_gpio)
- proc_gpio->read_proc = gpio_proc_read;
+ proc_gpio = proc_create("gpio", S_IRUGO, NULL, &gpio_proc_ops);
return proc_gpio != NULL;
}
__initcall(gpio_register_proc);
#include <asm/cacheflush.h>
#include <asm/io.h>
+#include <asm/irq_handler.h>
/* Allow people to have their own Blackfin exception handler in a module */
EXPORT_SYMBOL(bfin_return_from_exception);
--- /dev/null
+/*
+ * debugfs interface to core/system MMRs
+ *
+ * Copyright 2007-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later
+ */
+
+#include <linux/debugfs.h>
+#include <linux/fs.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include <asm/blackfin.h>
+#include <asm/gpio.h>
+#include <asm/bfin_can.h>
+#include <asm/bfin_dma.h>
+#include <asm/bfin_ppi.h>
+#include <asm/bfin_serial.h>
+#include <asm/bfin5xx_spi.h>
+#include <asm/bfin_twi.h>
+
+/* Common code defines PORT_MUX on us, so redirect the MMR back locally */
+#ifdef BFIN_PORT_MUX
+#undef PORT_MUX
+#define PORT_MUX BFIN_PORT_MUX
+#endif
+
+#define _d(name, bits, addr, perms) debugfs_create_x##bits(name, perms, parent, (u##bits *)addr)
+#define d(name, bits, addr) _d(name, bits, addr, S_IRUSR|S_IWUSR)
+#define d_RO(name, bits, addr) _d(name, bits, addr, S_IRUSR)
+#define d_WO(name, bits, addr) _d(name, bits, addr, S_IWUSR)
+
+#define D_RO(name, bits) d_RO(#name, bits, name)
+#define D_WO(name, bits) d_WO(#name, bits, name)
+#define D32(name) d(#name, 32, name)
+#define D16(name) d(#name, 16, name)
+
+#define REGS_OFF(peri, mmr) offsetof(struct bfin_##peri##_regs, mmr)
+#define __REGS(peri, sname, rname) \
+ do { \
+ struct bfin_##peri##_regs r; \
+ void *addr = (void *)(base + REGS_OFF(peri, rname)); \
+ strcpy(_buf, sname); \
+ if (sizeof(r.rname) == 2) \
+ debugfs_create_x16(buf, S_IRUSR|S_IWUSR, parent, addr); \
+ else \
+ debugfs_create_x32(buf, S_IRUSR|S_IWUSR, parent, addr); \
+ } while (0)
+#define REGS_STR_PFX(buf, pfx, num) \
+ ({ \
+ buf + (num >= 0 ? \
+ sprintf(buf, #pfx "%i_", num) : \
+ sprintf(buf, #pfx "_")); \
+ })
+#define REGS_STR_PFX_C(buf, pfx, num) \
+ ({ \
+ buf + (num >= 0 ? \
+ sprintf(buf, #pfx "%c_", 'A' + num) : \
+ sprintf(buf, #pfx "_")); \
+ })
+
+/*
+ * Core registers (not memory mapped)
+ */
+extern u32 last_seqstat;
+
+static int debug_cclk_get(void *data, u64 *val)
+{
+ *val = get_cclk();
+ return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(fops_debug_cclk, debug_cclk_get, NULL, "0x%08llx\n");
+
+static int debug_sclk_get(void *data, u64 *val)
+{
+ *val = get_sclk();
+ return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(fops_debug_sclk, debug_sclk_get, NULL, "0x%08llx\n");
+
+#define DEFINE_SYSREG(sr, pre, post) \
+static int sysreg_##sr##_get(void *data, u64 *val) \
+{ \
+ unsigned long tmp; \
+ pre; \
+ __asm__ __volatile__("%0 = " #sr ";" : "=d"(tmp)); \
+ *val = tmp; \
+ return 0; \
+} \
+static int sysreg_##sr##_set(void *data, u64 val) \
+{ \
+ unsigned long tmp = val; \
+ __asm__ __volatile__(#sr " = %0;" : : "d"(tmp)); \
+ post; \
+ return 0; \
+} \
+DEFINE_SIMPLE_ATTRIBUTE(fops_sysreg_##sr, sysreg_##sr##_get, sysreg_##sr##_set, "0x%08llx\n")
+
+DEFINE_SYSREG(cycles, , );
+DEFINE_SYSREG(cycles2, __asm__ __volatile__("%0 = cycles;" : "=d"(tmp)), );
+DEFINE_SYSREG(emudat, , );
+DEFINE_SYSREG(seqstat, , );
+DEFINE_SYSREG(syscfg, , CSYNC());
+#define D_SYSREG(sr) debugfs_create_file(#sr, S_IRUSR|S_IWUSR, parent, NULL, &fops_sysreg_##sr)
+
+/*
+ * CAN
+ */
+#define CAN_OFF(mmr) REGS_OFF(can, mmr)
+#define __CAN(uname, lname) __REGS(can, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_can(struct dentry *parent, unsigned long base, int num)
+{
+ static struct dentry *am, *mb;
+ int i, j;
+ char buf[32], *_buf = REGS_STR_PFX(buf, CAN, num);
+
+ if (!am) {
+ am = debugfs_create_dir("am", parent);
+ mb = debugfs_create_dir("mb", parent);
+ }
+
+ __CAN(MC1, mc1);
+ __CAN(MD1, md1);
+ __CAN(TRS1, trs1);
+ __CAN(TRR1, trr1);
+ __CAN(TA1, ta1);
+ __CAN(AA1, aa1);
+ __CAN(RMP1, rmp1);
+ __CAN(RML1, rml1);
+ __CAN(MBTIF1, mbtif1);
+ __CAN(MBRIF1, mbrif1);
+ __CAN(MBIM1, mbim1);
+ __CAN(RFH1, rfh1);
+ __CAN(OPSS1, opss1);
+
+ __CAN(MC2, mc2);
+ __CAN(MD2, md2);
+ __CAN(TRS2, trs2);
+ __CAN(TRR2, trr2);
+ __CAN(TA2, ta2);
+ __CAN(AA2, aa2);
+ __CAN(RMP2, rmp2);
+ __CAN(RML2, rml2);
+ __CAN(MBTIF2, mbtif2);
+ __CAN(MBRIF2, mbrif2);
+ __CAN(MBIM2, mbim2);
+ __CAN(RFH2, rfh2);
+ __CAN(OPSS2, opss2);
+
+ __CAN(CLOCK, clock);
+ __CAN(TIMING, timing);
+ __CAN(DEBUG, debug);
+ __CAN(STATUS, status);
+ __CAN(CEC, cec);
+ __CAN(GIS, gis);
+ __CAN(GIM, gim);
+ __CAN(GIF, gif);
+ __CAN(CONTROL, control);
+ __CAN(INTR, intr);
+ __CAN(VERSION, version);
+ __CAN(MBTD, mbtd);
+ __CAN(EWR, ewr);
+ __CAN(ESR, esr);
+ /*__CAN(UCREG, ucreg); no longer exists */
+ __CAN(UCCNT, uccnt);
+ __CAN(UCRC, ucrc);
+ __CAN(UCCNF, uccnf);
+ __CAN(VERSION2, version2);
+
+ for (i = 0; i < 32; ++i) {
+ sprintf(_buf, "AM%02iL", i);
+ debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
+ (u16 *)(base + CAN_OFF(msk[i].aml)));
+ sprintf(_buf, "AM%02iH", i);
+ debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
+ (u16 *)(base + CAN_OFF(msk[i].amh)));
+
+ for (j = 0; j < 3; ++j) {
+ sprintf(_buf, "MB%02i_DATA%i", i, j);
+ debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
+ (u16 *)(base + CAN_OFF(chl[i].data[j*2])));
+ }
+ sprintf(_buf, "MB%02i_LENGTH", i);
+ debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
+ (u16 *)(base + CAN_OFF(chl[i].dlc)));
+ sprintf(_buf, "MB%02i_TIMESTAMP", i);
+ debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
+ (u16 *)(base + CAN_OFF(chl[i].tsv)));
+ sprintf(_buf, "MB%02i_ID0", i);
+ debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
+ (u16 *)(base + CAN_OFF(chl[i].id0)));
+ sprintf(_buf, "MB%02i_ID1", i);
+ debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
+ (u16 *)(base + CAN_OFF(chl[i].id1)));
+ }
+}
+#define CAN(num) bfin_debug_mmrs_can(parent, CAN##num##_MC1, num)
+
+/*
+ * DMA
+ */
+#define __DMA(uname, lname) __REGS(dma, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_dma(struct dentry *parent, unsigned long base, int num, char mdma, const char *pfx)
+{
+ char buf[32], *_buf;
+
+ if (mdma)
+ _buf = buf + sprintf(buf, "%s_%c%i_", pfx, mdma, num);
+ else
+ _buf = buf + sprintf(buf, "%s%i_", pfx, num);
+
+ __DMA(NEXT_DESC_PTR, next_desc_ptr);
+ __DMA(START_ADDR, start_addr);
+ __DMA(CONFIG, config);
+ __DMA(X_COUNT, x_count);
+ __DMA(X_MODIFY, x_modify);
+ __DMA(Y_COUNT, y_count);
+ __DMA(Y_MODIFY, y_modify);
+ __DMA(CURR_DESC_PTR, curr_desc_ptr);
+ __DMA(CURR_ADDR, curr_addr);
+ __DMA(IRQ_STATUS, irq_status);
+ __DMA(PERIPHERAL_MAP, peripheral_map);
+ __DMA(CURR_X_COUNT, curr_x_count);
+ __DMA(CURR_Y_COUNT, curr_y_count);
+}
+#define _DMA(num, base, mdma, pfx) bfin_debug_mmrs_dma(parent, base, num, mdma, pfx "DMA")
+#define DMA(num) _DMA(num, DMA##num##_NEXT_DESC_PTR, 0, "")
+#define _MDMA(num, x) \
+ do { \
+ _DMA(num, x##DMA_D##num##_CONFIG, 'D', #x); \
+ _DMA(num, x##DMA_S##num##_CONFIG, 'S', #x); \
+ } while (0)
+#define MDMA(num) _MDMA(num, M)
+#define IMDMA(num) _MDMA(num, IM)
+
+/*
+ * EPPI
+ */
+#define __EPPI(uname, lname) __REGS(eppi, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_eppi(struct dentry *parent, unsigned long base, int num)
+{
+ char buf[32], *_buf = REGS_STR_PFX(buf, EPPI, num);
+ __EPPI(STATUS, status);
+ __EPPI(HCOUNT, hcount);
+ __EPPI(HDELAY, hdelay);
+ __EPPI(VCOUNT, vcount);
+ __EPPI(VDELAY, vdelay);
+ __EPPI(FRAME, frame);
+ __EPPI(LINE, line);
+ __EPPI(CLKDIV, clkdiv);
+ __EPPI(CONTROL, control);
+ __EPPI(FS1W_HBL, fs1w_hbl);
+ __EPPI(FS1P_AVPL, fs1p_avpl);
+ __EPPI(FS2W_LVB, fs2w_lvb);
+ __EPPI(FS2P_LAVF, fs2p_lavf);
+ __EPPI(CLIP, clip);
+}
+#define EPPI(num) bfin_debug_mmrs_eppi(parent, EPPI##num##_STATUS, num)
+
+/*
+ * General Purpose Timers
+ */
+#define GPTIMER_OFF(mmr) (TIMER0_##mmr - TIMER0_CONFIG)
+#define __GPTIMER(name) \
+ do { \
+ strcpy(_buf, #name); \
+ debugfs_create_x16(buf, S_IRUSR|S_IWUSR, parent, (u16 *)(base + GPTIMER_OFF(name))); \
+ } while (0)
+static void __init __maybe_unused
+bfin_debug_mmrs_gptimer(struct dentry *parent, unsigned long base, int num)
+{
+ char buf[32], *_buf = REGS_STR_PFX(buf, TIMER, num);
+ __GPTIMER(CONFIG);
+ __GPTIMER(COUNTER);
+ __GPTIMER(PERIOD);
+ __GPTIMER(WIDTH);
+}
+#define GPTIMER(num) bfin_debug_mmrs_gptimer(parent, TIMER##num##_CONFIG, num)
+
+/*
+ * Handshake MDMA
+ */
+#define __HMDMA(uname, lname) __REGS(hmdma, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_hmdma(struct dentry *parent, unsigned long base, int num)
+{
+ char buf[32], *_buf = REGS_STR_PFX(buf, HMDMA, num);
+ __HMDMA(CONTROL, control);
+ __HMDMA(ECINIT, ecinit);
+ __HMDMA(BCINIT, bcinit);
+ __HMDMA(ECURGENT, ecurgent);
+ __HMDMA(ECOVERFLOW, ecoverflow);
+ __HMDMA(ECOUNT, ecount);
+ __HMDMA(BCOUNT, bcount);
+}
+#define HMDMA(num) bfin_debug_mmrs_hmdma(parent, HMDMA##num##_CONTROL, num)
+
+/*
+ * Port/GPIO
+ */
+#define bfin_gpio_regs gpio_port_t
+#define __PORT(uname, lname) __REGS(gpio, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_port(struct dentry *parent, unsigned long base, int num)
+{
+ char buf[32], *_buf;
+#ifdef __ADSPBF54x__
+ _buf = REGS_STR_PFX_C(buf, PORT, num);
+ __PORT(FER, port_fer);
+ __PORT(SET, data_set);
+ __PORT(CLEAR, data_clear);
+ __PORT(DIR_SET, dir_set);
+ __PORT(DIR_CLEAR, dir_clear);
+ __PORT(INEN, inen);
+ __PORT(MUX, port_mux);
+#else
+ _buf = buf + sprintf(buf, "PORT%cIO_", num);
+ __PORT(CLEAR, data_clear);
+ __PORT(SET, data_set);
+ __PORT(TOGGLE, toggle);
+ __PORT(MASKA, maska);
+ __PORT(MASKA_CLEAR, maska_clear);
+ __PORT(MASKA_SET, maska_set);
+ __PORT(MASKA_TOGGLE, maska_toggle);
+ __PORT(MASKB, maskb);
+ __PORT(MASKB_CLEAR, maskb_clear);
+ __PORT(MASKB_SET, maskb_set);
+ __PORT(MASKB_TOGGLE, maskb_toggle);
+ __PORT(DIR, dir);
+ __PORT(POLAR, polar);
+ __PORT(EDGE, edge);
+ __PORT(BOTH, both);
+ __PORT(INEN, inen);
+#endif
+ _buf[-1] = '\0';
+ d(buf, 16, base + REGS_OFF(gpio, data));
+}
+#define PORT(base, num) bfin_debug_mmrs_port(parent, base, num)
+
+/*
+ * PPI
+ */
+#define __PPI(uname, lname) __REGS(ppi, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_ppi(struct dentry *parent, unsigned long base, int num)
+{
+ char buf[32], *_buf = REGS_STR_PFX(buf, PPI, num);
+ __PPI(CONTROL, control);
+ __PPI(STATUS, status);
+ __PPI(COUNT, count);
+ __PPI(DELAY, delay);
+ __PPI(FRAME, frame);
+}
+#define PPI(num) bfin_debug_mmrs_ppi(parent, PPI##num##_STATUS, num)
+
+/*
+ * SPI
+ */
+#define __SPI(uname, lname) __REGS(spi, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_spi(struct dentry *parent, unsigned long base, int num)
+{
+ char buf[32], *_buf = REGS_STR_PFX(buf, SPI, num);
+ __SPI(CTL, ctl);
+ __SPI(FLG, flg);
+ __SPI(STAT, stat);
+ __SPI(TDBR, tdbr);
+ __SPI(RDBR, rdbr);
+ __SPI(BAUD, baud);
+ __SPI(SHADOW, shadow);
+}
+#define SPI(num) bfin_debug_mmrs_spi(parent, SPI##num##_REGBASE, num)
+
+/*
+ * SPORT
+ */
+static inline int sport_width(void *mmr)
+{
+ unsigned long lmmr = (unsigned long)mmr;
+ if ((lmmr & 0xff) == 0x10)
+ /* SPORT#_TX has 0x10 offset -> SPORT#_TCR2 has 0x04 offset */
+ lmmr -= 0xc;
+ else
+ /* SPORT#_RX has 0x18 offset -> SPORT#_RCR2 has 0x24 offset */
+ lmmr += 0xc;
+ /* extract SLEN field from control register 2 and add 1 */
+ return (bfin_read16(lmmr) & 0x1f) + 1;
+}
+static int sport_set(void *mmr, u64 val)
+{
+ unsigned long flags;
+ local_irq_save(flags);
+ if (sport_width(mmr) <= 16)
+ bfin_write16(mmr, val);
+ else
+ bfin_write32(mmr, val);
+ local_irq_restore(flags);
+ return 0;
+}
+static int sport_get(void *mmr, u64 *val)
+{
+ unsigned long flags;
+ local_irq_save(flags);
+ if (sport_width(mmr) <= 16)
+ *val = bfin_read16(mmr);
+ else
+ *val = bfin_read32(mmr);
+ local_irq_restore(flags);
+ return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(fops_sport, sport_get, sport_set, "0x%08llx\n");
+/*DEFINE_SIMPLE_ATTRIBUTE(fops_sport_ro, sport_get, NULL, "0x%08llx\n");*/
+DEFINE_SIMPLE_ATTRIBUTE(fops_sport_wo, NULL, sport_set, "0x%08llx\n");
+#define SPORT_OFF(mmr) (SPORT0_##mmr - SPORT0_TCR1)
+#define _D_SPORT(name, perms, fops) \
+ do { \
+ strcpy(_buf, #name); \
+ debugfs_create_file(buf, perms, parent, (void *)(base + SPORT_OFF(name)), fops); \
+ } while (0)
+#define __SPORT_RW(name) _D_SPORT(name, S_IRUSR|S_IWUSR, &fops_sport)
+#define __SPORT_RO(name) _D_SPORT(name, S_IRUSR, &fops_sport_ro)
+#define __SPORT_WO(name) _D_SPORT(name, S_IWUSR, &fops_sport_wo)
+#define __SPORT(name, bits) \
+ do { \
+ strcpy(_buf, #name); \
+ debugfs_create_x##bits(buf, S_IRUSR|S_IWUSR, parent, (u##bits *)(base + SPORT_OFF(name))); \
+ } while (0)
+static void __init __maybe_unused
+bfin_debug_mmrs_sport(struct dentry *parent, unsigned long base, int num)
+{
+ char buf[32], *_buf = REGS_STR_PFX(buf, SPORT, num);
+ __SPORT(CHNL, 16);
+ __SPORT(MCMC1, 16);
+ __SPORT(MCMC2, 16);
+ __SPORT(MRCS0, 32);
+ __SPORT(MRCS1, 32);
+ __SPORT(MRCS2, 32);
+ __SPORT(MRCS3, 32);
+ __SPORT(MTCS0, 32);
+ __SPORT(MTCS1, 32);
+ __SPORT(MTCS2, 32);
+ __SPORT(MTCS3, 32);
+ __SPORT(RCLKDIV, 16);
+ __SPORT(RCR1, 16);
+ __SPORT(RCR2, 16);
+ __SPORT(RFSDIV, 16);
+ __SPORT_RW(RX);
+ __SPORT(STAT, 16);
+ __SPORT(TCLKDIV, 16);
+ __SPORT(TCR1, 16);
+ __SPORT(TCR2, 16);
+ __SPORT(TFSDIV, 16);
+ __SPORT_WO(TX);
+}
+#define SPORT(num) bfin_debug_mmrs_sport(parent, SPORT##num##_TCR1, num)
+
+/*
+ * TWI
+ */
+#define __TWI(uname, lname) __REGS(twi, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_twi(struct dentry *parent, unsigned long base, int num)
+{
+ char buf[32], *_buf = REGS_STR_PFX(buf, TWI, num);
+ __TWI(CLKDIV, clkdiv);
+ __TWI(CONTROL, control);
+ __TWI(SLAVE_CTL, slave_ctl);
+ __TWI(SLAVE_STAT, slave_stat);
+ __TWI(SLAVE_ADDR, slave_addr);
+ __TWI(MASTER_CTL, master_ctl);
+ __TWI(MASTER_STAT, master_stat);
+ __TWI(MASTER_ADDR, master_addr);
+ __TWI(INT_STAT, int_stat);
+ __TWI(INT_MASK, int_mask);
+ __TWI(FIFO_CTL, fifo_ctl);
+ __TWI(FIFO_STAT, fifo_stat);
+ __TWI(XMT_DATA8, xmt_data8);
+ __TWI(XMT_DATA16, xmt_data16);
+ __TWI(RCV_DATA8, rcv_data8);
+ __TWI(RCV_DATA16, rcv_data16);
+}
+#define TWI(num) bfin_debug_mmrs_twi(parent, TWI##num##_CLKDIV, num)
+
+/*
+ * UART
+ */
+#define __UART(uname, lname) __REGS(uart, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_uart(struct dentry *parent, unsigned long base, int num)
+{
+ char buf[32], *_buf = REGS_STR_PFX(buf, UART, num);
+#ifdef BFIN_UART_BF54X_STYLE
+ __UART(DLL, dll);
+ __UART(DLH, dlh);
+ __UART(GCTL, gctl);
+ __UART(LCR, lcr);
+ __UART(MCR, mcr);
+ __UART(LSR, lsr);
+ __UART(MSR, msr);
+ __UART(SCR, scr);
+ __UART(IER_SET, ier_set);
+ __UART(IER_CLEAR, ier_clear);
+ __UART(THR, thr);
+ __UART(RBR, rbr);
+#else
+ __UART(DLL, dll);
+ __UART(THR, thr);
+ __UART(RBR, rbr);
+ __UART(DLH, dlh);
+ __UART(IER, ier);
+ __UART(IIR, iir);
+ __UART(LCR, lcr);
+ __UART(MCR, mcr);
+ __UART(LSR, lsr);
+ __UART(MSR, msr);
+ __UART(SCR, scr);
+ __UART(GCTL, gctl);
+#endif
+}
+#define UART(num) bfin_debug_mmrs_uart(parent, UART##num##_DLL, num)
+
+/*
+ * The actual debugfs generation
+ */
+static struct dentry *debug_mmrs_dentry;
+
+static int __init bfin_debug_mmrs_init(void)
+{
+ struct dentry *top, *parent;
+
+ pr_info("debug-mmrs: setting up Blackfin MMR debugfs\n");
+
+ top = debugfs_create_dir("blackfin", NULL);
+ if (top == NULL)
+ return -1;
+
+ parent = debugfs_create_dir("core_regs", top);
+ debugfs_create_file("cclk", S_IRUSR, parent, NULL, &fops_debug_cclk);
+ debugfs_create_file("sclk", S_IRUSR, parent, NULL, &fops_debug_sclk);
+ debugfs_create_x32("last_seqstat", S_IRUSR, parent, &last_seqstat);
+ D_SYSREG(cycles);
+ D_SYSREG(cycles2);
+ D_SYSREG(emudat);
+ D_SYSREG(seqstat);
+ D_SYSREG(syscfg);
+
+ /* Core MMRs */
+ parent = debugfs_create_dir("ctimer", top);
+ D32(TCNTL);
+ D32(TCOUNT);
+ D32(TPERIOD);
+ D32(TSCALE);
+
+ parent = debugfs_create_dir("cec", top);
+ D32(EVT0);
+ D32(EVT1);
+ D32(EVT2);
+ D32(EVT3);
+ D32(EVT4);
+ D32(EVT5);
+ D32(EVT6);
+ D32(EVT7);
+ D32(EVT8);
+ D32(EVT9);
+ D32(EVT10);
+ D32(EVT11);
+ D32(EVT12);
+ D32(EVT13);
+ D32(EVT14);
+ D32(EVT15);
+ D32(EVT_OVERRIDE);
+ D32(IMASK);
+ D32(IPEND);
+ D32(ILAT);
+ D32(IPRIO);
+
+ parent = debugfs_create_dir("debug", top);
+ D32(DBGSTAT);
+ D32(DSPID);
+
+ parent = debugfs_create_dir("mmu", top);
+ D32(SRAM_BASE_ADDRESS);
+ D32(DCPLB_ADDR0);
+ D32(DCPLB_ADDR10);
+ D32(DCPLB_ADDR11);
+ D32(DCPLB_ADDR12);
+ D32(DCPLB_ADDR13);
+ D32(DCPLB_ADDR14);
+ D32(DCPLB_ADDR15);
+ D32(DCPLB_ADDR1);
+ D32(DCPLB_ADDR2);
+ D32(DCPLB_ADDR3);
+ D32(DCPLB_ADDR4);
+ D32(DCPLB_ADDR5);
+ D32(DCPLB_ADDR6);
+ D32(DCPLB_ADDR7);
+ D32(DCPLB_ADDR8);
+ D32(DCPLB_ADDR9);
+ D32(DCPLB_DATA0);
+ D32(DCPLB_DATA10);
+ D32(DCPLB_DATA11);
+ D32(DCPLB_DATA12);
+ D32(DCPLB_DATA13);
+ D32(DCPLB_DATA14);
+ D32(DCPLB_DATA15);
+ D32(DCPLB_DATA1);
+ D32(DCPLB_DATA2);
+ D32(DCPLB_DATA3);
+ D32(DCPLB_DATA4);
+ D32(DCPLB_DATA5);
+ D32(DCPLB_DATA6);
+ D32(DCPLB_DATA7);
+ D32(DCPLB_DATA8);
+ D32(DCPLB_DATA9);
+ D32(DCPLB_FAULT_ADDR);
+ D32(DCPLB_STATUS);
+ D32(DMEM_CONTROL);
+ D32(DTEST_COMMAND);
+ D32(DTEST_DATA0);
+ D32(DTEST_DATA1);
+
+ D32(ICPLB_ADDR0);
+ D32(ICPLB_ADDR1);
+ D32(ICPLB_ADDR2);
+ D32(ICPLB_ADDR3);
+ D32(ICPLB_ADDR4);
+ D32(ICPLB_ADDR5);
+ D32(ICPLB_ADDR6);
+ D32(ICPLB_ADDR7);
+ D32(ICPLB_ADDR8);
+ D32(ICPLB_ADDR9);
+ D32(ICPLB_ADDR10);
+ D32(ICPLB_ADDR11);
+ D32(ICPLB_ADDR12);
+ D32(ICPLB_ADDR13);
+ D32(ICPLB_ADDR14);
+ D32(ICPLB_ADDR15);
+ D32(ICPLB_DATA0);
+ D32(ICPLB_DATA1);
+ D32(ICPLB_DATA2);
+ D32(ICPLB_DATA3);
+ D32(ICPLB_DATA4);
+ D32(ICPLB_DATA5);
+ D32(ICPLB_DATA6);
+ D32(ICPLB_DATA7);
+ D32(ICPLB_DATA8);
+ D32(ICPLB_DATA9);
+ D32(ICPLB_DATA10);
+ D32(ICPLB_DATA11);
+ D32(ICPLB_DATA12);
+ D32(ICPLB_DATA13);
+ D32(ICPLB_DATA14);
+ D32(ICPLB_DATA15);
+ D32(ICPLB_FAULT_ADDR);
+ D32(ICPLB_STATUS);
+ D32(IMEM_CONTROL);
+ if (!ANOMALY_05000481) {
+ D32(ITEST_COMMAND);
+ D32(ITEST_DATA0);
+ D32(ITEST_DATA1);
+ }
+
+ parent = debugfs_create_dir("perf", top);
+ D32(PFCNTR0);
+ D32(PFCNTR1);
+ D32(PFCTL);
+
+ parent = debugfs_create_dir("trace", top);
+ D32(TBUF);
+ D32(TBUFCTL);
+ D32(TBUFSTAT);
+
+ parent = debugfs_create_dir("watchpoint", top);
+ D32(WPIACTL);
+ D32(WPIA0);
+ D32(WPIA1);
+ D32(WPIA2);
+ D32(WPIA3);
+ D32(WPIA4);
+ D32(WPIA5);
+ D32(WPIACNT0);
+ D32(WPIACNT1);
+ D32(WPIACNT2);
+ D32(WPIACNT3);
+ D32(WPIACNT4);
+ D32(WPIACNT5);
+ D32(WPDACTL);
+ D32(WPDA0);
+ D32(WPDA1);
+ D32(WPDACNT0);
+ D32(WPDACNT1);
+ D32(WPSTAT);
+
+ /* System MMRs */
+#ifdef ATAPI_CONTROL
+ parent = debugfs_create_dir("atapi", top);
+ D16(ATAPI_CONTROL);
+ D16(ATAPI_DEV_ADDR);
+ D16(ATAPI_DEV_RXBUF);
+ D16(ATAPI_DEV_TXBUF);
+ D16(ATAPI_DMA_TFRCNT);
+ D16(ATAPI_INT_MASK);
+ D16(ATAPI_INT_STATUS);
+ D16(ATAPI_LINE_STATUS);
+ D16(ATAPI_MULTI_TIM_0);
+ D16(ATAPI_MULTI_TIM_1);
+ D16(ATAPI_MULTI_TIM_2);
+ D16(ATAPI_PIO_TFRCNT);
+ D16(ATAPI_PIO_TIM_0);
+ D16(ATAPI_PIO_TIM_1);
+ D16(ATAPI_REG_TIM_0);
+ D16(ATAPI_SM_STATE);
+ D16(ATAPI_STATUS);
+ D16(ATAPI_TERMINATE);
+ D16(ATAPI_UDMAOUT_TFRCNT);
+ D16(ATAPI_ULTRA_TIM_0);
+ D16(ATAPI_ULTRA_TIM_1);
+ D16(ATAPI_ULTRA_TIM_2);
+ D16(ATAPI_ULTRA_TIM_3);
+ D16(ATAPI_UMAIN_TFRCNT);
+ D16(ATAPI_XFER_LEN);
+#endif
+
+#if defined(CAN_MC1) || defined(CAN0_MC1) || defined(CAN1_MC1)
+ parent = debugfs_create_dir("can", top);
+# ifdef CAN_MC1
+ bfin_debug_mmrs_can(parent, CAN_MC1, -1);
+# endif
+# ifdef CAN0_MC1
+ CAN(0);
+# endif
+# ifdef CAN1_MC1
+ CAN(1);
+# endif
+#endif
+
+#ifdef CNT_COMMAND
+ parent = debugfs_create_dir("counter", top);
+ D16(CNT_COMMAND);
+ D16(CNT_CONFIG);
+ D32(CNT_COUNTER);
+ D16(CNT_DEBOUNCE);
+ D16(CNT_IMASK);
+ D32(CNT_MAX);
+ D32(CNT_MIN);
+ D16(CNT_STATUS);
+#endif
+
+ parent = debugfs_create_dir("dmac", top);
+#ifdef DMA_TC_CNT
+ D16(DMAC_TC_CNT);
+ D16(DMAC_TC_PER);
+#endif
+#ifdef DMAC0_TC_CNT
+ D16(DMAC0_TC_CNT);
+ D16(DMAC0_TC_PER);
+#endif
+#ifdef DMAC1_TC_CNT
+ D16(DMAC1_TC_CNT);
+ D16(DMAC1_TC_PER);
+#endif
+#ifdef DMAC1_PERIMUX
+ D16(DMAC1_PERIMUX);
+#endif
+
+#ifdef __ADSPBF561__
+ /* XXX: should rewrite the MMR map */
+# define DMA0_NEXT_DESC_PTR DMA2_0_NEXT_DESC_PTR
+# define DMA1_NEXT_DESC_PTR DMA2_1_NEXT_DESC_PTR
+# define DMA2_NEXT_DESC_PTR DMA2_2_NEXT_DESC_PTR
+# define DMA3_NEXT_DESC_PTR DMA2_3_NEXT_DESC_PTR
+# define DMA4_NEXT_DESC_PTR DMA2_4_NEXT_DESC_PTR
+# define DMA5_NEXT_DESC_PTR DMA2_5_NEXT_DESC_PTR
+# define DMA6_NEXT_DESC_PTR DMA2_6_NEXT_DESC_PTR
+# define DMA7_NEXT_DESC_PTR DMA2_7_NEXT_DESC_PTR
+# define DMA8_NEXT_DESC_PTR DMA2_8_NEXT_DESC_PTR
+# define DMA9_NEXT_DESC_PTR DMA2_9_NEXT_DESC_PTR
+# define DMA10_NEXT_DESC_PTR DMA2_10_NEXT_DESC_PTR
+# define DMA11_NEXT_DESC_PTR DMA2_11_NEXT_DESC_PTR
+# define DMA12_NEXT_DESC_PTR DMA1_0_NEXT_DESC_PTR
+# define DMA13_NEXT_DESC_PTR DMA1_1_NEXT_DESC_PTR
+# define DMA14_NEXT_DESC_PTR DMA1_2_NEXT_DESC_PTR
+# define DMA15_NEXT_DESC_PTR DMA1_3_NEXT_DESC_PTR
+# define DMA16_NEXT_DESC_PTR DMA1_4_NEXT_DESC_PTR
+# define DMA17_NEXT_DESC_PTR DMA1_5_NEXT_DESC_PTR
+# define DMA18_NEXT_DESC_PTR DMA1_6_NEXT_DESC_PTR
+# define DMA19_NEXT_DESC_PTR DMA1_7_NEXT_DESC_PTR
+# define DMA20_NEXT_DESC_PTR DMA1_8_NEXT_DESC_PTR
+# define DMA21_NEXT_DESC_PTR DMA1_9_NEXT_DESC_PTR
+# define DMA22_NEXT_DESC_PTR DMA1_10_NEXT_DESC_PTR
+# define DMA23_NEXT_DESC_PTR DMA1_11_NEXT_DESC_PTR
+#endif
+ parent = debugfs_create_dir("dma", top);
+ DMA(0);
+ DMA(1);
+ DMA(1);
+ DMA(2);
+ DMA(3);
+ DMA(4);
+ DMA(5);
+ DMA(6);
+ DMA(7);
+#ifdef DMA8_NEXT_DESC_PTR
+ DMA(8);
+ DMA(9);
+ DMA(10);
+ DMA(11);
+#endif
+#ifdef DMA12_NEXT_DESC_PTR
+ DMA(12);
+ DMA(13);
+ DMA(14);
+ DMA(15);
+ DMA(16);
+ DMA(17);
+ DMA(18);
+ DMA(19);
+#endif
+#ifdef DMA20_NEXT_DESC_PTR
+ DMA(20);
+ DMA(21);
+ DMA(22);
+ DMA(23);
+#endif
+
+ parent = debugfs_create_dir("ebiu_amc", top);
+ D32(EBIU_AMBCTL0);
+ D32(EBIU_AMBCTL1);
+ D16(EBIU_AMGCTL);
+#ifdef EBIU_MBSCTL
+ D16(EBIU_MBSCTL);
+ D32(EBIU_ARBSTAT);
+ D32(EBIU_MODE);
+ D16(EBIU_FCTL);
+#endif
+
+#ifdef EBIU_SDGCTL
+ parent = debugfs_create_dir("ebiu_sdram", top);
+# ifdef __ADSPBF561__
+ D32(EBIU_SDBCTL);
+# else
+ D16(EBIU_SDBCTL);
+# endif
+ D32(EBIU_SDGCTL);
+ D16(EBIU_SDRRC);
+ D16(EBIU_SDSTAT);
+#endif
+
+#ifdef EBIU_DDRACCT
+ parent = debugfs_create_dir("ebiu_ddr", top);
+ D32(EBIU_DDRACCT);
+ D32(EBIU_DDRARCT);
+ D32(EBIU_DDRBRC0);
+ D32(EBIU_DDRBRC1);
+ D32(EBIU_DDRBRC2);
+ D32(EBIU_DDRBRC3);
+ D32(EBIU_DDRBRC4);
+ D32(EBIU_DDRBRC5);
+ D32(EBIU_DDRBRC6);
+ D32(EBIU_DDRBRC7);
+ D32(EBIU_DDRBWC0);
+ D32(EBIU_DDRBWC1);
+ D32(EBIU_DDRBWC2);
+ D32(EBIU_DDRBWC3);
+ D32(EBIU_DDRBWC4);
+ D32(EBIU_DDRBWC5);
+ D32(EBIU_DDRBWC6);
+ D32(EBIU_DDRBWC7);
+ D32(EBIU_DDRCTL0);
+ D32(EBIU_DDRCTL1);
+ D32(EBIU_DDRCTL2);
+ D32(EBIU_DDRCTL3);
+ D32(EBIU_DDRGC0);
+ D32(EBIU_DDRGC1);
+ D32(EBIU_DDRGC2);
+ D32(EBIU_DDRGC3);
+ D32(EBIU_DDRMCCL);
+ D32(EBIU_DDRMCEN);
+ D32(EBIU_DDRQUE);
+ D32(EBIU_DDRTACT);
+ D32(EBIU_ERRADD);
+ D16(EBIU_ERRMST);
+ D16(EBIU_RSTCTL);
+#endif
+
+#ifdef EMAC_ADDRHI
+ parent = debugfs_create_dir("emac", top);
+ D32(EMAC_ADDRHI);
+ D32(EMAC_ADDRLO);
+ D32(EMAC_FLC);
+ D32(EMAC_HASHHI);
+ D32(EMAC_HASHLO);
+ D32(EMAC_MMC_CTL);
+ D32(EMAC_MMC_RIRQE);
+ D32(EMAC_MMC_RIRQS);
+ D32(EMAC_MMC_TIRQE);
+ D32(EMAC_MMC_TIRQS);
+ D32(EMAC_OPMODE);
+ D32(EMAC_RXC_ALIGN);
+ D32(EMAC_RXC_ALLFRM);
+ D32(EMAC_RXC_ALLOCT);
+ D32(EMAC_RXC_BROAD);
+ D32(EMAC_RXC_DMAOVF);
+ D32(EMAC_RXC_EQ64);
+ D32(EMAC_RXC_FCS);
+ D32(EMAC_RXC_GE1024);
+ D32(EMAC_RXC_LNERRI);
+ D32(EMAC_RXC_LNERRO);
+ D32(EMAC_RXC_LONG);
+ D32(EMAC_RXC_LT1024);
+ D32(EMAC_RXC_LT128);
+ D32(EMAC_RXC_LT256);
+ D32(EMAC_RXC_LT512);
+ D32(EMAC_RXC_MACCTL);
+ D32(EMAC_RXC_MULTI);
+ D32(EMAC_RXC_OCTET);
+ D32(EMAC_RXC_OK);
+ D32(EMAC_RXC_OPCODE);
+ D32(EMAC_RXC_PAUSE);
+ D32(EMAC_RXC_SHORT);
+ D32(EMAC_RXC_TYPED);
+ D32(EMAC_RXC_UNICST);
+ D32(EMAC_RX_IRQE);
+ D32(EMAC_RX_STAT);
+ D32(EMAC_RX_STKY);
+ D32(EMAC_STAADD);
+ D32(EMAC_STADAT);
+ D32(EMAC_SYSCTL);
+ D32(EMAC_SYSTAT);
+ D32(EMAC_TXC_1COL);
+ D32(EMAC_TXC_ABORT);
+ D32(EMAC_TXC_ALLFRM);
+ D32(EMAC_TXC_ALLOCT);
+ D32(EMAC_TXC_BROAD);
+ D32(EMAC_TXC_CRSERR);
+ D32(EMAC_TXC_DEFER);
+ D32(EMAC_TXC_DMAUND);
+ D32(EMAC_TXC_EQ64);
+ D32(EMAC_TXC_GE1024);
+ D32(EMAC_TXC_GT1COL);
+ D32(EMAC_TXC_LATECL);
+ D32(EMAC_TXC_LT1024);
+ D32(EMAC_TXC_LT128);
+ D32(EMAC_TXC_LT256);
+ D32(EMAC_TXC_LT512);
+ D32(EMAC_TXC_MACCTL);
+ D32(EMAC_TXC_MULTI);
+ D32(EMAC_TXC_OCTET);
+ D32(EMAC_TXC_OK);
+ D32(EMAC_TXC_UNICST);
+ D32(EMAC_TXC_XS_COL);
+ D32(EMAC_TXC_XS_DFR);
+ D32(EMAC_TX_IRQE);
+ D32(EMAC_TX_STAT);
+ D32(EMAC_TX_STKY);
+ D32(EMAC_VLAN1);
+ D32(EMAC_VLAN2);
+ D32(EMAC_WKUP_CTL);
+ D32(EMAC_WKUP_FFCMD);
+ D32(EMAC_WKUP_FFCRC0);
+ D32(EMAC_WKUP_FFCRC1);
+ D32(EMAC_WKUP_FFMSK0);
+ D32(EMAC_WKUP_FFMSK1);
+ D32(EMAC_WKUP_FFMSK2);
+ D32(EMAC_WKUP_FFMSK3);
+ D32(EMAC_WKUP_FFOFF);
+# ifdef EMAC_PTP_ACCR
+ D32(EMAC_PTP_ACCR);
+ D32(EMAC_PTP_ADDEND);
+ D32(EMAC_PTP_ALARMHI);
+ D32(EMAC_PTP_ALARMLO);
+ D16(EMAC_PTP_CTL);
+ D32(EMAC_PTP_FOFF);
+ D32(EMAC_PTP_FV1);
+ D32(EMAC_PTP_FV2);
+ D32(EMAC_PTP_FV3);
+ D16(EMAC_PTP_ID_OFF);
+ D32(EMAC_PTP_ID_SNAP);
+ D16(EMAC_PTP_IE);
+ D16(EMAC_PTP_ISTAT);
+ D32(EMAC_PTP_OFFSET);
+ D32(EMAC_PTP_PPS_PERIOD);
+ D32(EMAC_PTP_PPS_STARTHI);
+ D32(EMAC_PTP_PPS_STARTLO);
+ D32(EMAC_PTP_RXSNAPHI);
+ D32(EMAC_PTP_RXSNAPLO);
+ D32(EMAC_PTP_TIMEHI);
+ D32(EMAC_PTP_TIMELO);
+ D32(EMAC_PTP_TXSNAPHI);
+ D32(EMAC_PTP_TXSNAPLO);
+# endif
+#endif
+
+#if defined(EPPI0_STATUS) || defined(EPPI1_STATUS) || defined(EPPI2_STATUS)
+ parent = debugfs_create_dir("eppi", top);
+# ifdef EPPI0_STATUS
+ EPPI(0);
+# endif
+# ifdef EPPI1_STATUS
+ EPPI(1);
+# endif
+# ifdef EPPI2_STATUS
+ EPPI(2);
+# endif
+#endif
+
+ parent = debugfs_create_dir("gptimer", top);
+#ifdef TIMER_DISABLE
+ D16(TIMER_DISABLE);
+ D16(TIMER_ENABLE);
+ D32(TIMER_STATUS);
+#endif
+#ifdef TIMER_DISABLE0
+ D16(TIMER_DISABLE0);
+ D16(TIMER_ENABLE0);
+ D32(TIMER_STATUS0);
+#endif
+#ifdef TIMER_DISABLE1
+ D16(TIMER_DISABLE1);
+ D16(TIMER_ENABLE1);
+ D32(TIMER_STATUS1);
+#endif
+ /* XXX: Should convert BF561 MMR names */
+#ifdef TMRS4_DISABLE
+ D16(TMRS4_DISABLE);
+ D16(TMRS4_ENABLE);
+ D32(TMRS4_STATUS);
+ D16(TMRS8_DISABLE);
+ D16(TMRS8_ENABLE);
+ D32(TMRS8_STATUS);
+#endif
+ GPTIMER(0);
+ GPTIMER(1);
+ GPTIMER(2);
+#ifdef TIMER3_CONFIG
+ GPTIMER(3);
+ GPTIMER(4);
+ GPTIMER(5);
+ GPTIMER(6);
+ GPTIMER(7);
+#endif
+#ifdef TIMER8_CONFIG
+ GPTIMER(8);
+ GPTIMER(9);
+ GPTIMER(10);
+#endif
+#ifdef TIMER11_CONFIG
+ GPTIMER(11);
+#endif
+
+#ifdef HMDMA0_CONTROL
+ parent = debugfs_create_dir("hmdma", top);
+ HMDMA(0);
+ HMDMA(1);
+#endif
+
+#ifdef HOST_CONTROL
+ parent = debugfs_create_dir("hostdp", top);
+ D16(HOST_CONTROL);
+ D16(HOST_STATUS);
+ D16(HOST_TIMEOUT);
+#endif
+
+#ifdef IMDMA_S0_CONFIG
+ parent = debugfs_create_dir("imdma", top);
+ IMDMA(0);
+ IMDMA(1);
+#endif
+
+#ifdef KPAD_CTL
+ parent = debugfs_create_dir("keypad", top);
+ D16(KPAD_CTL);
+ D16(KPAD_PRESCALE);
+ D16(KPAD_MSEL);
+ D16(KPAD_ROWCOL);
+ D16(KPAD_STAT);
+ D16(KPAD_SOFTEVAL);
+#endif
+
+ parent = debugfs_create_dir("mdma", top);
+ MDMA(0);
+ MDMA(1);
+#ifdef MDMA_D2_CONFIG
+ MDMA(2);
+ MDMA(3);
+#endif
+
+#ifdef MXVR_CONFIG
+ parent = debugfs_create_dir("mxvr", top);
+ D16(MXVR_CONFIG);
+# ifdef MXVR_PLL_CTL_0
+ D32(MXVR_PLL_CTL_0);
+# endif
+ D32(MXVR_STATE_0);
+ D32(MXVR_STATE_1);
+ D32(MXVR_INT_STAT_0);
+ D32(MXVR_INT_STAT_1);
+ D32(MXVR_INT_EN_0);
+ D32(MXVR_INT_EN_1);
+ D16(MXVR_POSITION);
+ D16(MXVR_MAX_POSITION);
+ D16(MXVR_DELAY);
+ D16(MXVR_MAX_DELAY);
+ D32(MXVR_LADDR);
+ D16(MXVR_GADDR);
+ D32(MXVR_AADDR);
+ D32(MXVR_ALLOC_0);
+ D32(MXVR_ALLOC_1);
+ D32(MXVR_ALLOC_2);
+ D32(MXVR_ALLOC_3);
+ D32(MXVR_ALLOC_4);
+ D32(MXVR_ALLOC_5);
+ D32(MXVR_ALLOC_6);
+ D32(MXVR_ALLOC_7);
+ D32(MXVR_ALLOC_8);
+ D32(MXVR_ALLOC_9);
+ D32(MXVR_ALLOC_10);
+ D32(MXVR_ALLOC_11);
+ D32(MXVR_ALLOC_12);
+ D32(MXVR_ALLOC_13);
+ D32(MXVR_ALLOC_14);
+ D32(MXVR_SYNC_LCHAN_0);
+ D32(MXVR_SYNC_LCHAN_1);
+ D32(MXVR_SYNC_LCHAN_2);
+ D32(MXVR_SYNC_LCHAN_3);
+ D32(MXVR_SYNC_LCHAN_4);
+ D32(MXVR_SYNC_LCHAN_5);
+ D32(MXVR_SYNC_LCHAN_6);
+ D32(MXVR_SYNC_LCHAN_7);
+ D32(MXVR_DMA0_CONFIG);
+ D32(MXVR_DMA0_START_ADDR);
+ D16(MXVR_DMA0_COUNT);
+ D32(MXVR_DMA0_CURR_ADDR);
+ D16(MXVR_DMA0_CURR_COUNT);
+ D32(MXVR_DMA1_CONFIG);
+ D32(MXVR_DMA1_START_ADDR);
+ D16(MXVR_DMA1_COUNT);
+ D32(MXVR_DMA1_CURR_ADDR);
+ D16(MXVR_DMA1_CURR_COUNT);
+ D32(MXVR_DMA2_CONFIG);
+ D32(MXVR_DMA2_START_ADDR);
+ D16(MXVR_DMA2_COUNT);
+ D32(MXVR_DMA2_CURR_ADDR);
+ D16(MXVR_DMA2_CURR_COUNT);
+ D32(MXVR_DMA3_CONFIG);
+ D32(MXVR_DMA3_START_ADDR);
+ D16(MXVR_DMA3_COUNT);
+ D32(MXVR_DMA3_CURR_ADDR);
+ D16(MXVR_DMA3_CURR_COUNT);
+ D32(MXVR_DMA4_CONFIG);
+ D32(MXVR_DMA4_START_ADDR);
+ D16(MXVR_DMA4_COUNT);
+ D32(MXVR_DMA4_CURR_ADDR);
+ D16(MXVR_DMA4_CURR_COUNT);
+ D32(MXVR_DMA5_CONFIG);
+ D32(MXVR_DMA5_START_ADDR);
+ D16(MXVR_DMA5_COUNT);
+ D32(MXVR_DMA5_CURR_ADDR);
+ D16(MXVR_DMA5_CURR_COUNT);
+ D32(MXVR_DMA6_CONFIG);
+ D32(MXVR_DMA6_START_ADDR);
+ D16(MXVR_DMA6_COUNT);
+ D32(MXVR_DMA6_CURR_ADDR);
+ D16(MXVR_DMA6_CURR_COUNT);
+ D32(MXVR_DMA7_CONFIG);
+ D32(MXVR_DMA7_START_ADDR);
+ D16(MXVR_DMA7_COUNT);
+ D32(MXVR_DMA7_CURR_ADDR);
+ D16(MXVR_DMA7_CURR_COUNT);
+ D16(MXVR_AP_CTL);
+ D32(MXVR_APRB_START_ADDR);
+ D32(MXVR_APRB_CURR_ADDR);
+ D32(MXVR_APTB_START_ADDR);
+ D32(MXVR_APTB_CURR_ADDR);
+ D32(MXVR_CM_CTL);
+ D32(MXVR_CMRB_START_ADDR);
+ D32(MXVR_CMRB_CURR_ADDR);
+ D32(MXVR_CMTB_START_ADDR);
+ D32(MXVR_CMTB_CURR_ADDR);
+ D32(MXVR_RRDB_START_ADDR);
+ D32(MXVR_RRDB_CURR_ADDR);
+ D32(MXVR_PAT_DATA_0);
+ D32(MXVR_PAT_EN_0);
+ D32(MXVR_PAT_DATA_1);
+ D32(MXVR_PAT_EN_1);
+ D16(MXVR_FRAME_CNT_0);
+ D16(MXVR_FRAME_CNT_1);
+ D32(MXVR_ROUTING_0);
+ D32(MXVR_ROUTING_1);
+ D32(MXVR_ROUTING_2);
+ D32(MXVR_ROUTING_3);
+ D32(MXVR_ROUTING_4);
+ D32(MXVR_ROUTING_5);
+ D32(MXVR_ROUTING_6);
+ D32(MXVR_ROUTING_7);
+ D32(MXVR_ROUTING_8);
+ D32(MXVR_ROUTING_9);
+ D32(MXVR_ROUTING_10);
+ D32(MXVR_ROUTING_11);
+ D32(MXVR_ROUTING_12);
+ D32(MXVR_ROUTING_13);
+ D32(MXVR_ROUTING_14);
+# ifdef MXVR_PLL_CTL_1
+ D32(MXVR_PLL_CTL_1);
+# endif
+ D16(MXVR_BLOCK_CNT);
+# ifdef MXVR_CLK_CTL
+ D32(MXVR_CLK_CTL);
+# endif
+# ifdef MXVR_CDRPLL_CTL
+ D32(MXVR_CDRPLL_CTL);
+# endif
+# ifdef MXVR_FMPLL_CTL
+ D32(MXVR_FMPLL_CTL);
+# endif
+# ifdef MXVR_PIN_CTL
+ D16(MXVR_PIN_CTL);
+# endif
+# ifdef MXVR_SCLK_CNT
+ D16(MXVR_SCLK_CNT);
+# endif
+#endif
+
+#ifdef NFC_ADDR
+ parent = debugfs_create_dir("nfc", top);
+ D_WO(NFC_ADDR, 16);
+ D_WO(NFC_CMD, 16);
+ D_RO(NFC_COUNT, 16);
+ D16(NFC_CTL);
+ D_WO(NFC_DATA_RD, 16);
+ D_WO(NFC_DATA_WR, 16);
+ D_RO(NFC_ECC0, 16);
+ D_RO(NFC_ECC1, 16);
+ D_RO(NFC_ECC2, 16);
+ D_RO(NFC_ECC3, 16);
+ D16(NFC_IRQMASK);
+ D16(NFC_IRQSTAT);
+ D_WO(NFC_PGCTL, 16);
+ D_RO(NFC_READ, 16);
+ D16(NFC_RST);
+ D_RO(NFC_STAT, 16);
+#endif
+
+#ifdef OTP_CONTROL
+ parent = debugfs_create_dir("otp", top);
+ D16(OTP_CONTROL);
+ D16(OTP_BEN);
+ D16(OTP_STATUS);
+ D32(OTP_TIMING);
+ D32(OTP_DATA0);
+ D32(OTP_DATA1);
+ D32(OTP_DATA2);
+ D32(OTP_DATA3);
+#endif
+
+#ifdef PIXC_CTL
+ parent = debugfs_create_dir("pixc", top);
+ D16(PIXC_CTL);
+ D16(PIXC_PPL);
+ D16(PIXC_LPF);
+ D16(PIXC_AHSTART);
+ D16(PIXC_AHEND);
+ D16(PIXC_AVSTART);
+ D16(PIXC_AVEND);
+ D16(PIXC_ATRANSP);
+ D16(PIXC_BHSTART);
+ D16(PIXC_BHEND);
+ D16(PIXC_BVSTART);
+ D16(PIXC_BVEND);
+ D16(PIXC_BTRANSP);
+ D16(PIXC_INTRSTAT);
+ D32(PIXC_RYCON);
+ D32(PIXC_GUCON);
+ D32(PIXC_BVCON);
+ D32(PIXC_CCBIAS);
+ D32(PIXC_TC);
+#endif
+
+ parent = debugfs_create_dir("pll", top);
+ D16(PLL_CTL);
+ D16(PLL_DIV);
+ D16(PLL_LOCKCNT);
+ D16(PLL_STAT);
+ D16(VR_CTL);
+ D32(CHIPID); /* it's part of this hardware block */
+
+#if defined(PPI_STATUS) || defined(PPI0_STATUS) || defined(PPI1_STATUS)
+ parent = debugfs_create_dir("ppi", top);
+# ifdef PPI_STATUS
+ bfin_debug_mmrs_ppi(parent, PPI_STATUS, -1);
+# endif
+# ifdef PPI0_STATUS
+ PPI(0);
+# endif
+# ifdef PPI1_STATUS
+ PPI(1);
+# endif
+#endif
+
+#ifdef PWM_CTRL
+ parent = debugfs_create_dir("pwm", top);
+ D16(PWM_CTRL);
+ D16(PWM_STAT);
+ D16(PWM_TM);
+ D16(PWM_DT);
+ D16(PWM_GATE);
+ D16(PWM_CHA);
+ D16(PWM_CHB);
+ D16(PWM_CHC);
+ D16(PWM_SEG);
+ D16(PWM_SYNCWT);
+ D16(PWM_CHAL);
+ D16(PWM_CHBL);
+ D16(PWM_CHCL);
+ D16(PWM_LSI);
+ D16(PWM_STAT2);
+#endif
+
+#ifdef RSI_CONFIG
+ parent = debugfs_create_dir("rsi", top);
+ D32(RSI_ARGUMENT);
+ D16(RSI_CEATA_CONTROL);
+ D16(RSI_CLK_CONTROL);
+ D16(RSI_COMMAND);
+ D16(RSI_CONFIG);
+ D16(RSI_DATA_CNT);
+ D16(RSI_DATA_CONTROL);
+ D16(RSI_DATA_LGTH);
+ D32(RSI_DATA_TIMER);
+ D16(RSI_EMASK);
+ D16(RSI_ESTAT);
+ D32(RSI_FIFO);
+ D16(RSI_FIFO_CNT);
+ D32(RSI_MASK0);
+ D32(RSI_MASK1);
+ D16(RSI_PID0);
+ D16(RSI_PID1);
+ D16(RSI_PID2);
+ D16(RSI_PID3);
+ D16(RSI_PWR_CONTROL);
+ D16(RSI_RD_WAIT_EN);
+ D32(RSI_RESPONSE0);
+ D32(RSI_RESPONSE1);
+ D32(RSI_RESPONSE2);
+ D32(RSI_RESPONSE3);
+ D16(RSI_RESP_CMD);
+ D32(RSI_STATUS);
+ D_WO(RSI_STATUSCL, 16);
+#endif
+
+#ifdef RTC_ALARM
+ parent = debugfs_create_dir("rtc", top);
+ D32(RTC_ALARM);
+ D16(RTC_ICTL);
+ D16(RTC_ISTAT);
+ D16(RTC_PREN);
+ D32(RTC_STAT);
+ D16(RTC_SWCNT);
+#endif
+
+#ifdef SDH_CFG
+ parent = debugfs_create_dir("sdh", top);
+ D32(SDH_ARGUMENT);
+ D16(SDH_CFG);
+ D16(SDH_CLK_CTL);
+ D16(SDH_COMMAND);
+ D_RO(SDH_DATA_CNT, 16);
+ D16(SDH_DATA_CTL);
+ D16(SDH_DATA_LGTH);
+ D32(SDH_DATA_TIMER);
+ D16(SDH_E_MASK);
+ D16(SDH_E_STATUS);
+ D32(SDH_FIFO);
+ D_RO(SDH_FIFO_CNT, 16);
+ D32(SDH_MASK0);
+ D32(SDH_MASK1);
+ D_RO(SDH_PID0, 16);
+ D_RO(SDH_PID1, 16);
+ D_RO(SDH_PID2, 16);
+ D_RO(SDH_PID3, 16);
+ D_RO(SDH_PID4, 16);
+ D_RO(SDH_PID5, 16);
+ D_RO(SDH_PID6, 16);
+ D_RO(SDH_PID7, 16);
+ D16(SDH_PWR_CTL);
+ D16(SDH_RD_WAIT_EN);
+ D_RO(SDH_RESPONSE0, 32);
+ D_RO(SDH_RESPONSE1, 32);
+ D_RO(SDH_RESPONSE2, 32);
+ D_RO(SDH_RESPONSE3, 32);
+ D_RO(SDH_RESP_CMD, 16);
+ D_RO(SDH_STATUS, 32);
+ D_WO(SDH_STATUS_CLR, 16);
+#endif
+
+#ifdef SECURE_CONTROL
+ parent = debugfs_create_dir("security", top);
+ D16(SECURE_CONTROL);
+ D16(SECURE_STATUS);
+ D32(SECURE_SYSSWT);
+#endif
+
+ parent = debugfs_create_dir("sic", top);
+ D16(SWRST);
+ D16(SYSCR);
+ D16(SIC_RVECT);
+ D32(SIC_IAR0);
+ D32(SIC_IAR1);
+ D32(SIC_IAR2);
+#ifdef SIC_IAR3
+ D32(SIC_IAR3);
+#endif
+#ifdef SIC_IAR4
+ D32(SIC_IAR4);
+ D32(SIC_IAR5);
+ D32(SIC_IAR6);
+#endif
+#ifdef SIC_IAR7
+ D32(SIC_IAR7);
+#endif
+#ifdef SIC_IAR8
+ D32(SIC_IAR8);
+ D32(SIC_IAR9);
+ D32(SIC_IAR10);
+ D32(SIC_IAR11);
+#endif
+#ifdef SIC_IMASK
+ D32(SIC_IMASK);
+ D32(SIC_ISR);
+ D32(SIC_IWR);
+#endif
+#ifdef SIC_IMASK0
+ D32(SIC_IMASK0);
+ D32(SIC_IMASK1);
+ D32(SIC_ISR0);
+ D32(SIC_ISR1);
+ D32(SIC_IWR0);
+ D32(SIC_IWR1);
+#endif
+#ifdef SIC_IMASK2
+ D32(SIC_IMASK2);
+ D32(SIC_ISR2);
+ D32(SIC_IWR2);
+#endif
+#ifdef SICB_RVECT
+ D16(SICB_SWRST);
+ D16(SICB_SYSCR);
+ D16(SICB_RVECT);
+ D32(SICB_IAR0);
+ D32(SICB_IAR1);
+ D32(SICB_IAR2);
+ D32(SICB_IAR3);
+ D32(SICB_IAR4);
+ D32(SICB_IAR5);
+ D32(SICB_IAR6);
+ D32(SICB_IAR7);
+ D32(SICB_IMASK0);
+ D32(SICB_IMASK1);
+ D32(SICB_ISR0);
+ D32(SICB_ISR1);
+ D32(SICB_IWR0);
+ D32(SICB_IWR1);
+#endif
+
+ parent = debugfs_create_dir("spi", top);
+#ifdef SPI0_REGBASE
+ SPI(0);
+#endif
+#ifdef SPI1_REGBASE
+ SPI(1);
+#endif
+#ifdef SPI2_REGBASE
+ SPI(2);
+#endif
+
+ parent = debugfs_create_dir("sport", top);
+#ifdef SPORT0_STAT
+ SPORT(0);
+#endif
+#ifdef SPORT1_STAT
+ SPORT(1);
+#endif
+#ifdef SPORT2_STAT
+ SPORT(2);
+#endif
+#ifdef SPORT3_STAT
+ SPORT(3);
+#endif
+
+#if defined(TWI_CLKDIV) || defined(TWI0_CLKDIV) || defined(TWI1_CLKDIV)
+ parent = debugfs_create_dir("twi", top);
+# ifdef TWI_CLKDIV
+ bfin_debug_mmrs_twi(parent, TWI_CLKDIV, -1);
+# endif
+# ifdef TWI0_CLKDIV
+ TWI(0);
+# endif
+# ifdef TWI1_CLKDIV
+ TWI(1);
+# endif
+#endif
+
+ parent = debugfs_create_dir("uart", top);
+#ifdef BFIN_UART_DLL
+ bfin_debug_mmrs_uart(parent, BFIN_UART_DLL, -1);
+#endif
+#ifdef UART0_DLL
+ UART(0);
+#endif
+#ifdef UART1_DLL
+ UART(1);
+#endif
+#ifdef UART2_DLL
+ UART(2);
+#endif
+#ifdef UART3_DLL
+ UART(3);
+#endif
+
+#ifdef USB_FADDR
+ parent = debugfs_create_dir("usb", top);
+ D16(USB_FADDR);
+ D16(USB_POWER);
+ D16(USB_INTRTX);
+ D16(USB_INTRRX);
+ D16(USB_INTRTXE);
+ D16(USB_INTRRXE);
+ D16(USB_INTRUSB);
+ D16(USB_INTRUSBE);
+ D16(USB_FRAME);
+ D16(USB_INDEX);
+ D16(USB_TESTMODE);
+ D16(USB_GLOBINTR);
+ D16(USB_GLOBAL_CTL);
+ D16(USB_TX_MAX_PACKET);
+ D16(USB_CSR0);
+ D16(USB_TXCSR);
+ D16(USB_RX_MAX_PACKET);
+ D16(USB_RXCSR);
+ D16(USB_COUNT0);
+ D16(USB_RXCOUNT);
+ D16(USB_TXTYPE);
+ D16(USB_NAKLIMIT0);
+ D16(USB_TXINTERVAL);
+ D16(USB_RXTYPE);
+ D16(USB_RXINTERVAL);
+ D16(USB_TXCOUNT);
+ D16(USB_EP0_FIFO);
+ D16(USB_EP1_FIFO);
+ D16(USB_EP2_FIFO);
+ D16(USB_EP3_FIFO);
+ D16(USB_EP4_FIFO);
+ D16(USB_EP5_FIFO);
+ D16(USB_EP6_FIFO);
+ D16(USB_EP7_FIFO);
+ D16(USB_OTG_DEV_CTL);
+ D16(USB_OTG_VBUS_IRQ);
+ D16(USB_OTG_VBUS_MASK);
+ D16(USB_LINKINFO);
+ D16(USB_VPLEN);
+ D16(USB_HS_EOF1);
+ D16(USB_FS_EOF1);
+ D16(USB_LS_EOF1);
+ D16(USB_APHY_CNTRL);
+ D16(USB_APHY_CALIB);
+ D16(USB_APHY_CNTRL2);
+ D16(USB_PHY_TEST);
+ D16(USB_PLLOSC_CTRL);
+ D16(USB_SRP_CLKDIV);
+ D16(USB_EP_NI0_TXMAXP);
+ D16(USB_EP_NI0_TXCSR);
+ D16(USB_EP_NI0_RXMAXP);
+ D16(USB_EP_NI0_RXCSR);
+ D16(USB_EP_NI0_RXCOUNT);
+ D16(USB_EP_NI0_TXTYPE);
+ D16(USB_EP_NI0_TXINTERVAL);
+ D16(USB_EP_NI0_RXTYPE);
+ D16(USB_EP_NI0_RXINTERVAL);
+ D16(USB_EP_NI0_TXCOUNT);
+ D16(USB_EP_NI1_TXMAXP);
+ D16(USB_EP_NI1_TXCSR);
+ D16(USB_EP_NI1_RXMAXP);
+ D16(USB_EP_NI1_RXCSR);
+ D16(USB_EP_NI1_RXCOUNT);
+ D16(USB_EP_NI1_TXTYPE);
+ D16(USB_EP_NI1_TXINTERVAL);
+ D16(USB_EP_NI1_RXTYPE);
+ D16(USB_EP_NI1_RXINTERVAL);
+ D16(USB_EP_NI1_TXCOUNT);
+ D16(USB_EP_NI2_TXMAXP);
+ D16(USB_EP_NI2_TXCSR);
+ D16(USB_EP_NI2_RXMAXP);
+ D16(USB_EP_NI2_RXCSR);
+ D16(USB_EP_NI2_RXCOUNT);
+ D16(USB_EP_NI2_TXTYPE);
+ D16(USB_EP_NI2_TXINTERVAL);
+ D16(USB_EP_NI2_RXTYPE);
+ D16(USB_EP_NI2_RXINTERVAL);
+ D16(USB_EP_NI2_TXCOUNT);
+ D16(USB_EP_NI3_TXMAXP);
+ D16(USB_EP_NI3_TXCSR);
+ D16(USB_EP_NI3_RXMAXP);
+ D16(USB_EP_NI3_RXCSR);
+ D16(USB_EP_NI3_RXCOUNT);
+ D16(USB_EP_NI3_TXTYPE);
+ D16(USB_EP_NI3_TXINTERVAL);
+ D16(USB_EP_NI3_RXTYPE);
+ D16(USB_EP_NI3_RXINTERVAL);
+ D16(USB_EP_NI3_TXCOUNT);
+ D16(USB_EP_NI4_TXMAXP);
+ D16(USB_EP_NI4_TXCSR);
+ D16(USB_EP_NI4_RXMAXP);
+ D16(USB_EP_NI4_RXCSR);
+ D16(USB_EP_NI4_RXCOUNT);
+ D16(USB_EP_NI4_TXTYPE);
+ D16(USB_EP_NI4_TXINTERVAL);
+ D16(USB_EP_NI4_RXTYPE);
+ D16(USB_EP_NI4_RXINTERVAL);
+ D16(USB_EP_NI4_TXCOUNT);
+ D16(USB_EP_NI5_TXMAXP);
+ D16(USB_EP_NI5_TXCSR);
+ D16(USB_EP_NI5_RXMAXP);
+ D16(USB_EP_NI5_RXCSR);
+ D16(USB_EP_NI5_RXCOUNT);
+ D16(USB_EP_NI5_TXTYPE);
+ D16(USB_EP_NI5_TXINTERVAL);
+ D16(USB_EP_NI5_RXTYPE);
+ D16(USB_EP_NI5_RXINTERVAL);
+ D16(USB_EP_NI5_TXCOUNT);
+ D16(USB_EP_NI6_TXMAXP);
+ D16(USB_EP_NI6_TXCSR);
+ D16(USB_EP_NI6_RXMAXP);
+ D16(USB_EP_NI6_RXCSR);
+ D16(USB_EP_NI6_RXCOUNT);
+ D16(USB_EP_NI6_TXTYPE);
+ D16(USB_EP_NI6_TXINTERVAL);
+ D16(USB_EP_NI6_RXTYPE);
+ D16(USB_EP_NI6_RXINTERVAL);
+ D16(USB_EP_NI6_TXCOUNT);
+ D16(USB_EP_NI7_TXMAXP);
+ D16(USB_EP_NI7_TXCSR);
+ D16(USB_EP_NI7_RXMAXP);
+ D16(USB_EP_NI7_RXCSR);
+ D16(USB_EP_NI7_RXCOUNT);
+ D16(USB_EP_NI7_TXTYPE);
+ D16(USB_EP_NI7_TXINTERVAL);
+ D16(USB_EP_NI7_RXTYPE);
+ D16(USB_EP_NI7_RXINTERVAL);
+ D16(USB_EP_NI7_TXCOUNT);
+ D16(USB_DMA_INTERRUPT);
+ D16(USB_DMA0CONTROL);
+ D16(USB_DMA0ADDRLOW);
+ D16(USB_DMA0ADDRHIGH);
+ D16(USB_DMA0COUNTLOW);
+ D16(USB_DMA0COUNTHIGH);
+ D16(USB_DMA1CONTROL);
+ D16(USB_DMA1ADDRLOW);
+ D16(USB_DMA1ADDRHIGH);
+ D16(USB_DMA1COUNTLOW);
+ D16(USB_DMA1COUNTHIGH);
+ D16(USB_DMA2CONTROL);
+ D16(USB_DMA2ADDRLOW);
+ D16(USB_DMA2ADDRHIGH);
+ D16(USB_DMA2COUNTLOW);
+ D16(USB_DMA2COUNTHIGH);
+ D16(USB_DMA3CONTROL);
+ D16(USB_DMA3ADDRLOW);
+ D16(USB_DMA3ADDRHIGH);
+ D16(USB_DMA3COUNTLOW);
+ D16(USB_DMA3COUNTHIGH);
+ D16(USB_DMA4CONTROL);
+ D16(USB_DMA4ADDRLOW);
+ D16(USB_DMA4ADDRHIGH);
+ D16(USB_DMA4COUNTLOW);
+ D16(USB_DMA4COUNTHIGH);
+ D16(USB_DMA5CONTROL);
+ D16(USB_DMA5ADDRLOW);
+ D16(USB_DMA5ADDRHIGH);
+ D16(USB_DMA5COUNTLOW);
+ D16(USB_DMA5COUNTHIGH);
+ D16(USB_DMA6CONTROL);
+ D16(USB_DMA6ADDRLOW);
+ D16(USB_DMA6ADDRHIGH);
+ D16(USB_DMA6COUNTLOW);
+ D16(USB_DMA6COUNTHIGH);
+ D16(USB_DMA7CONTROL);
+ D16(USB_DMA7ADDRLOW);
+ D16(USB_DMA7ADDRHIGH);
+ D16(USB_DMA7COUNTLOW);
+ D16(USB_DMA7COUNTHIGH);
+#endif
+
+#ifdef WDOG_CNT
+ parent = debugfs_create_dir("watchdog", top);
+ D32(WDOG_CNT);
+ D16(WDOG_CTL);
+ D32(WDOG_STAT);
+#endif
+#ifdef WDOGA_CNT
+ parent = debugfs_create_dir("watchdog", top);
+ D32(WDOGA_CNT);
+ D16(WDOGA_CTL);
+ D32(WDOGA_STAT);
+ D32(WDOGB_CNT);
+ D16(WDOGB_CTL);
+ D32(WDOGB_STAT);
+#endif
+
+ /* BF533 glue */
+#ifdef FIO_FLAG_D
+#define PORTFIO FIO_FLAG_D
+#endif
+ /* BF561 glue */
+#ifdef FIO0_FLAG_D
+#define PORTFIO FIO0_FLAG_D
+#endif
+#ifdef FIO1_FLAG_D
+#define PORTGIO FIO1_FLAG_D
+#endif
+#ifdef FIO2_FLAG_D
+#define PORTHIO FIO2_FLAG_D
+#endif
+ parent = debugfs_create_dir("port", top);
+#ifdef PORTFIO
+ PORT(PORTFIO, 'F');
+#endif
+#ifdef PORTGIO
+ PORT(PORTGIO, 'G');
+#endif
+#ifdef PORTHIO
+ PORT(PORTHIO, 'H');
+#endif
+
+#ifdef __ADSPBF51x__
+ D16(PORTF_FER);
+ D16(PORTF_DRIVE);
+ D16(PORTF_HYSTERESIS);
+ D16(PORTF_MUX);
+
+ D16(PORTG_FER);
+ D16(PORTG_DRIVE);
+ D16(PORTG_HYSTERESIS);
+ D16(PORTG_MUX);
+
+ D16(PORTH_FER);
+ D16(PORTH_DRIVE);
+ D16(PORTH_HYSTERESIS);
+ D16(PORTH_MUX);
+
+ D16(MISCPORT_DRIVE);
+ D16(MISCPORT_HYSTERESIS);
+#endif /* BF51x */
+
+#ifdef __ADSPBF52x__
+ D16(PORTF_FER);
+ D16(PORTF_DRIVE);
+ D16(PORTF_HYSTERESIS);
+ D16(PORTF_MUX);
+ D16(PORTF_SLEW);
+
+ D16(PORTG_FER);
+ D16(PORTG_DRIVE);
+ D16(PORTG_HYSTERESIS);
+ D16(PORTG_MUX);
+ D16(PORTG_SLEW);
+
+ D16(PORTH_FER);
+ D16(PORTH_DRIVE);
+ D16(PORTH_HYSTERESIS);
+ D16(PORTH_MUX);
+ D16(PORTH_SLEW);
+
+ D16(MISCPORT_DRIVE);
+ D16(MISCPORT_HYSTERESIS);
+ D16(MISCPORT_SLEW);
+#endif /* BF52x */
+
+#ifdef BF537_FAMILY
+ D16(PORTF_FER);
+ D16(PORTG_FER);
+ D16(PORTH_FER);
+ D16(PORT_MUX);
+#endif /* BF534 BF536 BF537 */
+
+#ifdef BF538_FAMILY
+ D16(PORTCIO_FER);
+ D16(PORTCIO);
+ D16(PORTCIO_CLEAR);
+ D16(PORTCIO_SET);
+ D16(PORTCIO_TOGGLE);
+ D16(PORTCIO_DIR);
+ D16(PORTCIO_INEN);
+
+ D16(PORTDIO);
+ D16(PORTDIO_CLEAR);
+ D16(PORTDIO_DIR);
+ D16(PORTDIO_FER);
+ D16(PORTDIO_INEN);
+ D16(PORTDIO_SET);
+ D16(PORTDIO_TOGGLE);
+
+ D16(PORTEIO);
+ D16(PORTEIO_CLEAR);
+ D16(PORTEIO_DIR);
+ D16(PORTEIO_FER);
+ D16(PORTEIO_INEN);
+ D16(PORTEIO_SET);
+ D16(PORTEIO_TOGGLE);
+#endif /* BF538 BF539 */
+
+#ifdef __ADSPBF54x__
+ {
+ int num;
+ unsigned long base;
+ char *_buf, buf[32];
+
+ base = PORTA_FER;
+ for (num = 0; num < 10; ++num) {
+ PORT(base, num);
+ base += sizeof(struct bfin_gpio_regs);
+ }
+
+#define __PINT(uname, lname) __REGS(pint, #uname, lname)
+ parent = debugfs_create_dir("pint", top);
+ base = PINT0_MASK_SET;
+ for (num = 0; num < 4; ++num) {
+ _buf = REGS_STR_PFX(buf, PINT, num);
+ __PINT(MASK_SET, mask_set);
+ __PINT(MASK_CLEAR, mask_clear);
+ __PINT(IRQ, irq);
+ __PINT(ASSIGN, assign);
+ __PINT(EDGE_SET, edge_set);
+ __PINT(EDGE_CLEAR, edge_clear);
+ __PINT(INVERT_SET, invert_set);
+ __PINT(INVERT_CLEAR, invert_clear);
+ __PINT(PINSTATE, pinstate);
+ __PINT(LATCH, latch);
+ base += sizeof(struct bfin_pint_regs);
+ }
+
+ }
+#endif /* BF54x */
+
+ debug_mmrs_dentry = top;
+
+ return 0;
+}
+module_init(bfin_debug_mmrs_init);
+
+static void __exit bfin_debug_mmrs_exit(void)
+{
+ debugfs_remove_recursive(debug_mmrs_dentry);
+}
+module_exit(bfin_debug_mmrs_exit);
+
+MODULE_LICENSE("GPL");
#include <linux/io.h>
#include <asm/system.h>
#include <asm/atomic.h>
+#include <asm/irq_handler.h>
DEFINE_PER_CPU(struct pt_regs, __ipipe_tick_regs);
#include <linux/kallsyms.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
+#include <asm/irq_handler.h>
#include <asm/trace.h>
#include <asm/pda.h>
{
unsigned int this_cpu = smp_processor_id();
unsigned int cpu;
+ cpumask_t mask;
- cpumask_t mask = cpu_online_map;
-
+ cpumask_copy(&mask, cpu_online_mask);
if (!atomic_read(&nmi_touched[this_cpu]))
return 0;
atomic_set(&nmi_touched[this_cpu], 0);
- cpu_clear(this_cpu, mask);
- for_each_cpu_mask(cpu, mask) {
+ cpumask_clear_cpu(this_cpu, &mask);
+ for_each_cpu(cpu, &mask) {
invalidate_dcache_range((unsigned long)(&nmi_touched[cpu]),
(unsigned long)(&nmi_touched[cpu]));
if (!atomic_read(&nmi_touched[cpu]))
--- /dev/null
+/*
+ * Blackfin performance counters
+ *
+ * Copyright 2011 Analog Devices Inc.
+ *
+ * Ripped from SuperH version:
+ *
+ * Copyright (C) 2009 Paul Mundt
+ *
+ * Heavily based on the x86 and PowerPC implementations.
+ *
+ * x86:
+ * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
+ * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
+ * Copyright (C) 2009 Jaswinder Singh Rajput
+ * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
+ * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
+ * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
+ *
+ * ppc:
+ * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/perf_event.h>
+#include <asm/bfin_pfmon.h>
+
+/*
+ * We have two counters, and each counter can support an event type.
+ * The 'o' is PFCNTx=1 and 's' is PFCNTx=0
+ *
+ * 0x04 o pc invariant branches
+ * 0x06 o mispredicted branches
+ * 0x09 o predicted branches taken
+ * 0x0B o EXCPT insn
+ * 0x0C o CSYNC/SSYNC insn
+ * 0x0D o Insns committed
+ * 0x0E o Interrupts taken
+ * 0x0F o Misaligned address exceptions
+ * 0x80 o Code memory fetches stalled due to DMA
+ * 0x83 o 64bit insn fetches delivered
+ * 0x9A o data cache fills (bank a)
+ * 0x9B o data cache fills (bank b)
+ * 0x9C o data cache lines evicted (bank a)
+ * 0x9D o data cache lines evicted (bank b)
+ * 0x9E o data cache high priority fills
+ * 0x9F o data cache low priority fills
+ * 0x00 s loop 0 iterations
+ * 0x01 s loop 1 iterations
+ * 0x0A s CSYNC/SSYNC stalls
+ * 0x10 s DAG read/after write hazards
+ * 0x13 s RAW data hazards
+ * 0x81 s code TAG stalls
+ * 0x82 s code fill stalls
+ * 0x90 s processor to memory stalls
+ * 0x91 s data memory stalls not hidden by 0x90
+ * 0x92 s data store buffer full stalls
+ * 0x93 s data memory write buffer full stalls due to high->low priority
+ * 0x95 s data memory fill buffer stalls
+ * 0x96 s data TAG collision stalls
+ * 0x97 s data collision stalls
+ * 0x98 s data stalls
+ * 0x99 s data stalls sent to processor
+ */
+
+static const int event_map[] = {
+ /* use CYCLES cpu register */
+ [PERF_COUNT_HW_CPU_CYCLES] = -1,
+ [PERF_COUNT_HW_INSTRUCTIONS] = 0x0D,
+ [PERF_COUNT_HW_CACHE_REFERENCES] = -1,
+ [PERF_COUNT_HW_CACHE_MISSES] = 0x83,
+ [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x09,
+ [PERF_COUNT_HW_BRANCH_MISSES] = 0x06,
+ [PERF_COUNT_HW_BUS_CYCLES] = -1,
+};
+
+#define C(x) PERF_COUNT_HW_CACHE_##x
+
+static const int cache_events[PERF_COUNT_HW_CACHE_MAX]
+ [PERF_COUNT_HW_CACHE_OP_MAX]
+ [PERF_COUNT_HW_CACHE_RESULT_MAX] =
+{
+ [C(L1D)] = { /* Data bank A */
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = 0,
+ [C(RESULT_MISS) ] = 0x9A,
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = 0,
+ [C(RESULT_MISS) ] = 0,
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = 0,
+ [C(RESULT_MISS) ] = 0,
+ },
+ },
+
+ [C(L1I)] = {
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = 0,
+ [C(RESULT_MISS) ] = 0x83,
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = -1,
+ [C(RESULT_MISS) ] = -1,
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = 0,
+ [C(RESULT_MISS) ] = 0,
+ },
+ },
+
+ [C(LL)] = {
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = -1,
+ [C(RESULT_MISS) ] = -1,
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = -1,
+ [C(RESULT_MISS) ] = -1,
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = -1,
+ [C(RESULT_MISS) ] = -1,
+ },
+ },
+
+ [C(DTLB)] = {
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = -1,
+ [C(RESULT_MISS) ] = -1,
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = -1,
+ [C(RESULT_MISS) ] = -1,
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = -1,
+ [C(RESULT_MISS) ] = -1,
+ },
+ },
+
+ [C(ITLB)] = {
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = -1,
+ [C(RESULT_MISS) ] = -1,
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = -1,
+ [C(RESULT_MISS) ] = -1,
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = -1,
+ [C(RESULT_MISS) ] = -1,
+ },
+ },
+
+ [C(BPU)] = {
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = -1,
+ [C(RESULT_MISS) ] = -1,
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = -1,
+ [C(RESULT_MISS) ] = -1,
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = -1,
+ [C(RESULT_MISS) ] = -1,
+ },
+ },
+};
+
+const char *perf_pmu_name(void)
+{
+ return "bfin";
+}
+EXPORT_SYMBOL(perf_pmu_name);
+
+int perf_num_counters(void)
+{
+ return ARRAY_SIZE(event_map);
+}
+EXPORT_SYMBOL(perf_num_counters);
+
+static u64 bfin_pfmon_read(int idx)
+{
+ return bfin_read32(PFCNTR0 + (idx * 4));
+}
+
+static void bfin_pfmon_disable(struct hw_perf_event *hwc, int idx)
+{
+ bfin_write_PFCTL(bfin_read_PFCTL() & ~PFCEN(idx, PFCEN_MASK));
+}
+
+static void bfin_pfmon_enable(struct hw_perf_event *hwc, int idx)
+{
+ u32 val, mask;
+
+ val = PFPWR;
+ if (idx) {
+ mask = ~(PFCNT1 | PFMON1 | PFCEN1 | PEMUSW1);
+ /* The packed config is for event0, so shift it to event1 slots */
+ val |= (hwc->config << (PFMON1_P - PFMON0_P));
+ val |= (hwc->config & PFCNT0) << (PFCNT1_P - PFCNT0_P);
+ bfin_write_PFCNTR1(0);
+ } else {
+ mask = ~(PFCNT0 | PFMON0 | PFCEN0 | PEMUSW0);
+ val |= hwc->config;
+ bfin_write_PFCNTR0(0);
+ }
+
+ bfin_write_PFCTL((bfin_read_PFCTL() & mask) | val);
+}
+
+static void bfin_pfmon_disable_all(void)
+{
+ bfin_write_PFCTL(bfin_read_PFCTL() & ~PFPWR);
+}
+
+static void bfin_pfmon_enable_all(void)
+{
+ bfin_write_PFCTL(bfin_read_PFCTL() | PFPWR);
+}
+
+struct cpu_hw_events {
+ struct perf_event *events[MAX_HWEVENTS];
+ unsigned long used_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
+};
+DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
+
+static int hw_perf_cache_event(int config, int *evp)
+{
+ unsigned long type, op, result;
+ int ev;
+
+ /* unpack config */
+ type = config & 0xff;
+ op = (config >> 8) & 0xff;
+ result = (config >> 16) & 0xff;
+
+ if (type >= PERF_COUNT_HW_CACHE_MAX ||
+ op >= PERF_COUNT_HW_CACHE_OP_MAX ||
+ result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
+ return -EINVAL;
+
+ ev = cache_events[type][op][result];
+ if (ev == 0)
+ return -EOPNOTSUPP;
+ if (ev == -1)
+ return -EINVAL;
+ *evp = ev;
+ return 0;
+}
+
+static void bfin_perf_event_update(struct perf_event *event,
+ struct hw_perf_event *hwc, int idx)
+{
+ u64 prev_raw_count, new_raw_count;
+ s64 delta;
+ int shift = 0;
+
+ /*
+ * Depending on the counter configuration, they may or may not
+ * be chained, in which case the previous counter value can be
+ * updated underneath us if the lower-half overflows.
+ *
+ * Our tactic to handle this is to first atomically read and
+ * exchange a new raw count - then add that new-prev delta
+ * count to the generic counter atomically.
+ *
+ * As there is no interrupt associated with the overflow events,
+ * this is the simplest approach for maintaining consistency.
+ */
+again:
+ prev_raw_count = local64_read(&hwc->prev_count);
+ new_raw_count = bfin_pfmon_read(idx);
+
+ if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
+ new_raw_count) != prev_raw_count)
+ goto again;
+
+ /*
+ * Now we have the new raw value and have updated the prev
+ * timestamp already. We can now calculate the elapsed delta
+ * (counter-)time and add that to the generic counter.
+ *
+ * Careful, not all hw sign-extends above the physical width
+ * of the count.
+ */
+ delta = (new_raw_count << shift) - (prev_raw_count << shift);
+ delta >>= shift;
+
+ local64_add(delta, &event->count);
+}
+
+static void bfin_pmu_stop(struct perf_event *event, int flags)
+{
+ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+ struct hw_perf_event *hwc = &event->hw;
+ int idx = hwc->idx;
+
+ if (!(event->hw.state & PERF_HES_STOPPED)) {
+ bfin_pfmon_disable(hwc, idx);
+ cpuc->events[idx] = NULL;
+ event->hw.state |= PERF_HES_STOPPED;
+ }
+
+ if ((flags & PERF_EF_UPDATE) && !(event->hw.state & PERF_HES_UPTODATE)) {
+ bfin_perf_event_update(event, &event->hw, idx);
+ event->hw.state |= PERF_HES_UPTODATE;
+ }
+}
+
+static void bfin_pmu_start(struct perf_event *event, int flags)
+{
+ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+ struct hw_perf_event *hwc = &event->hw;
+ int idx = hwc->idx;
+
+ if (WARN_ON_ONCE(idx == -1))
+ return;
+
+ if (flags & PERF_EF_RELOAD)
+ WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
+
+ cpuc->events[idx] = event;
+ event->hw.state = 0;
+ bfin_pfmon_enable(hwc, idx);
+}
+
+static void bfin_pmu_del(struct perf_event *event, int flags)
+{
+ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+
+ bfin_pmu_stop(event, PERF_EF_UPDATE);
+ __clear_bit(event->hw.idx, cpuc->used_mask);
+
+ perf_event_update_userpage(event);
+}
+
+static int bfin_pmu_add(struct perf_event *event, int flags)
+{
+ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+ struct hw_perf_event *hwc = &event->hw;
+ int idx = hwc->idx;
+ int ret = -EAGAIN;
+
+ perf_pmu_disable(event->pmu);
+
+ if (__test_and_set_bit(idx, cpuc->used_mask)) {
+ idx = find_first_zero_bit(cpuc->used_mask, MAX_HWEVENTS);
+ if (idx == MAX_HWEVENTS)
+ goto out;
+
+ __set_bit(idx, cpuc->used_mask);
+ hwc->idx = idx;
+ }
+
+ bfin_pfmon_disable(hwc, idx);
+
+ event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
+ if (flags & PERF_EF_START)
+ bfin_pmu_start(event, PERF_EF_RELOAD);
+
+ perf_event_update_userpage(event);
+ ret = 0;
+out:
+ perf_pmu_enable(event->pmu);
+ return ret;
+}
+
+static void bfin_pmu_read(struct perf_event *event)
+{
+ bfin_perf_event_update(event, &event->hw, event->hw.idx);
+}
+
+static int bfin_pmu_event_init(struct perf_event *event)
+{
+ struct perf_event_attr *attr = &event->attr;
+ struct hw_perf_event *hwc = &event->hw;
+ int config = -1;
+ int ret;
+
+ if (attr->exclude_hv || attr->exclude_idle)
+ return -EPERM;
+
+ /*
+ * All of the on-chip counters are "limited", in that they have
+ * no interrupts, and are therefore unable to do sampling without
+ * further work and timer assistance.
+ */
+ if (hwc->sample_period)
+ return -EINVAL;
+
+ ret = 0;
+ switch (attr->type) {
+ case PERF_TYPE_RAW:
+ config = PFMON(0, attr->config & PFMON_MASK) |
+ PFCNT(0, !(attr->config & 0x100));
+ break;
+ case PERF_TYPE_HW_CACHE:
+ ret = hw_perf_cache_event(attr->config, &config);
+ break;
+ case PERF_TYPE_HARDWARE:
+ if (attr->config >= ARRAY_SIZE(event_map))
+ return -EINVAL;
+
+ config = event_map[attr->config];
+ break;
+ }
+
+ if (config == -1)
+ return -EINVAL;
+
+ if (!attr->exclude_kernel)
+ config |= PFCEN(0, PFCEN_ENABLE_SUPV);
+ if (!attr->exclude_user)
+ config |= PFCEN(0, PFCEN_ENABLE_USER);
+
+ hwc->config |= config;
+
+ return ret;
+}
+
+static void bfin_pmu_enable(struct pmu *pmu)
+{
+ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+ struct perf_event *event;
+ struct hw_perf_event *hwc;
+ int i;
+
+ for (i = 0; i < MAX_HWEVENTS; ++i) {
+ event = cpuc->events[i];
+ if (!event)
+ continue;
+ hwc = &event->hw;
+ bfin_pfmon_enable(hwc, hwc->idx);
+ }
+
+ bfin_pfmon_enable_all();
+}
+
+static void bfin_pmu_disable(struct pmu *pmu)
+{
+ bfin_pfmon_disable_all();
+}
+
+static struct pmu pmu = {
+ .pmu_enable = bfin_pmu_enable,
+ .pmu_disable = bfin_pmu_disable,
+ .event_init = bfin_pmu_event_init,
+ .add = bfin_pmu_add,
+ .del = bfin_pmu_del,
+ .start = bfin_pmu_start,
+ .stop = bfin_pmu_stop,
+ .read = bfin_pmu_read,
+};
+
+static void bfin_pmu_setup(int cpu)
+{
+ struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
+
+ memset(cpuhw, 0, sizeof(struct cpu_hw_events));
+}
+
+static int __cpuinit
+bfin_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
+{
+ unsigned int cpu = (long)hcpu;
+
+ switch (action & ~CPU_TASKS_FROZEN) {
+ case CPU_UP_PREPARE:
+ bfin_write_PFCTL(0);
+ bfin_pmu_setup(cpu);
+ break;
+
+ default:
+ break;
+ }
+
+ return NOTIFY_OK;
+}
+
+static int __init bfin_pmu_init(void)
+{
+ int ret;
+
+ ret = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
+ if (!ret)
+ perf_cpu_notifier(bfin_pmu_notifier);
+
+ return ret;
+}
+early_initcall(bfin_pmu_init);
unsigned long newsp;
#ifdef __ARCH_SYNC_CORE_DCACHE
- if (current->rt.nr_cpus_allowed == num_possible_cpus()) {
- current->cpus_allowed = cpumask_of_cpu(smp_processor_id());
- current->rt.nr_cpus_allowed = 1;
- }
+ if (current->rt.nr_cpus_allowed == num_possible_cpus())
+ set_cpus_allowed_ptr(current, cpumask_of(smp_processor_id()));
#endif
/* syscall2 puts clone_flags in r0 and usp in r1 */
__attribute__ ((__l1_text__, __noreturn__))
static void bfin_reset(void)
{
+ if (!ANOMALY_05000353 && !ANOMALY_05000386)
+ bfrom_SoftReset((void *)(L1_SCRATCH_START + L1_SCRATCH_LENGTH - 20));
+
/* Wait for completion of "system" events such as cache line
* line fills so that we avoid infinite stalls later on as
* much as possible. This code is in L1, so it won't trigger
*/
__builtin_bfin_ssync();
- /* The bootrom checks to see how it was reset and will
- * automatically perform a software reset for us when
- * it starts executing after the core reset.
- */
- if (ANOMALY_05000353 || ANOMALY_05000386) {
- /* Initiate System software reset. */
- bfin_write_SWRST(0x7);
+ /* Initiate System software reset. */
+ bfin_write_SWRST(0x7);
- /* Due to the way reset is handled in the hardware, we need
- * to delay for 10 SCLKS. The only reliable way to do this is
- * to calculate the CCLK/SCLK ratio and multiply 10. For now,
- * we'll assume worse case which is a 1:15 ratio.
- */
- asm(
- "LSETUP (1f, 1f) LC0 = %0\n"
- "1: nop;"
- :
- : "a" (15 * 10)
- : "LC0", "LB0", "LT0"
- );
+ /* Due to the way reset is handled in the hardware, we need
+ * to delay for 10 SCLKS. The only reliable way to do this is
+ * to calculate the CCLK/SCLK ratio and multiply 10. For now,
+ * we'll assume worse case which is a 1:15 ratio.
+ */
+ asm(
+ "LSETUP (1f, 1f) LC0 = %0\n"
+ "1: nop;"
+ :
+ : "a" (15 * 10)
+ : "LC0", "LB0", "LT0"
+ );
- /* Clear System software reset */
- bfin_write_SWRST(0);
+ /* Clear System software reset */
+ bfin_write_SWRST(0);
- /* The BF526 ROM will crash during reset */
+ /* The BF526 ROM will crash during reset */
#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
- bfin_read_SWRST();
+ bfin_read_SWRST();
#endif
- /* Wait for the SWRST write to complete. Cannot rely on SSYNC
- * though as the System state is all reset now.
- */
- asm(
- "LSETUP (1f, 1f) LC1 = %0\n"
- "1: nop;"
- :
- : "a" (15 * 1)
- : "LC1", "LB1", "LT1"
- );
- }
+ /* Wait for the SWRST write to complete. Cannot rely on SSYNC
+ * though as the System state is all reset now.
+ */
+ asm(
+ "LSETUP (1f, 1f) LC1 = %0\n"
+ "1: nop;"
+ :
+ : "a" (15 * 1)
+ : "LC1", "LB1", "LT1"
+ );
while (1)
/* Issue core reset */
#include <asm/cpu.h>
#include <asm/fixed_code.h>
#include <asm/early_printk.h>
+#include <asm/irq_handler.h>
u16 _bfin_swrst;
EXPORT_SYMBOL(_bfin_swrst);
bfin_dcache_init(dcplb_tbl[cpu]);
#endif
+ bfin_setup_cpudata(cpu);
+
/*
* In cache coherence emulation mode, we need to have the
* D-cache enabled before running any atomic operation which
{
struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu);
- cpudata->idle = current;
cpudata->imemctl = bfin_read_IMEM_CONTROL();
cpudata->dmemctl = bfin_read_DMEM_CONTROL();
}
void __init setup_arch(char **cmdline_p)
{
+ u32 mmr;
unsigned long sclk, cclk;
native_machine_early_platform_add_devices();
bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL);
#endif
#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
- bfin_write_PORTF_HYSTERISIS(HYST_PORTF_0_15);
- bfin_write_PORTG_HYSTERISIS(HYST_PORTG_0_15);
- bfin_write_PORTH_HYSTERISIS(HYST_PORTH_0_15);
- bfin_write_MISCPORT_HYSTERISIS((bfin_read_MISCPORT_HYSTERISIS() &
+ bfin_write_PORTF_HYSTERESIS(HYST_PORTF_0_15);
+ bfin_write_PORTG_HYSTERESIS(HYST_PORTG_0_15);
+ bfin_write_PORTH_HYSTERESIS(HYST_PORTH_0_15);
+ bfin_write_MISCPORT_HYSTERESIS((bfin_read_MISCPORT_HYSTERESIS() &
~HYST_NONEGPIO_MASK) | HYST_NONEGPIO);
#endif
bfin_read_IMDMA_D1_IRQ_STATUS();
}
#endif
- printk(KERN_INFO "Hardware Trace ");
- if (bfin_read_TBUFCTL() & 0x1)
- printk(KERN_CONT "Active ");
- else
- printk(KERN_CONT "Off ");
- if (bfin_read_TBUFCTL() & 0x2)
- printk(KERN_CONT "and Enabled\n");
- else
- printk(KERN_CONT "and Disabled\n");
- printk(KERN_INFO "Boot Mode: %i\n", bfin_read_SYSCR() & 0xF);
+ mmr = bfin_read_TBUFCTL();
+ printk(KERN_INFO "Hardware Trace %s and %sabled\n",
+ (mmr & 0x1) ? "active" : "off",
+ (mmr & 0x2) ? "en" : "dis");
+
+ mmr = bfin_read_SYSCR();
+ printk(KERN_INFO "Boot Mode: %i\n", mmr & 0xF);
/* Newer parts mirror SWRST bits in SYSCR */
#if defined(CONFIG_BF53x) || defined(CONFIG_BF561) || \
_bfin_swrst = bfin_read_SWRST();
#else
/* Clear boot mode field */
- _bfin_swrst = bfin_read_SYSCR() & ~0xf;
+ _bfin_swrst = mmr & ~0xf;
#endif
#ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
static int __init topology_init(void)
{
unsigned int cpu;
- /* Record CPU-private information for the boot processor. */
- bfin_setup_cpudata(0);
for_each_possible_cpu(cpu) {
register_cpu(&per_cpu(cpu_data, cpu).cpu, cpu);
dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS,
BFIN_DLINES);
#ifdef __ARCH_SYNC_CORE_DCACHE
- seq_printf(m, "SMP Dcache Flushes\t: %lu\n\n", dcache_invld_count[cpu_num]);
+ seq_printf(m, "dcache flushes\t: %lu\n", dcache_invld_count[cpu_num]);
#endif
#ifdef __ARCH_SYNC_CORE_ICACHE
- seq_printf(m, "SMP Icache Flushes\t: %lu\n\n", icache_invld_count[cpu_num]);
+ seq_printf(m, "icache flushes\t: %lu\n", icache_invld_count[cpu_num]);
#endif
+ seq_printf(m, "\n");
+
if (cpu_num != num_possible_cpus() - 1)
return 0;
" in data cache\n");
}
seq_printf(m, "board name\t: %s\n", bfin_board_name);
- seq_printf(m, "board memory\t: %ld kB (0x%p -> 0x%p)\n",
- physical_mem_end >> 10, (void *)0, (void *)physical_mem_end);
- seq_printf(m, "kernel memory\t: %d kB (0x%p -> 0x%p)\n",
+ seq_printf(m, "board memory\t: %ld kB (0x%08lx -> 0x%08lx)\n",
+ physical_mem_end >> 10, 0ul, physical_mem_end);
+ seq_printf(m, "kernel memory\t: %d kB (0x%08lx -> 0x%08lx)\n",
((int)memory_end - (int)_rambase) >> 10,
- (void *)_rambase,
- (void *)memory_end);
- seq_printf(m, "\n");
+ _rambase, memory_end);
return 0;
}
static void *c_start(struct seq_file *m, loff_t *pos)
{
if (*pos == 0)
- *pos = first_cpu(cpu_online_map);
+ *pos = cpumask_first(cpu_online_mask);
if (*pos >= num_online_cpus())
return NULL;
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
{
- *pos = next_cpu(*pos, cpu_online_map);
+ *pos = cpumask_next(*pos, cpu_online_mask);
return c_start(m, pos);
}
SECURITY_INITCALL
INIT_RAM_FS
- . = ALIGN(4);
___per_cpu_load = .;
- ___per_cpu_start = .;
- *(.data.percpu.first)
- *(.data.percpu.page_aligned)
- *(.data.percpu)
- *(.data.percpu.shared_aligned)
- ___per_cpu_end = .;
+ PERCPU_INPUT(32)
EXIT_DATA
__einitdata = .;
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
#define ANOMALY_05000364 (0)
#define ANOMALY_05000371 (0)
#define ANOMALY_05000380 (0)
+#define ANOMALY_05000383 (0)
#define ANOMALY_05000386 (0)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0)
#define ANOMALY_05000475 (0)
+#define ANOMALY_05000480 (0)
#define ANOMALY_05000485 (0)
#endif
#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val)
#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW)
#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val)
-#define bfin_read_PORTF_HYSTERISIS() bfin_read16(PORTF_HYSTERISIS)
-#define bfin_write_PORTF_HYSTERISIS(val) bfin_write16(PORTF_HYSTERISIS, val)
-#define bfin_read_PORTG_HYSTERISIS() bfin_read16(PORTG_HYSTERISIS)
-#define bfin_write_PORTG_HYSTERISIS(val) bfin_write16(PORTG_HYSTERISIS, val)
-#define bfin_read_PORTH_HYSTERISIS() bfin_read16(PORTH_HYSTERISIS)
-#define bfin_write_PORTH_HYSTERISIS(val) bfin_write16(PORTH_HYSTERISIS, val)
+#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS)
+#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
+#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS)
+#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
+#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS)
+#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE)
#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val)
#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW)
#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val)
-#define bfin_read_MISCPORT_HYSTERISIS() bfin_read16(MISCPORT_HYSTERISIS)
-#define bfin_write_MISCPORT_HYSTERISIS(val) bfin_write16(MISCPORT_HYSTERISIS, val)
+#define bfin_read_MISCPORT_HYSTERESIS() bfin_read16(MISCPORT_HYSTERESIS)
+#define bfin_write_MISCPORT_HYSTERESIS(val) bfin_write16(MISCPORT_HYSTERESIS, val)
/* HOST Port Registers */
#define PORTF_SLEW 0xFFC03230 /* Port F slew control */
#define PORTG_SLEW 0xFFC03234 /* Port G slew control */
#define PORTH_SLEW 0xFFC03238 /* Port H slew control */
-#define PORTF_HYSTERISIS 0xFFC03240 /* Port F Schmitt trigger control */
-#define PORTG_HYSTERISIS 0xFFC03244 /* Port G Schmitt trigger control */
-#define PORTH_HYSTERISIS 0xFFC03248 /* Port H Schmitt trigger control */
+#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */
+#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */
+#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */
#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */
#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */
-#define MISCPORT_HYSTERISIS 0xFFC03288 /* Misc Port Schmitt trigger control */
+#define MISCPORT_HYSTERESIS 0xFFC03288 /* Misc Port Schmitt trigger control */
/***********************************************************************************
#ifndef _BF518_IRQ_H_
#define _BF518_IRQ_H_
-/*
- * Interrupt source definitions
- Event Source Core Event Name
- Core Emulation **
- Events (highest priority) EMU 0
- Reset RST 1
- NMI NMI 2
- Exception EVX 3
- Reserved -- 4
- Hardware Error IVHW 5
- Core Timer IVTMR 6 *
-
- .....
-
- Software Interrupt 1 IVG14 31
- Software Interrupt 2 --
- (lowest priority) IVG15 32 *
-*/
-
-#define NR_PERI_INTS (2 * 32)
-
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU 0 /* Emulation */
-#define IRQ_RST 1 /* reset */
-#define IRQ_NMI 2 /* Non Maskable */
-#define IRQ_EVX 3 /* Exception */
-#define IRQ_UNUSED 4 /* - unused interrupt */
-#define IRQ_HWERR 5 /* Hardware Error */
-#define IRQ_CORETMR 6 /* Core timer */
-
-#define BFIN_IRQ(x) ((x) + 7)
+#include <mach-common/irq.h>
+
+#define NR_PERI_INTS (2 * 32)
#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
#define IRQ_RTC BFIN_IRQ(14) /* RTC */
-#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI) */
+#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI) */
#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
#define IRQ_RSI BFIN_IRQ(17) /* DMA 4 Channel (RSI) */
#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX/SPI) */
#define IRQ_SPI1 BFIN_IRQ(18) /* DMA 5 Channel (SPI1) */
#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
-#define IRQ_TWI BFIN_IRQ(20) /* TWI */
-#define IRQ_SPI0 BFIN_IRQ(21) /* DMA 7 Channel (SPI0) */
-#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
-#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
-#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
-#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
-#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
-#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
-#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX) */
-#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
+#define IRQ_TWI BFIN_IRQ(20) /* TWI */
+#define IRQ_SPI0 BFIN_IRQ(21) /* DMA 7 Channel (SPI0) */
+#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
+#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
+#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
+#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
+#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
+#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
+#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX) */
+#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX) */
#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */
#define IRQ_PWM_SYNC BFIN_IRQ(54) /* PWM Sync Interrupt */
#define IRQ_PTP_STAT BFIN_IRQ(55) /* PTP Stat Interrupt */
-#define SYS_IRQS BFIN_IRQ(63) /* 70 */
-
-#define IRQ_PF0 71
-#define IRQ_PF1 72
-#define IRQ_PF2 73
-#define IRQ_PF3 74
-#define IRQ_PF4 75
-#define IRQ_PF5 76
-#define IRQ_PF6 77
-#define IRQ_PF7 78
-#define IRQ_PF8 79
-#define IRQ_PF9 80
-#define IRQ_PF10 81
-#define IRQ_PF11 82
-#define IRQ_PF12 83
-#define IRQ_PF13 84
-#define IRQ_PF14 85
-#define IRQ_PF15 86
-
-#define IRQ_PG0 87
-#define IRQ_PG1 88
-#define IRQ_PG2 89
-#define IRQ_PG3 90
-#define IRQ_PG4 91
-#define IRQ_PG5 92
-#define IRQ_PG6 93
-#define IRQ_PG7 94
-#define IRQ_PG8 95
-#define IRQ_PG9 96
-#define IRQ_PG10 97
-#define IRQ_PG11 98
-#define IRQ_PG12 99
-#define IRQ_PG13 100
-#define IRQ_PG14 101
-#define IRQ_PG15 102
-
-#define IRQ_PH0 103
-#define IRQ_PH1 104
-#define IRQ_PH2 105
-#define IRQ_PH3 106
-#define IRQ_PH4 107
-#define IRQ_PH5 108
-#define IRQ_PH6 109
-#define IRQ_PH7 110
-#define IRQ_PH8 111
-#define IRQ_PH9 112
-#define IRQ_PH10 113
-#define IRQ_PH11 114
-#define IRQ_PH12 115
-#define IRQ_PH13 116
-#define IRQ_PH14 117
-#define IRQ_PH15 118
-
-#define GPIO_IRQ_BASE IRQ_PF0
-
-#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
-#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
-#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
-#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
-#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
-#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
-#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
-#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
-
-#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
-#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
-
-#define IVG7 7
-#define IVG8 8
-#define IVG9 9
-#define IVG10 10
-#define IVG11 11
-#define IVG12 12
-#define IVG13 13
-#define IVG14 14
-#define IVG15 15
+#define SYS_IRQS BFIN_IRQ(63) /* 70 */
+
+#define IRQ_PF0 71
+#define IRQ_PF1 72
+#define IRQ_PF2 73
+#define IRQ_PF3 74
+#define IRQ_PF4 75
+#define IRQ_PF5 76
+#define IRQ_PF6 77
+#define IRQ_PF7 78
+#define IRQ_PF8 79
+#define IRQ_PF9 80
+#define IRQ_PF10 81
+#define IRQ_PF11 82
+#define IRQ_PF12 83
+#define IRQ_PF13 84
+#define IRQ_PF14 85
+#define IRQ_PF15 86
+
+#define IRQ_PG0 87
+#define IRQ_PG1 88
+#define IRQ_PG2 89
+#define IRQ_PG3 90
+#define IRQ_PG4 91
+#define IRQ_PG5 92
+#define IRQ_PG6 93
+#define IRQ_PG7 94
+#define IRQ_PG8 95
+#define IRQ_PG9 96
+#define IRQ_PG10 97
+#define IRQ_PG11 98
+#define IRQ_PG12 99
+#define IRQ_PG13 100
+#define IRQ_PG14 101
+#define IRQ_PG15 102
+
+#define IRQ_PH0 103
+#define IRQ_PH1 104
+#define IRQ_PH2 105
+#define IRQ_PH3 106
+#define IRQ_PH4 107
+#define IRQ_PH5 108
+#define IRQ_PH6 109
+#define IRQ_PH7 110
+#define IRQ_PH8 111
+#define IRQ_PH9 112
+#define IRQ_PH10 113
+#define IRQ_PH11 114
+#define IRQ_PH12 115
+#define IRQ_PH13 116
+#define IRQ_PH14 117
+#define IRQ_PH15 118
+
+#define GPIO_IRQ_BASE IRQ_PF0
+
+#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
+#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
+#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
+#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
+#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
+#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
+#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
+#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
+
+#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
/* IAR0 BIT FIELDS */
#define IRQ_PLL_WAKEUP_POS 0
#define IRQ_DMA0_ERROR_POS 4
-#define IRQ_DMAR0_BLK_POS 8
-#define IRQ_DMAR1_BLK_POS 12
-#define IRQ_DMAR0_OVR_POS 16
-#define IRQ_DMAR1_OVR_POS 20
-#define IRQ_PPI_ERROR_POS 24
-#define IRQ_MAC_ERROR_POS 28
+#define IRQ_DMAR0_BLK_POS 8
+#define IRQ_DMAR1_BLK_POS 12
+#define IRQ_DMAR0_OVR_POS 16
+#define IRQ_DMAR1_OVR_POS 20
+#define IRQ_PPI_ERROR_POS 24
+#define IRQ_MAC_ERROR_POS 28
/* IAR1 BIT FIELDS */
#define IRQ_SPORT0_ERROR_POS 0
#define IRQ_SPORT1_ERROR_POS 4
#define IRQ_PTP_ERROR_POS 8
-#define IRQ_UART0_ERROR_POS 16
-#define IRQ_UART1_ERROR_POS 20
-#define IRQ_RTC_POS 24
-#define IRQ_PPI_POS 28
+#define IRQ_UART0_ERROR_POS 16
+#define IRQ_UART1_ERROR_POS 20
+#define IRQ_RTC_POS 24
+#define IRQ_PPI_POS 28
/* IAR2 BIT FIELDS */
#define IRQ_SPORT0_RX_POS 0
#define IRQ_SPORT1_RX_POS 8
#define IRQ_SPI1_POS 8
#define IRQ_SPORT1_TX_POS 12
-#define IRQ_TWI_POS 16
-#define IRQ_SPI0_POS 20
-#define IRQ_UART0_RX_POS 24
-#define IRQ_UART0_TX_POS 28
+#define IRQ_TWI_POS 16
+#define IRQ_SPI0_POS 20
+#define IRQ_UART0_RX_POS 24
+#define IRQ_UART0_TX_POS 28
/* IAR3 BIT FIELDS */
-#define IRQ_UART1_RX_POS 0
-#define IRQ_UART1_TX_POS 4
-#define IRQ_OPTSEC_POS 8
-#define IRQ_CNT_POS 12
-#define IRQ_MAC_RX_POS 16
+#define IRQ_UART1_RX_POS 0
+#define IRQ_UART1_TX_POS 4
+#define IRQ_OPTSEC_POS 8
+#define IRQ_CNT_POS 12
+#define IRQ_MAC_RX_POS 16
#define IRQ_PORTH_INTA_POS 20
-#define IRQ_MAC_TX_POS 24
+#define IRQ_MAC_TX_POS 24
#define IRQ_PORTH_INTB_POS 28
/* IAR4 BIT FIELDS */
/* IAR5 BIT FIELDS */
#define IRQ_PORTG_INTA_POS 0
#define IRQ_PORTG_INTB_POS 4
-#define IRQ_MEM_DMA0_POS 8
-#define IRQ_MEM_DMA1_POS 12
-#define IRQ_WATCH_POS 16
+#define IRQ_MEM_DMA0_POS 8
+#define IRQ_MEM_DMA1_POS 12
+#define IRQ_WATCH_POS 16
#define IRQ_PORTF_INTA_POS 20
#define IRQ_PORTF_INTB_POS 24
-#define IRQ_SPI0_ERROR_POS 28
+#define IRQ_SPI0_ERROR_POS 28
/* IAR6 BIT FIELDS */
-#define IRQ_SPI1_ERROR_POS 0
-#define IRQ_RSI_INT0_POS 12
-#define IRQ_RSI_INT1_POS 16
-#define IRQ_PWM_TRIP_POS 20
-#define IRQ_PWM_SYNC_POS 24
-#define IRQ_PTP_STAT_POS 28
-
-#endif /* _BF518_IRQ_H_ */
+#define IRQ_SPI1_ERROR_POS 0
+#define IRQ_RSI_INT0_POS 12
+#define IRQ_RSI_INT1_POS 16
+#define IRQ_PWM_TRIP_POS 20
+#define IRQ_PWM_SYNC_POS 24
+#define IRQ_PTP_STAT_POS 28
+
+#endif
#include <asm/portmux.h>
#include <asm/dpmc.h>
#include <linux/spi/ad7877.h>
+#include <asm/bfin_sport.h>
/*
* Name the Board for the /proc/cpuinfo
};
#endif
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
+ defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
+
+static const u16 bfin_snd_pin[][7] = {
+ {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
+ P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0, 0},
+ {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
+ P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_TFS, 0},
+};
+
+static struct bfin_snd_platform_data bfin_snd_data[] = {
+ {
+ .pin_req = &bfin_snd_pin[0][0],
+ },
+ {
+ .pin_req = &bfin_snd_pin[1][0],
+ },
+};
+
+#define BFIN_SND_RES(x) \
+ [x] = { \
+ { \
+ .start = SPORT##x##_TCR1, \
+ .end = SPORT##x##_TCR1, \
+ .flags = IORESOURCE_MEM \
+ }, \
+ { \
+ .start = CH_SPORT##x##_RX, \
+ .end = CH_SPORT##x##_RX, \
+ .flags = IORESOURCE_DMA, \
+ }, \
+ { \
+ .start = CH_SPORT##x##_TX, \
+ .end = CH_SPORT##x##_TX, \
+ .flags = IORESOURCE_DMA, \
+ }, \
+ { \
+ .start = IRQ_SPORT##x##_ERROR, \
+ .end = IRQ_SPORT##x##_ERROR, \
+ .flags = IORESOURCE_IRQ, \
+ } \
+ }
+
+static struct resource bfin_snd_resources[][4] = {
+ BFIN_SND_RES(0),
+ BFIN_SND_RES(1),
+};
+
+static struct platform_device bfin_pcm = {
+ .name = "bfin-pcm-audio",
+ .id = -1,
+};
+#endif
+
#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
static struct platform_device bfin_i2s = {
.name = "bfin-i2s",
.id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
+ .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
+ .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
+ .dev = {
+ .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
+ },
};
#endif
static struct platform_device bfin_tdm = {
.name = "bfin-tdm",
.id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
+ .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
+ .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
+ .dev = {
+ .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
+ },
};
#endif
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 4,
+ .platform_data = "ad1836",
.controller_data = &ad1836_spi_chip_info,
+ .mode = SPI_MODE_3,
},
#endif
#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
&ezkit_flash_device,
#endif
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
+ defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
+ &bfin_pcm,
+#endif
+
#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
&bfin_i2s,
#endif
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
* - Revision E, 03/15/2010; ADSP-BF526 Blackfin Processor Anomaly List
- * - Revision G, 08/25/2009; ADSP-BF527 Blackfin Processor Anomaly List
+ * - Revision H, 04/29/2010; ADSP-BF527 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define ANOMALY_05000483 (1)
/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, < 3))
+/* The CODEC Zero-Cross Detect Feature is not Functional */
+#define ANOMALY_05000487 (1)
/* IFLUSH sucks at life */
#define ANOMALY_05000491 (1)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000362 (1)
#define ANOMALY_05000363 (0)
+#define ANOMALY_05000383 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000402 (0)
#define ANOMALY_05000412 (0)
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
#define ANOMALY_05000474 (0)
+#define ANOMALY_05000480 (0)
#endif
#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val)
#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW)
#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val)
-#define bfin_read_PORTF_HYSTERISIS() bfin_read16(PORTF_HYSTERISIS)
-#define bfin_write_PORTF_HYSTERISIS(val) bfin_write16(PORTF_HYSTERISIS, val)
-#define bfin_read_PORTG_HYSTERISIS() bfin_read16(PORTG_HYSTERISIS)
-#define bfin_write_PORTG_HYSTERISIS(val) bfin_write16(PORTG_HYSTERISIS, val)
-#define bfin_read_PORTH_HYSTERISIS() bfin_read16(PORTH_HYSTERISIS)
-#define bfin_write_PORTH_HYSTERISIS(val) bfin_write16(PORTH_HYSTERISIS, val)
+#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS)
+#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
+#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS)
+#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
+#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS)
+#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE)
#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val)
#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW)
#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val)
-#define bfin_read_MISCPORT_HYSTERISIS() bfin_read16(MISCPORT_HYSTERISIS)
-#define bfin_write_MISCPORT_HYSTERISIS(val) bfin_write16(MISCPORT_HYSTERISIS, val)
+#define bfin_read_MISCPORT_HYSTERESIS() bfin_read16(MISCPORT_HYSTERESIS)
+#define bfin_write_MISCPORT_HYSTERESIS(val) bfin_write16(MISCPORT_HYSTERESIS, val)
/* HOST Port Registers */
#define PORTF_SLEW 0xFFC03230 /* Port F slew control */
#define PORTG_SLEW 0xFFC03234 /* Port G slew control */
#define PORTH_SLEW 0xFFC03238 /* Port H slew control */
-#define PORTF_HYSTERISIS 0xFFC03240 /* Port F Schmitt trigger control */
-#define PORTG_HYSTERISIS 0xFFC03244 /* Port G Schmitt trigger control */
-#define PORTH_HYSTERISIS 0xFFC03248 /* Port H Schmitt trigger control */
+#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */
+#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */
+#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */
#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */
#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */
-#define MISCPORT_HYSTERISIS 0xFFC03288 /* Misc Port Schmitt trigger control */
+#define MISCPORT_HYSTERESIS 0xFFC03288 /* Misc Port Schmitt trigger control */
/***********************************************************************************
#ifndef _BF527_IRQ_H_
#define _BF527_IRQ_H_
-/*
- * Interrupt source definitions
- Event Source Core Event Name
- Core Emulation **
- Events (highest priority) EMU 0
- Reset RST 1
- NMI NMI 2
- Exception EVX 3
- Reserved -- 4
- Hardware Error IVHW 5
- Core Timer IVTMR 6 *
-
- .....
-
- Software Interrupt 1 IVG14 31
- Software Interrupt 2 --
- (lowest priority) IVG15 32 *
-*/
-
-#define NR_PERI_INTS (2 * 32)
-
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU 0 /* Emulation */
-#define IRQ_RST 1 /* reset */
-#define IRQ_NMI 2 /* Non Maskable */
-#define IRQ_EVX 3 /* Exception */
-#define IRQ_UNUSED 4 /* - unused interrupt */
-#define IRQ_HWERR 5 /* Hardware Error */
-#define IRQ_CORETMR 6 /* Core timer */
-
-#define BFIN_IRQ(x) ((x) + 7)
+#include <mach-common/irq.h>
+
+#define NR_PERI_INTS (2 * 32)
#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
#define IRQ_RTC BFIN_IRQ(14) /* RTC */
-#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI/NAND) */
+#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI/NAND) */
#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX) */
#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
-#define IRQ_TWI BFIN_IRQ(20) /* TWI */
-#define IRQ_SPI BFIN_IRQ(21) /* DMA 7 Channel (SPI) */
-#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
-#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
-#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
-#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
-#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
-#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
-#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX/HDMA) */
-#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
+#define IRQ_TWI BFIN_IRQ(20) /* TWI */
+#define IRQ_SPI BFIN_IRQ(21) /* DMA 7 Channel (SPI) */
+#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
+#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
+#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
+#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
+#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
+#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
+#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX/HDMA) */
+#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
#define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
#define IRQ_USB_INT2 BFIN_IRQ(54) /* USB_INT2 Interrupt */
#define IRQ_USB_DMA BFIN_IRQ(55) /* USB_DMAINT Interrupt */
-#define SYS_IRQS BFIN_IRQ(63) /* 70 */
-
-#define IRQ_PF0 71
-#define IRQ_PF1 72
-#define IRQ_PF2 73
-#define IRQ_PF3 74
-#define IRQ_PF4 75
-#define IRQ_PF5 76
-#define IRQ_PF6 77
-#define IRQ_PF7 78
-#define IRQ_PF8 79
-#define IRQ_PF9 80
-#define IRQ_PF10 81
-#define IRQ_PF11 82
-#define IRQ_PF12 83
-#define IRQ_PF13 84
-#define IRQ_PF14 85
-#define IRQ_PF15 86
-
-#define IRQ_PG0 87
-#define IRQ_PG1 88
-#define IRQ_PG2 89
-#define IRQ_PG3 90
-#define IRQ_PG4 91
-#define IRQ_PG5 92
-#define IRQ_PG6 93
-#define IRQ_PG7 94
-#define IRQ_PG8 95
-#define IRQ_PG9 96
-#define IRQ_PG10 97
-#define IRQ_PG11 98
-#define IRQ_PG12 99
-#define IRQ_PG13 100
-#define IRQ_PG14 101
-#define IRQ_PG15 102
-
-#define IRQ_PH0 103
-#define IRQ_PH1 104
-#define IRQ_PH2 105
-#define IRQ_PH3 106
-#define IRQ_PH4 107
-#define IRQ_PH5 108
-#define IRQ_PH6 109
-#define IRQ_PH7 110
-#define IRQ_PH8 111
-#define IRQ_PH9 112
-#define IRQ_PH10 113
-#define IRQ_PH11 114
-#define IRQ_PH12 115
-#define IRQ_PH13 116
-#define IRQ_PH14 117
-#define IRQ_PH15 118
-
-#define GPIO_IRQ_BASE IRQ_PF0
-
-#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
-#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
-#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
-#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
-#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
-#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
-#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
-#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
-
-#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
-#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
-
-#define IVG7 7
-#define IVG8 8
-#define IVG9 9
-#define IVG10 10
-#define IVG11 11
-#define IVG12 12
-#define IVG13 13
-#define IVG14 14
-#define IVG15 15
+#define SYS_IRQS BFIN_IRQ(63) /* 70 */
+
+#define IRQ_PF0 71
+#define IRQ_PF1 72
+#define IRQ_PF2 73
+#define IRQ_PF3 74
+#define IRQ_PF4 75
+#define IRQ_PF5 76
+#define IRQ_PF6 77
+#define IRQ_PF7 78
+#define IRQ_PF8 79
+#define IRQ_PF9 80
+#define IRQ_PF10 81
+#define IRQ_PF11 82
+#define IRQ_PF12 83
+#define IRQ_PF13 84
+#define IRQ_PF14 85
+#define IRQ_PF15 86
+
+#define IRQ_PG0 87
+#define IRQ_PG1 88
+#define IRQ_PG2 89
+#define IRQ_PG3 90
+#define IRQ_PG4 91
+#define IRQ_PG5 92
+#define IRQ_PG6 93
+#define IRQ_PG7 94
+#define IRQ_PG8 95
+#define IRQ_PG9 96
+#define IRQ_PG10 97
+#define IRQ_PG11 98
+#define IRQ_PG12 99
+#define IRQ_PG13 100
+#define IRQ_PG14 101
+#define IRQ_PG15 102
+
+#define IRQ_PH0 103
+#define IRQ_PH1 104
+#define IRQ_PH2 105
+#define IRQ_PH3 106
+#define IRQ_PH4 107
+#define IRQ_PH5 108
+#define IRQ_PH6 109
+#define IRQ_PH7 110
+#define IRQ_PH8 111
+#define IRQ_PH9 112
+#define IRQ_PH10 113
+#define IRQ_PH11 114
+#define IRQ_PH12 115
+#define IRQ_PH13 116
+#define IRQ_PH14 117
+#define IRQ_PH15 118
+
+#define GPIO_IRQ_BASE IRQ_PF0
+
+#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
+#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
+#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
+#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
+#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
+#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
+#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
+#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
+
+#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
/* IAR0 BIT FIELDS */
#define IRQ_PLL_WAKEUP_POS 0
#define IRQ_DMA0_ERROR_POS 4
-#define IRQ_DMAR0_BLK_POS 8
-#define IRQ_DMAR1_BLK_POS 12
-#define IRQ_DMAR0_OVR_POS 16
-#define IRQ_DMAR1_OVR_POS 20
-#define IRQ_PPI_ERROR_POS 24
-#define IRQ_MAC_ERROR_POS 28
+#define IRQ_DMAR0_BLK_POS 8
+#define IRQ_DMAR1_BLK_POS 12
+#define IRQ_DMAR0_OVR_POS 16
+#define IRQ_DMAR1_OVR_POS 20
+#define IRQ_PPI_ERROR_POS 24
+#define IRQ_MAC_ERROR_POS 28
/* IAR1 BIT FIELDS */
#define IRQ_SPORT0_ERROR_POS 0
#define IRQ_SPORT1_ERROR_POS 4
-#define IRQ_UART0_ERROR_POS 16
-#define IRQ_UART1_ERROR_POS 20
-#define IRQ_RTC_POS 24
-#define IRQ_PPI_POS 28
+#define IRQ_UART0_ERROR_POS 16
+#define IRQ_UART1_ERROR_POS 20
+#define IRQ_RTC_POS 24
+#define IRQ_PPI_POS 28
/* IAR2 BIT FIELDS */
#define IRQ_SPORT0_RX_POS 0
#define IRQ_SPORT0_TX_POS 4
#define IRQ_SPORT1_RX_POS 8
#define IRQ_SPORT1_TX_POS 12
-#define IRQ_TWI_POS 16
-#define IRQ_SPI_POS 20
-#define IRQ_UART0_RX_POS 24
-#define IRQ_UART0_TX_POS 28
+#define IRQ_TWI_POS 16
+#define IRQ_SPI_POS 20
+#define IRQ_UART0_RX_POS 24
+#define IRQ_UART0_TX_POS 28
/* IAR3 BIT FIELDS */
-#define IRQ_UART1_RX_POS 0
-#define IRQ_UART1_TX_POS 4
-#define IRQ_OPTSEC_POS 8
-#define IRQ_CNT_POS 12
-#define IRQ_MAC_RX_POS 16
+#define IRQ_UART1_RX_POS 0
+#define IRQ_UART1_TX_POS 4
+#define IRQ_OPTSEC_POS 8
+#define IRQ_CNT_POS 12
+#define IRQ_MAC_RX_POS 16
#define IRQ_PORTH_INTA_POS 20
-#define IRQ_MAC_TX_POS 24
+#define IRQ_MAC_TX_POS 24
#define IRQ_PORTH_INTB_POS 28
/* IAR4 BIT FIELDS */
/* IAR5 BIT FIELDS */
#define IRQ_PORTG_INTA_POS 0
#define IRQ_PORTG_INTB_POS 4
-#define IRQ_MEM_DMA0_POS 8
-#define IRQ_MEM_DMA1_POS 12
-#define IRQ_WATCH_POS 16
+#define IRQ_MEM_DMA0_POS 8
+#define IRQ_MEM_DMA1_POS 12
+#define IRQ_WATCH_POS 16
#define IRQ_PORTF_INTA_POS 20
#define IRQ_PORTF_INTB_POS 24
-#define IRQ_SPI_ERROR_POS 28
+#define IRQ_SPI_ERROR_POS 28
/* IAR6 BIT FIELDS */
-#define IRQ_NFC_ERROR_POS 0
-#define IRQ_HDMA_ERROR_POS 4
-#define IRQ_HDMA_POS 8
-#define IRQ_USB_EINT_POS 12
-#define IRQ_USB_INT0_POS 16
-#define IRQ_USB_INT1_POS 20
-#define IRQ_USB_INT2_POS 24
-#define IRQ_USB_DMA_POS 28
-
-#endif /* _BF527_IRQ_H_ */
+#define IRQ_NFC_ERROR_POS 0
+#define IRQ_HDMA_ERROR_POS 4
+#define IRQ_HDMA_POS 8
+#define IRQ_USB_EINT_POS 12
+#define IRQ_USB_INT0_POS 16
+#define IRQ_USB_INT1_POS 20
+#define IRQ_USB_INT2_POS 24
+#define IRQ_USB_DMA_POS 28
+
+#endif
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
- * - Revision E, 09/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
+ * - Revision F, 05/25/2010; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define ANOMALY_05000443 (1)
/* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1)
+/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
+#define ANOMALY_05000462 (1)
+/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
+#define ANOMALY_05000471 (1)
/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
#define ANOMALY_05000473 (1)
/* Possible Lockup Condition whem Modifying PLL from External Memory */
#define ANOMALY_05000362 (1)
#define ANOMALY_05000364 (0)
#define ANOMALY_05000380 (0)
+#define ANOMALY_05000383 (0)
#define ANOMALY_05000386 (1)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000412 (0)
#define ANOMALY_05000430 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
+#define ANOMALY_05000440 (0)
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0)
#define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0)
+#define ANOMALY_05000480 (0)
#define ANOMALY_05000485 (0)
#endif
#ifndef _BF533_IRQ_H_
#define _BF533_IRQ_H_
-/*
- * Interrupt source definitions
- Event Source Core Event Name
-Core Emulation **
- Events (highest priority) EMU 0
- Reset RST 1
- NMI NMI 2
- Exception EVX 3
- Reserved -- 4
- Hardware Error IVHW 5
- Core Timer IVTMR 6 *
- PLL Wakeup Interrupt IVG7 7
- DMA Error (generic) IVG7 8
- PPI Error Interrupt IVG7 9
- SPORT0 Error Interrupt IVG7 10
- SPORT1 Error Interrupt IVG7 11
- SPI Error Interrupt IVG7 12
- UART Error Interrupt IVG7 13
- RTC Interrupt IVG8 14
- DMA0 Interrupt (PPI) IVG8 15
- DMA1 (SPORT0 RX) IVG9 16
- DMA2 (SPORT0 TX) IVG9 17
- DMA3 (SPORT1 RX) IVG9 18
- DMA4 (SPORT1 TX) IVG9 19
- DMA5 (PPI) IVG10 20
- DMA6 (UART RX) IVG10 21
- DMA7 (UART TX) IVG10 22
- Timer0 IVG11 23
- Timer1 IVG11 24
- Timer2 IVG11 25
- PF Interrupt A IVG12 26
- PF Interrupt B IVG12 27
- DMA8/9 Interrupt IVG13 28
- DMA10/11 Interrupt IVG13 29
- Watchdog Timer IVG13 30
+#include <mach-common/irq.h>
- Softirq IVG14 31
- System Call --
- (lowest priority) IVG15 32 *
- */
-#define SYS_IRQS 31
-#define NR_PERI_INTS 24
+#define NR_PERI_INTS 24
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU 0 /*Emulation */
-#define IRQ_RST 1 /*reset */
-#define IRQ_NMI 2 /*Non Maskable */
-#define IRQ_EVX 3 /*Exception */
-#define IRQ_UNUSED 4 /*- unused interrupt*/
-#define IRQ_HWERR 5 /*Hardware Error */
-#define IRQ_CORETMR 6 /*Core timer */
+#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
+#define IRQ_DMA_ERROR BFIN_IRQ(1) /* DMA Error (general) */
+#define IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error Interrupt */
+#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Error Interrupt */
+#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Error Interrupt */
+#define IRQ_SPI_ERROR BFIN_IRQ(5) /* SPI Error Interrupt */
+#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART Error Interrupt */
+#define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */
+#define IRQ_PPI BFIN_IRQ(8) /* DMA0 Interrupt (PPI) */
+#define IRQ_SPORT0_RX BFIN_IRQ(9) /* DMA1 Interrupt (SPORT0 RX) */
+#define IRQ_SPORT0_TX BFIN_IRQ(10) /* DMA2 Interrupt (SPORT0 TX) */
+#define IRQ_SPORT1_RX BFIN_IRQ(11) /* DMA3 Interrupt (SPORT1 RX) */
+#define IRQ_SPORT1_TX BFIN_IRQ(12) /* DMA4 Interrupt (SPORT1 TX) */
+#define IRQ_SPI BFIN_IRQ(13) /* DMA5 Interrupt (SPI) */
+#define IRQ_UART0_RX BFIN_IRQ(14) /* DMA6 Interrupt (UART RX) */
+#define IRQ_UART0_TX BFIN_IRQ(15) /* DMA7 Interrupt (UART TX) */
+#define IRQ_TIMER0 BFIN_IRQ(16) /* Timer 0 */
+#define IRQ_TIMER1 BFIN_IRQ(17) /* Timer 1 */
+#define IRQ_TIMER2 BFIN_IRQ(18) /* Timer 2 */
+#define IRQ_PROG_INTA BFIN_IRQ(19) /* Programmable Flags A (8) */
+#define IRQ_PROG_INTB BFIN_IRQ(20) /* Programmable Flags B (8) */
+#define IRQ_MEM_DMA0 BFIN_IRQ(21) /* DMA8/9 Interrupt (Memory DMA Stream 0) */
+#define IRQ_MEM_DMA1 BFIN_IRQ(22) /* DMA10/11 Interrupt (Memory DMA Stream 1) */
+#define IRQ_WATCH BFIN_IRQ(23) /* Watch Dog Timer */
-#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */
-#define IRQ_DMA_ERROR 8 /*DMA Error (general) */
-#define IRQ_PPI_ERROR 9 /*PPI Error Interrupt */
-#define IRQ_SPORT0_ERROR 10 /*SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERROR 11 /*SPORT1 Error Interrupt */
-#define IRQ_SPI_ERROR 12 /*SPI Error Interrupt */
-#define IRQ_UART0_ERROR 13 /*UART Error Interrupt */
-#define IRQ_RTC 14 /*RTC Interrupt */
-#define IRQ_PPI 15 /*DMA0 Interrupt (PPI) */
-#define IRQ_SPORT0_RX 16 /*DMA1 Interrupt (SPORT0 RX) */
-#define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */
-#define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */
-#define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */
-#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */
-#define IRQ_UART0_RX 21 /*DMA6 Interrupt (UART RX) */
-#define IRQ_UART0_TX 22 /*DMA7 Interrupt (UART TX) */
-#define IRQ_TIMER0 23 /*Timer 0 */
-#define IRQ_TIMER1 24 /*Timer 1 */
-#define IRQ_TIMER2 25 /*Timer 2 */
-#define IRQ_PROG_INTA 26 /*Programmable Flags A (8) */
-#define IRQ_PROG_INTB 27 /*Programmable Flags B (8) */
-#define IRQ_MEM_DMA0 28 /*DMA8/9 Interrupt (Memory DMA Stream 0) */
-#define IRQ_MEM_DMA1 29 /*DMA10/11 Interrupt (Memory DMA Stream 1) */
-#define IRQ_WATCH 30 /*Watch Dog Timer */
+#define SYS_IRQS 31
#define IRQ_PF0 33
#define IRQ_PF1 34
#define GPIO_IRQ_BASE IRQ_PF0
#define NR_MACH_IRQS (IRQ_PF15 + 1)
-#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
-
-#define IVG7 7
-#define IVG8 8
-#define IVG9 9
-#define IVG10 10
-#define IVG11 11
-#define IVG12 12
-#define IVG13 13
-#define IVG14 14
-#define IVG15 15
-/* IAR0 BIT FIELDS*/
-#define RTC_ERROR_POS 28
-#define UART_ERROR_POS 24
-#define SPORT1_ERROR_POS 20
-#define SPI_ERROR_POS 16
-#define SPORT0_ERROR_POS 12
-#define PPI_ERROR_POS 8
-#define DMA_ERROR_POS 4
-#define PLLWAKE_ERROR_POS 0
+/* IAR0 BIT FIELDS */
+#define RTC_ERROR_POS 28
+#define UART_ERROR_POS 24
+#define SPORT1_ERROR_POS 20
+#define SPI_ERROR_POS 16
+#define SPORT0_ERROR_POS 12
+#define PPI_ERROR_POS 8
+#define DMA_ERROR_POS 4
+#define PLLWAKE_ERROR_POS 0
-/* IAR1 BIT FIELDS*/
-#define DMA7_UARTTX_POS 28
-#define DMA6_UARTRX_POS 24
-#define DMA5_SPI_POS 20
-#define DMA4_SPORT1TX_POS 16
-#define DMA3_SPORT1RX_POS 12
-#define DMA2_SPORT0TX_POS 8
-#define DMA1_SPORT0RX_POS 4
-#define DMA0_PPI_POS 0
+/* IAR1 BIT FIELDS */
+#define DMA7_UARTTX_POS 28
+#define DMA6_UARTRX_POS 24
+#define DMA5_SPI_POS 20
+#define DMA4_SPORT1TX_POS 16
+#define DMA3_SPORT1RX_POS 12
+#define DMA2_SPORT0TX_POS 8
+#define DMA1_SPORT0RX_POS 4
+#define DMA0_PPI_POS 0
-/* IAR2 BIT FIELDS*/
-#define WDTIMER_POS 28
-#define MEMDMA1_POS 24
-#define MEMDMA0_POS 20
-#define PFB_POS 16
-#define PFA_POS 12
-#define TIMER2_POS 8
-#define TIMER1_POS 4
-#define TIMER0_POS 0
+/* IAR2 BIT FIELDS */
+#define WDTIMER_POS 28
+#define MEMDMA1_POS 24
+#define MEMDMA0_POS 20
+#define PFB_POS 16
+#define PFA_POS 12
+#define TIMER2_POS 8
+#define TIMER1_POS 4
+#define TIMER0_POS 0
-#endif /* _BF533_IRQ_H_ */
+#endif
#include <asm/reboot.h>
#include <asm/portmux.h>
#include <asm/dpmc.h>
+#include <asm/bfin_sport.h>
#ifdef CONFIG_REGULATOR_FIXED_VOLTAGE
#include <linux/regulator/fixed.h>
#endif
},
};
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
+ defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) || \
+ defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+
+#define SPORT_REQ(x) \
+ [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \
+ P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0}
+
+static const u16 bfin_snd_pin[][7] = {
+ SPORT_REQ(0),
+ SPORT_REQ(1),
+};
+
+static struct bfin_snd_platform_data bfin_snd_data[] = {
+ {
+ .pin_req = &bfin_snd_pin[0][0],
+ },
+ {
+ .pin_req = &bfin_snd_pin[1][0],
+ },
+};
+
+#define BFIN_SND_RES(x) \
+ [x] = { \
+ { \
+ .start = SPORT##x##_TCR1, \
+ .end = SPORT##x##_TCR1, \
+ .flags = IORESOURCE_MEM \
+ }, \
+ { \
+ .start = CH_SPORT##x##_RX, \
+ .end = CH_SPORT##x##_RX, \
+ .flags = IORESOURCE_DMA, \
+ }, \
+ { \
+ .start = CH_SPORT##x##_TX, \
+ .end = CH_SPORT##x##_TX, \
+ .flags = IORESOURCE_DMA, \
+ }, \
+ { \
+ .start = IRQ_SPORT##x##_ERROR, \
+ .end = IRQ_SPORT##x##_ERROR, \
+ .flags = IORESOURCE_IRQ, \
+ } \
+ }
+
+static struct resource bfin_snd_resources[][4] = {
+ BFIN_SND_RES(0),
+ BFIN_SND_RES(1),
+};
+
+static struct platform_device bfin_pcm = {
+ .name = "bfin-pcm-audio",
+ .id = -1,
+};
+#endif
+
+#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE)
+static struct platform_device bfin_ad73311_codec_device = {
+ .name = "ad73311",
+ .id = -1,
+};
+#endif
+
+#if defined(CONFIG_SND_BF5XX_SOC_I2S) || defined(CONFIG_SND_BF5XX_SOC_I2S_MODULE)
static struct platform_device bfin_i2s = {
.name = "bfin-i2s",
.id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
+ .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
+ .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
+ .dev = {
+ .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
+ },
};
#endif
-#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
+#if defined(CONFIG_SND_BF5XX_SOC_TDM) || defined(CONFIG_SND_BF5XX_SOC_TDM_MODULE)
static struct platform_device bfin_tdm = {
.name = "bfin-tdm",
.id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
+ .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
+ .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
+ .dev = {
+ .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
+ },
};
#endif
-#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+#if defined(CONFIG_SND_BF5XX_SOC_AC97) || defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE)
static struct platform_device bfin_ac97 = {
.name = "bfin-ac97",
.id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
+ .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
+ .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
+ .dev = {
+ .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
+ },
};
#endif
&stamp_flash_device,
#endif
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
+ defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) || \
+ defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+ &bfin_pcm,
+#endif
+
+#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE)
+ &bfin_ad73311_codec_device,
+#endif
+
+#if defined(CONFIG_SND_BF5XX_SOC_I2S) || defined(CONFIG_SND_BF5XX_SOC_I2S_MODULE)
&bfin_i2s,
#endif
-#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
+#if defined(CONFIG_SND_BF5XX_SOC_TDM) || defined(CONFIG_SND_BF5XX_SOC_TDM_MODULE)
&bfin_tdm,
#endif
-#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+#if defined(CONFIG_SND_BF5XX_SOC_AC97) || defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE)
&bfin_ac97,
#endif
+
#if defined(CONFIG_REGULATOR_AD5398) || defined(CONFIG_REGULATOR_AD5398_MODULE)
#if defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER) || \
defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER_MODULE)
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
- * - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
+ * - Revision E, 05/25/2010; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define ANOMALY_05000443 (1)
/* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1)
+/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
+#define ANOMALY_05000462 (1)
/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
#define ANOMALY_05000473 (1)
/* Possible Lockup Condition whem Modifying PLL from External Memory */
#define ANOMALY_05000475 (1)
/* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1)
+/* Multiple Simultaneous Urgent DMA Requests May Cause DMA System Instability */
+#define ANOMALY_05000480 (__SILICON_REVISION__ < 3)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000481 (1)
/* IFLUSH sucks at life */
#define ANOMALY_05000363 (0)
#define ANOMALY_05000364 (0)
#define ANOMALY_05000380 (0)
+#define ANOMALY_05000383 (0)
#define ANOMALY_05000386 (1)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000430 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
+#define ANOMALY_05000440 (0)
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0)
#ifndef _BF537_IRQ_H_
#define _BF537_IRQ_H_
-/*
- * Interrupt source definitions
- * Event Source Core Event Name
- * Core Emulation **
- * Events (highest priority) EMU 0
- * Reset RST 1
- * NMI NMI 2
- * Exception EVX 3
- * Reserved -- 4
- * Hardware Error IVHW 5
- * Core Timer IVTMR 6
- * .....
- *
- * Softirq IVG14
- * System Call --
- * (lowest priority) IVG15
- */
-
-#define SYS_IRQS 39
-#define NR_PERI_INTS 32
-
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU 0 /*Emulation */
-#define IRQ_RST 1 /*reset */
-#define IRQ_NMI 2 /*Non Maskable */
-#define IRQ_EVX 3 /*Exception */
-#define IRQ_UNUSED 4 /*- unused interrupt*/
-#define IRQ_HWERR 5 /*Hardware Error */
-#define IRQ_CORETMR 6 /*Core timer */
-
-#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */
-#define IRQ_DMA_ERROR 8 /*DMA Error (general) */
-#define IRQ_GENERIC_ERROR 9 /*GENERIC Error Interrupt */
-#define IRQ_RTC 10 /*RTC Interrupt */
-#define IRQ_PPI 11 /*DMA0 Interrupt (PPI) */
-#define IRQ_SPORT0_RX 12 /*DMA3 Interrupt (SPORT0 RX) */
-#define IRQ_SPORT0_TX 13 /*DMA4 Interrupt (SPORT0 TX) */
-#define IRQ_SPORT1_RX 14 /*DMA5 Interrupt (SPORT1 RX) */
-#define IRQ_SPORT1_TX 15 /*DMA6 Interrupt (SPORT1 TX) */
-#define IRQ_TWI 16 /*TWI Interrupt */
-#define IRQ_SPI 17 /*DMA7 Interrupt (SPI) */
-#define IRQ_UART0_RX 18 /*DMA8 Interrupt (UART0 RX) */
-#define IRQ_UART0_TX 19 /*DMA9 Interrupt (UART0 TX) */
-#define IRQ_UART1_RX 20 /*DMA10 Interrupt (UART1 RX) */
-#define IRQ_UART1_TX 21 /*DMA11 Interrupt (UART1 TX) */
-#define IRQ_CAN_RX 22 /*CAN Receive Interrupt */
-#define IRQ_CAN_TX 23 /*CAN Transmit Interrupt */
-#define IRQ_MAC_RX 24 /*DMA1 (Ethernet RX) Interrupt */
-#define IRQ_MAC_TX 25 /*DMA2 (Ethernet TX) Interrupt */
-#define IRQ_TIMER0 26 /*Timer 0 */
-#define IRQ_TIMER1 27 /*Timer 1 */
-#define IRQ_TIMER2 28 /*Timer 2 */
-#define IRQ_TIMER3 29 /*Timer 3 */
-#define IRQ_TIMER4 30 /*Timer 4 */
-#define IRQ_TIMER5 31 /*Timer 5 */
-#define IRQ_TIMER6 32 /*Timer 6 */
-#define IRQ_TIMER7 33 /*Timer 7 */
-#define IRQ_PROG_INTA 34 /* PF Ports F&G (PF15:0) Interrupt A */
-#define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */
-#define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */
-#define IRQ_MEM_DMA1 37 /*(Memory DMA Stream 1) */
-#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */
-#define IRQ_WATCH 38 /*Watch Dog Timer */
-
-#define IRQ_PPI_ERROR 42 /*PPI Error Interrupt */
-#define IRQ_CAN_ERROR 43 /*CAN Error Interrupt */
-#define IRQ_MAC_ERROR 44 /*MAC Status/Error Interrupt */
-#define IRQ_SPORT0_ERROR 45 /*SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERROR 46 /*SPORT1 Error Interrupt */
-#define IRQ_SPI_ERROR 47 /*SPI Error Interrupt */
-#define IRQ_UART0_ERROR 48 /*UART Error Interrupt */
-#define IRQ_UART1_ERROR 49 /*UART Error Interrupt */
-
-#define IRQ_PF0 50
-#define IRQ_PF1 51
-#define IRQ_PF2 52
-#define IRQ_PF3 53
-#define IRQ_PF4 54
-#define IRQ_PF5 55
-#define IRQ_PF6 56
-#define IRQ_PF7 57
-#define IRQ_PF8 58
-#define IRQ_PF9 59
-#define IRQ_PF10 60
-#define IRQ_PF11 61
-#define IRQ_PF12 62
-#define IRQ_PF13 63
-#define IRQ_PF14 64
-#define IRQ_PF15 65
-
-#define IRQ_PG0 66
-#define IRQ_PG1 67
-#define IRQ_PG2 68
-#define IRQ_PG3 69
-#define IRQ_PG4 70
-#define IRQ_PG5 71
-#define IRQ_PG6 72
-#define IRQ_PG7 73
-#define IRQ_PG8 74
-#define IRQ_PG9 75
-#define IRQ_PG10 76
-#define IRQ_PG11 77
-#define IRQ_PG12 78
-#define IRQ_PG13 79
-#define IRQ_PG14 80
-#define IRQ_PG15 81
-
-#define IRQ_PH0 82
-#define IRQ_PH1 83
-#define IRQ_PH2 84
-#define IRQ_PH3 85
-#define IRQ_PH4 86
-#define IRQ_PH5 87
-#define IRQ_PH6 88
-#define IRQ_PH7 89
-#define IRQ_PH8 90
-#define IRQ_PH9 91
-#define IRQ_PH10 92
-#define IRQ_PH11 93
-#define IRQ_PH12 94
-#define IRQ_PH13 95
-#define IRQ_PH14 96
-#define IRQ_PH15 97
-
-#define GPIO_IRQ_BASE IRQ_PF0
-
-#define IRQ_MAC_PHYINT 98 /* PHY_INT Interrupt */
-#define IRQ_MAC_MMCINT 99 /* MMC Counter Interrupt */
-#define IRQ_MAC_RXFSINT 100 /* RX Frame-Status Interrupt */
-#define IRQ_MAC_TXFSINT 101 /* TX Frame-Status Interrupt */
-#define IRQ_MAC_WAKEDET 102 /* Wake-Up Interrupt */
-#define IRQ_MAC_RXDMAERR 103 /* RX DMA Direction Error Interrupt */
-#define IRQ_MAC_TXDMAERR 104 /* TX DMA Direction Error Interrupt */
-#define IRQ_MAC_STMDONE 105 /* Station Mgt. Transfer Done Interrupt */
-
-#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
-#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
-
-#define IVG7 7
-#define IVG8 8
-#define IVG9 9
-#define IVG10 10
-#define IVG11 11
-#define IVG12 12
-#define IVG13 13
-#define IVG14 14
-#define IVG15 15
-
-/* IAR0 BIT FIELDS*/
-#define IRQ_PLL_WAKEUP_POS 0
-#define IRQ_DMA_ERROR_POS 4
-#define IRQ_ERROR_POS 8
-#define IRQ_RTC_POS 12
-#define IRQ_PPI_POS 16
-#define IRQ_SPORT0_RX_POS 20
-#define IRQ_SPORT0_TX_POS 24
-#define IRQ_SPORT1_RX_POS 28
-
-/* IAR1 BIT FIELDS*/
-#define IRQ_SPORT1_TX_POS 0
-#define IRQ_TWI_POS 4
-#define IRQ_SPI_POS 8
-#define IRQ_UART0_RX_POS 12
-#define IRQ_UART0_TX_POS 16
-#define IRQ_UART1_RX_POS 20
-#define IRQ_UART1_TX_POS 24
-#define IRQ_CAN_RX_POS 28
-
-/* IAR2 BIT FIELDS*/
-#define IRQ_CAN_TX_POS 0
-#define IRQ_MAC_RX_POS 4
-#define IRQ_MAC_TX_POS 8
-#define IRQ_TIMER0_POS 12
-#define IRQ_TIMER1_POS 16
-#define IRQ_TIMER2_POS 20
-#define IRQ_TIMER3_POS 24
-#define IRQ_TIMER4_POS 28
-
-/* IAR3 BIT FIELDS*/
-#define IRQ_TIMER5_POS 0
-#define IRQ_TIMER6_POS 4
-#define IRQ_TIMER7_POS 8
-#define IRQ_PROG_INTA_POS 12
-#define IRQ_PORTG_INTB_POS 16
-#define IRQ_MEM_DMA0_POS 20
-#define IRQ_MEM_DMA1_POS 24
-#define IRQ_WATCH_POS 28
-
-#endif /* _BF537_IRQ_H_ */
+#include <mach-common/irq.h>
+
+#define NR_PERI_INTS 32
+
+#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
+#define IRQ_DMA_ERROR BFIN_IRQ(1) /* DMA Error (general) */
+#define IRQ_GENERIC_ERROR BFIN_IRQ(2) /* GENERIC Error Interrupt */
+#define IRQ_RTC BFIN_IRQ(3) /* RTC Interrupt */
+#define IRQ_PPI BFIN_IRQ(4) /* DMA0 Interrupt (PPI) */
+#define IRQ_SPORT0_RX BFIN_IRQ(5) /* DMA3 Interrupt (SPORT0 RX) */
+#define IRQ_SPORT0_TX BFIN_IRQ(6) /* DMA4 Interrupt (SPORT0 TX) */
+#define IRQ_SPORT1_RX BFIN_IRQ(7) /* DMA5 Interrupt (SPORT1 RX) */
+#define IRQ_SPORT1_TX BFIN_IRQ(8) /* DMA6 Interrupt (SPORT1 TX) */
+#define IRQ_TWI BFIN_IRQ(9) /* TWI Interrupt */
+#define IRQ_SPI BFIN_IRQ(10) /* DMA7 Interrupt (SPI) */
+#define IRQ_UART0_RX BFIN_IRQ(11) /* DMA8 Interrupt (UART0 RX) */
+#define IRQ_UART0_TX BFIN_IRQ(12) /* DMA9 Interrupt (UART0 TX) */
+#define IRQ_UART1_RX BFIN_IRQ(13) /* DMA10 Interrupt (UART1 RX) */
+#define IRQ_UART1_TX BFIN_IRQ(14) /* DMA11 Interrupt (UART1 TX) */
+#define IRQ_CAN_RX BFIN_IRQ(15) /* CAN Receive Interrupt */
+#define IRQ_CAN_TX BFIN_IRQ(16) /* CAN Transmit Interrupt */
+#define IRQ_PH_INTA_MAC_RX BFIN_IRQ(17) /* Port H Interrupt A & DMA1 Interrupt (Ethernet RX) */
+#define IRQ_PH_INTB_MAC_TX BFIN_IRQ(18) /* Port H Interrupt B & DMA2 Interrupt (Ethernet TX) */
+#define IRQ_TIMER0 BFIN_IRQ(19) /* Timer 0 */
+#define IRQ_TIMER1 BFIN_IRQ(20) /* Timer 1 */
+#define IRQ_TIMER2 BFIN_IRQ(21) /* Timer 2 */
+#define IRQ_TIMER3 BFIN_IRQ(22) /* Timer 3 */
+#define IRQ_TIMER4 BFIN_IRQ(23) /* Timer 4 */
+#define IRQ_TIMER5 BFIN_IRQ(24) /* Timer 5 */
+#define IRQ_TIMER6 BFIN_IRQ(25) /* Timer 6 */
+#define IRQ_TIMER7 BFIN_IRQ(26) /* Timer 7 */
+#define IRQ_PF_INTA_PG_INTA BFIN_IRQ(27) /* Ports F&G Interrupt A */
+#define IRQ_PORTG_INTB BFIN_IRQ(28) /* Port G Interrupt B */
+#define IRQ_MEM_DMA0 BFIN_IRQ(29) /* (Memory DMA Stream 0) */
+#define IRQ_MEM_DMA1 BFIN_IRQ(30) /* (Memory DMA Stream 1) */
+#define IRQ_PF_INTB_WATCH BFIN_IRQ(31) /* Watchdog & Port F Interrupt B */
+
+#define SYS_IRQS 39
+
+#define IRQ_PPI_ERROR 42 /* PPI Error Interrupt */
+#define IRQ_CAN_ERROR 43 /* CAN Error Interrupt */
+#define IRQ_MAC_ERROR 44 /* MAC Status/Error Interrupt */
+#define IRQ_SPORT0_ERROR 45 /* SPORT0 Error Interrupt */
+#define IRQ_SPORT1_ERROR 46 /* SPORT1 Error Interrupt */
+#define IRQ_SPI_ERROR 47 /* SPI Error Interrupt */
+#define IRQ_UART0_ERROR 48 /* UART Error Interrupt */
+#define IRQ_UART1_ERROR 49 /* UART Error Interrupt */
+
+#define IRQ_PF0 50
+#define IRQ_PF1 51
+#define IRQ_PF2 52
+#define IRQ_PF3 53
+#define IRQ_PF4 54
+#define IRQ_PF5 55
+#define IRQ_PF6 56
+#define IRQ_PF7 57
+#define IRQ_PF8 58
+#define IRQ_PF9 59
+#define IRQ_PF10 60
+#define IRQ_PF11 61
+#define IRQ_PF12 62
+#define IRQ_PF13 63
+#define IRQ_PF14 64
+#define IRQ_PF15 65
+
+#define IRQ_PG0 66
+#define IRQ_PG1 67
+#define IRQ_PG2 68
+#define IRQ_PG3 69
+#define IRQ_PG4 70
+#define IRQ_PG5 71
+#define IRQ_PG6 72
+#define IRQ_PG7 73
+#define IRQ_PG8 74
+#define IRQ_PG9 75
+#define IRQ_PG10 76
+#define IRQ_PG11 77
+#define IRQ_PG12 78
+#define IRQ_PG13 79
+#define IRQ_PG14 80
+#define IRQ_PG15 81
+
+#define IRQ_PH0 82
+#define IRQ_PH1 83
+#define IRQ_PH2 84
+#define IRQ_PH3 85
+#define IRQ_PH4 86
+#define IRQ_PH5 87
+#define IRQ_PH6 88
+#define IRQ_PH7 89
+#define IRQ_PH8 90
+#define IRQ_PH9 91
+#define IRQ_PH10 92
+#define IRQ_PH11 93
+#define IRQ_PH12 94
+#define IRQ_PH13 95
+#define IRQ_PH14 96
+#define IRQ_PH15 97
+
+#define GPIO_IRQ_BASE IRQ_PF0
+
+#define IRQ_MAC_PHYINT 98 /* PHY_INT Interrupt */
+#define IRQ_MAC_MMCINT 99 /* MMC Counter Interrupt */
+#define IRQ_MAC_RXFSINT 100 /* RX Frame-Status Interrupt */
+#define IRQ_MAC_TXFSINT 101 /* TX Frame-Status Interrupt */
+#define IRQ_MAC_WAKEDET 102 /* Wake-Up Interrupt */
+#define IRQ_MAC_RXDMAERR 103 /* RX DMA Direction Error Interrupt */
+#define IRQ_MAC_TXDMAERR 104 /* TX DMA Direction Error Interrupt */
+#define IRQ_MAC_STMDONE 105 /* Station Mgt. Transfer Done Interrupt */
+
+#define IRQ_MAC_RX 106 /* DMA1 Interrupt (Ethernet RX) */
+#define IRQ_PORTH_INTA 107 /* Port H Interrupt A */
+
+#if 0 /* No Interrupt B support (yet) */
+#define IRQ_MAC_TX 108 /* DMA2 Interrupt (Ethernet TX) */
+#define IRQ_PORTH_INTB 109 /* Port H Interrupt B */
+#else
+#define IRQ_MAC_TX IRQ_PH_INTB_MAC_TX
+#endif
+
+#define IRQ_PORTF_INTA 110 /* Port F Interrupt A */
+#define IRQ_PORTG_INTA 111 /* Port G Interrupt A */
+
+#if 0 /* No Interrupt B support (yet) */
+#define IRQ_WATCH 112 /* Watchdog Timer */
+#define IRQ_PORTF_INTB 113 /* Port F Interrupt B */
+#else
+#define IRQ_WATCH IRQ_PF_INTB_WATCH
+#endif
+
+#define NR_MACH_IRQS (113 + 1)
+
+/* IAR0 BIT FIELDS */
+#define IRQ_PLL_WAKEUP_POS 0
+#define IRQ_DMA_ERROR_POS 4
+#define IRQ_ERROR_POS 8
+#define IRQ_RTC_POS 12
+#define IRQ_PPI_POS 16
+#define IRQ_SPORT0_RX_POS 20
+#define IRQ_SPORT0_TX_POS 24
+#define IRQ_SPORT1_RX_POS 28
+
+/* IAR1 BIT FIELDS */
+#define IRQ_SPORT1_TX_POS 0
+#define IRQ_TWI_POS 4
+#define IRQ_SPI_POS 8
+#define IRQ_UART0_RX_POS 12
+#define IRQ_UART0_TX_POS 16
+#define IRQ_UART1_RX_POS 20
+#define IRQ_UART1_TX_POS 24
+#define IRQ_CAN_RX_POS 28
+
+/* IAR2 BIT FIELDS */
+#define IRQ_CAN_TX_POS 0
+#define IRQ_MAC_RX_POS 4
+#define IRQ_MAC_TX_POS 8
+#define IRQ_TIMER0_POS 12
+#define IRQ_TIMER1_POS 16
+#define IRQ_TIMER2_POS 20
+#define IRQ_TIMER3_POS 24
+#define IRQ_TIMER4_POS 28
+
+/* IAR3 BIT FIELDS */
+#define IRQ_TIMER5_POS 0
+#define IRQ_TIMER6_POS 4
+#define IRQ_TIMER7_POS 8
+#define IRQ_PROG_INTA_POS 12
+#define IRQ_PORTG_INTB_POS 16
+#define IRQ_MEM_DMA0_POS 20
+#define IRQ_MEM_DMA1_POS 24
+#define IRQ_WATCH_POS 28
+
+#define init_mach_irq init_mach_irq
+
+#endif
#include <linux/irq.h>
#include <asm/blackfin.h>
+#include <asm/irq_handler.h>
+#include <asm/bfin5xx_spi.h>
+#include <asm/bfin_sport.h>
+#include <asm/bfin_can.h>
+#include <asm/bfin_dma.h>
+#include <asm/dpmc.h>
+
void __init program_IAR(void)
{
/* Program the IAR0 Register with the configured priority */
SSYNC();
}
+
+#define SPI_ERR_MASK (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */
+#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORT_STAT */
+#define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */
+#define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
+#define UART_ERR_MASK (0x6) /* UART_IIR */
+#define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */
+
+static int error_int_mask;
+
+static void bf537_generic_error_mask_irq(struct irq_data *d)
+{
+ error_int_mask &= ~(1L << (d->irq - IRQ_PPI_ERROR));
+ if (!error_int_mask)
+ bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
+}
+
+static void bf537_generic_error_unmask_irq(struct irq_data *d)
+{
+ bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
+ error_int_mask |= 1L << (d->irq - IRQ_PPI_ERROR);
+}
+
+static struct irq_chip bf537_generic_error_irqchip = {
+ .name = "ERROR",
+ .irq_ack = bfin_ack_noop,
+ .irq_mask_ack = bf537_generic_error_mask_irq,
+ .irq_mask = bf537_generic_error_mask_irq,
+ .irq_unmask = bf537_generic_error_unmask_irq,
+};
+
+static void bf537_demux_error_irq(unsigned int int_err_irq,
+ struct irq_desc *inta_desc)
+{
+ int irq = 0;
+
+#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
+ if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
+ irq = IRQ_MAC_ERROR;
+ else
+#endif
+ if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
+ irq = IRQ_SPORT0_ERROR;
+ else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
+ irq = IRQ_SPORT1_ERROR;
+ else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
+ irq = IRQ_PPI_ERROR;
+ else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
+ irq = IRQ_CAN_ERROR;
+ else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
+ irq = IRQ_SPI_ERROR;
+ else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
+ irq = IRQ_UART0_ERROR;
+ else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
+ irq = IRQ_UART1_ERROR;
+
+ if (irq) {
+ if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
+ bfin_handle_irq(irq);
+ else {
+
+ switch (irq) {
+ case IRQ_PPI_ERROR:
+ bfin_write_PPI_STATUS(PPI_ERR_MASK);
+ break;
+#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
+ case IRQ_MAC_ERROR:
+ bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
+ break;
+#endif
+ case IRQ_SPORT0_ERROR:
+ bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
+ break;
+
+ case IRQ_SPORT1_ERROR:
+ bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
+ break;
+
+ case IRQ_CAN_ERROR:
+ bfin_write_CAN_GIS(CAN_ERR_MASK);
+ break;
+
+ case IRQ_SPI_ERROR:
+ bfin_write_SPI_STAT(SPI_ERR_MASK);
+ break;
+
+ default:
+ break;
+ }
+
+ pr_debug("IRQ %d:"
+ " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
+ irq);
+ }
+ } else
+ pr_err("%s: IRQ ?: PERIPHERAL ERROR INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
+ __func__);
+
+}
+
+#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+static int mac_rx_int_mask;
+
+static void bf537_mac_rx_mask_irq(struct irq_data *d)
+{
+ mac_rx_int_mask &= ~(1L << (d->irq - IRQ_MAC_RX));
+ if (!mac_rx_int_mask)
+ bfin_internal_mask_irq(IRQ_PH_INTA_MAC_RX);
+}
+
+static void bf537_mac_rx_unmask_irq(struct irq_data *d)
+{
+ bfin_internal_unmask_irq(IRQ_PH_INTA_MAC_RX);
+ mac_rx_int_mask |= 1L << (d->irq - IRQ_MAC_RX);
+}
+
+static struct irq_chip bf537_mac_rx_irqchip = {
+ .name = "ERROR",
+ .irq_ack = bfin_ack_noop,
+ .irq_mask_ack = bf537_mac_rx_mask_irq,
+ .irq_mask = bf537_mac_rx_mask_irq,
+ .irq_unmask = bf537_mac_rx_unmask_irq,
+};
+
+static void bf537_demux_mac_rx_irq(unsigned int int_irq,
+ struct irq_desc *desc)
+{
+ if (bfin_read_DMA1_IRQ_STATUS() & (DMA_DONE | DMA_ERR))
+ bfin_handle_irq(IRQ_MAC_RX);
+ else
+ bfin_demux_gpio_irq(int_irq, desc);
+}
+#endif
+
+void __init init_mach_irq(void)
+{
+ int irq;
+
+#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
+ /* Clear EMAC Interrupt Status bits so we can demux it later */
+ bfin_write_EMAC_SYSTAT(-1);
+#endif
+
+ irq_set_chained_handler(IRQ_GENERIC_ERROR, bf537_demux_error_irq);
+ for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
+ irq_set_chip_and_handler(irq, &bf537_generic_error_irqchip,
+ handle_level_irq);
+
+#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+ irq_set_chained_handler(IRQ_PH_INTA_MAC_RX, bf537_demux_mac_rx_irq);
+ irq_set_chip_and_handler(IRQ_MAC_RX, &bf537_mac_rx_irqchip, handle_level_irq);
+ irq_set_chip_and_handler(IRQ_PORTH_INTA, &bf537_mac_rx_irqchip, handle_level_irq);
+
+ irq_set_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
+#endif
+}
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
- * - Revision H, 07/10/2009; ADSP-BF538/BF538F Blackfin Processor Anomaly List
- * - Revision M, 07/10/2009; ADSP-BF539/BF539F Blackfin Processor Anomaly List
+ * - Revision I, 05/25/2010; ADSP-BF538/BF538F Blackfin Processor Anomaly List
+ * - Revision N, 05/25/2010; ADSP-BF539/BF539F Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define ANOMALY_05000363 (0)
#define ANOMALY_05000364 (0)
#define ANOMALY_05000380 (0)
+#define ANOMALY_05000383 (0)
#define ANOMALY_05000386 (1)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000430 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
+#define ANOMALY_05000440 (0)
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0)
#define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0)
+#define ANOMALY_05000480 (0)
#define ANOMALY_05000485 (0)
#endif
#ifndef _BF538_IRQ_H_
#define _BF538_IRQ_H_
-/*
- * Interrupt source definitions
- Event Source Core Event Name
- Core Emulation **
- Events (highest priority) EMU 0
- Reset RST 1
- NMI NMI 2
- Exception EVX 3
- Reserved -- 4
- Hardware Error IVHW 5
- Core Timer IVTMR 6 *
-
- .....
-
- Software Interrupt 1 IVG14 31
- Software Interrupt 2 --
- (lowest priority) IVG15 32 *
-*/
-
-#define NR_PERI_INTS (2 * 32)
-
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU 0 /* Emulation */
-#define IRQ_RST 1 /* reset */
-#define IRQ_NMI 2 /* Non Maskable */
-#define IRQ_EVX 3 /* Exception */
-#define IRQ_UNUSED 4 /* - unused interrupt */
-#define IRQ_HWERR 5 /* Hardware Error */
-#define IRQ_CORETMR 6 /* Core timer */
-
-#define BFIN_IRQ(x) ((x) + 7)
+#include <mach-common/irq.h>
+
+#define NR_PERI_INTS (2 * 32)
#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
#define SYS_IRQS BFIN_IRQ(63) /* 70 */
-#define IRQ_PF0 71
-#define IRQ_PF1 72
-#define IRQ_PF2 73
-#define IRQ_PF3 74
-#define IRQ_PF4 75
-#define IRQ_PF5 76
-#define IRQ_PF6 77
-#define IRQ_PF7 78
-#define IRQ_PF8 79
-#define IRQ_PF9 80
-#define IRQ_PF10 81
-#define IRQ_PF11 82
-#define IRQ_PF12 83
-#define IRQ_PF13 84
-#define IRQ_PF14 85
-#define IRQ_PF15 86
-
-#define GPIO_IRQ_BASE IRQ_PF0
-
-#define NR_MACH_IRQS (IRQ_PF15 + 1)
-#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
-
-#define IVG7 7
-#define IVG8 8
-#define IVG9 9
-#define IVG10 10
-#define IVG11 11
-#define IVG12 12
-#define IVG13 13
-#define IVG14 14
-#define IVG15 15
+#define IRQ_PF0 71
+#define IRQ_PF1 72
+#define IRQ_PF2 73
+#define IRQ_PF3 74
+#define IRQ_PF4 75
+#define IRQ_PF5 76
+#define IRQ_PF6 77
+#define IRQ_PF7 78
+#define IRQ_PF8 79
+#define IRQ_PF9 80
+#define IRQ_PF10 81
+#define IRQ_PF11 82
+#define IRQ_PF12 83
+#define IRQ_PF13 84
+#define IRQ_PF14 85
+#define IRQ_PF15 86
+
+#define GPIO_IRQ_BASE IRQ_PF0
+
+#define NR_MACH_IRQS (IRQ_PF15 + 1)
/* IAR0 BIT FIELDS */
#define IRQ_PLL_WAKEUP_POS 0
#define IRQ_CAN_TX_POS 0
#define IRQ_MEM1_DMA0_POS 4
#define IRQ_MEM1_DMA1_POS 8
-#endif /* _BF538_IRQ_H_ */
+
+#endif
#include <asm/gpio.h>
#include <asm/nand.h>
#include <asm/dpmc.h>
+#include <asm/bfin_sport.h>
#include <asm/portmux.h>
#include <asm/bfin_sdh.h>
#include <mach/bf54x_keys.h>
.offset = MTDPART_OFS_APPEND,
}, {
.name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
+ .size = 0x1000000 - 0x80000 - 0x400000 - 0x8000 * 4,
+ .offset = MTDPART_OFS_APPEND,
+ }, {
+ .name = "config(nor)",
+ .size = 0x8000 * 3,
+ .offset = MTDPART_OFS_APPEND,
+ }, {
+ .name = "u-boot env(nor)",
+ .size = 0x8000,
.offset = MTDPART_OFS_APPEND,
}
};
},
};
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
+ defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) || \
+ defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+
+#define SPORT_REQ(x) \
+ [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \
+ P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0}
+
+static const u16 bfin_snd_pin[][7] = {
+ SPORT_REQ(0),
+ SPORT_REQ(1),
+};
+
+static struct bfin_snd_platform_data bfin_snd_data[] = {
+ {
+ .pin_req = &bfin_snd_pin[0][0],
+ },
+ {
+ .pin_req = &bfin_snd_pin[1][0],
+ },
+};
+
+#define BFIN_SND_RES(x) \
+ [x] = { \
+ { \
+ .start = SPORT##x##_TCR1, \
+ .end = SPORT##x##_TCR1, \
+ .flags = IORESOURCE_MEM \
+ }, \
+ { \
+ .start = CH_SPORT##x##_RX, \
+ .end = CH_SPORT##x##_RX, \
+ .flags = IORESOURCE_DMA, \
+ }, \
+ { \
+ .start = CH_SPORT##x##_TX, \
+ .end = CH_SPORT##x##_TX, \
+ .flags = IORESOURCE_DMA, \
+ }, \
+ { \
+ .start = IRQ_SPORT##x##_ERROR, \
+ .end = IRQ_SPORT##x##_ERROR, \
+ .flags = IORESOURCE_IRQ, \
+ } \
+ }
+
+static struct resource bfin_snd_resources[][4] = {
+ BFIN_SND_RES(0),
+ BFIN_SND_RES(1),
+};
+
+static struct platform_device bfin_pcm = {
+ .name = "bfin-pcm-audio",
+ .id = -1,
+};
+#endif
+
+#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE)
+static struct platform_device bfin_ad73311_codec_device = {
+ .name = "ad73311",
+ .id = -1,
+};
+#endif
+
+#if defined(CONFIG_SND_BF5XX_SOC_AD1980) || defined(CONFIG_SND_BF5XX_SOC_AD1980_MODULE)
+static struct platform_device bfin_ad1980_codec_device = {
+ .name = "ad1980",
+ .id = -1,
+};
+#endif
+
+#if defined(CONFIG_SND_BF5XX_SOC_I2S) || defined(CONFIG_SND_BF5XX_SOC_I2S_MODULE)
static struct platform_device bfin_i2s = {
.name = "bfin-i2s",
.id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
+ .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
+ .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
+ .dev = {
+ .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
+ },
};
#endif
-#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
+#if defined(CONFIG_SND_BF5XX_SOC_TDM) || defined(CONFIG_SND_BF5XX_SOC_TDM_MODULE)
static struct platform_device bfin_tdm = {
.name = "bfin-tdm",
.id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
+ .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
+ .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
+ .dev = {
+ .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
+ },
};
#endif
-#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+#if defined(CONFIG_SND_BF5XX_SOC_AC97) || defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE)
static struct platform_device bfin_ac97 = {
.name = "bfin-ac97",
.id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
+ .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
+ .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
+ .dev = {
+ .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
+ },
};
#endif
&ezkit_flash_device,
#endif
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
+ defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) || \
+ defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+ &bfin_pcm,
+#endif
+
+#if defined(CONFIG_SND_BF5XX_SOC_AD1980) || defined(CONFIG_SND_BF5XX_SOC_AD1980_MODULE)
+ &bfin_ad1980_codec_device,
+#endif
+
#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
&bfin_i2s,
#endif
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
- * - Revision I, 07/23/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
+ * - Revision J, 06/03/2010; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define ANOMALY_05000481 (1)
/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
#define ANOMALY_05000483 (1)
+/* DDR Trim May Not Be Performed for Certain VLEV Values in OTP Page PBS00L */
+#define ANOMALY_05000484 (__SILICON_REVISION__ < 3)
/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
#define ANOMALY_05000485 (__SILICON_REVISION__ >= 2)
/* IFLUSH sucks at life */
#define ANOMALY_05000412 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
+#define ANOMALY_05000440 (0)
#define ANOMALY_05000475 (0)
+#define ANOMALY_05000480 (0)
#endif
#ifndef _BF548_IRQ_H_
#define _BF548_IRQ_H_
-/*
- * Interrupt source definitions
- Event Source Core Event Name
-Core Emulation **
-Events (highest priority) EMU 0
- Reset RST 1
- NMI NMI 2
- Exception EVX 3
- Reserved -- 4
- Hardware Error IVHW 5
- Core Timer IVTMR 6 *
-
-.....
-
- Software Interrupt 1 IVG14 31
- Software Interrupt 2 --
- (lowest priority) IVG15 32 *
- */
-
-#define NR_PERI_INTS (32 * 3)
-
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU 0 /* Emulation */
-#define IRQ_RST 1 /* reset */
-#define IRQ_NMI 2 /* Non Maskable */
-#define IRQ_EVX 3 /* Exception */
-#define IRQ_UNUSED 4 /* - unused interrupt*/
-#define IRQ_HWERR 5 /* Hardware Error */
-#define IRQ_CORETMR 6 /* Core timer */
+#include <mach-common/irq.h>
-#define BFIN_IRQ(x) ((x) + 7)
+#define NR_PERI_INTS (3 * 32)
#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
#define IRQ_DMAC0_ERROR BFIN_IRQ(1) /* DMAC0 Status Interrupt */
#define IRQ_PJ14 BFIN_PJ_IRQ(14) /* N/A */
#define IRQ_PJ15 BFIN_PJ_IRQ(15) /* N/A */
-#define GPIO_IRQ_BASE IRQ_PA0
+#define GPIO_IRQ_BASE IRQ_PA0
-#define NR_MACH_IRQS (IRQ_PJ15 + 1)
-#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
+#define NR_MACH_IRQS (IRQ_PJ15 + 1)
/* For compatibility reasons with existing code */
-#define IRQ_DMAC0_ERR IRQ_DMAC0_ERROR
-#define IRQ_EPPI0_ERR IRQ_EPPI0_ERROR
+#define IRQ_DMAC0_ERR IRQ_DMAC0_ERROR
+#define IRQ_EPPI0_ERR IRQ_EPPI0_ERROR
#define IRQ_SPORT0_ERR IRQ_SPORT0_ERROR
#define IRQ_SPORT1_ERR IRQ_SPORT1_ERROR
-#define IRQ_SPI0_ERR IRQ_SPI0_ERROR
-#define IRQ_UART0_ERR IRQ_UART0_ERROR
-#define IRQ_DMAC1_ERR IRQ_DMAC1_ERROR
+#define IRQ_SPI0_ERR IRQ_SPI0_ERROR
+#define IRQ_UART0_ERR IRQ_UART0_ERROR
+#define IRQ_DMAC1_ERR IRQ_DMAC1_ERROR
#define IRQ_SPORT2_ERR IRQ_SPORT2_ERROR
#define IRQ_SPORT3_ERR IRQ_SPORT3_ERROR
-#define IRQ_SPI1_ERR IRQ_SPI1_ERROR
-#define IRQ_SPI2_ERR IRQ_SPI2_ERROR
-#define IRQ_UART1_ERR IRQ_UART1_ERROR
-#define IRQ_UART2_ERR IRQ_UART2_ERROR
-#define IRQ_CAN0_ERR IRQ_CAN0_ERROR
-#define IRQ_MXVR_ERR IRQ_MXVR_ERROR
-#define IRQ_EPPI1_ERR IRQ_EPPI1_ERROR
-#define IRQ_EPPI2_ERR IRQ_EPPI2_ERROR
-#define IRQ_UART3_ERR IRQ_UART3_ERROR
-#define IRQ_HOST_ERR IRQ_HOST_ERROR
-#define IRQ_PIXC_ERR IRQ_PIXC_ERROR
-#define IRQ_NFC_ERR IRQ_NFC_ERROR
-#define IRQ_ATAPI_ERR IRQ_ATAPI_ERROR
-#define IRQ_CAN1_ERR IRQ_CAN1_ERROR
+#define IRQ_SPI1_ERR IRQ_SPI1_ERROR
+#define IRQ_SPI2_ERR IRQ_SPI2_ERROR
+#define IRQ_UART1_ERR IRQ_UART1_ERROR
+#define IRQ_UART2_ERR IRQ_UART2_ERROR
+#define IRQ_CAN0_ERR IRQ_CAN0_ERROR
+#define IRQ_MXVR_ERR IRQ_MXVR_ERROR
+#define IRQ_EPPI1_ERR IRQ_EPPI1_ERROR
+#define IRQ_EPPI2_ERR IRQ_EPPI2_ERROR
+#define IRQ_UART3_ERR IRQ_UART3_ERROR
+#define IRQ_HOST_ERR IRQ_HOST_ERROR
+#define IRQ_PIXC_ERR IRQ_PIXC_ERROR
+#define IRQ_NFC_ERR IRQ_NFC_ERROR
+#define IRQ_ATAPI_ERR IRQ_ATAPI_ERROR
+#define IRQ_CAN1_ERR IRQ_CAN1_ERROR
#define IRQ_HS_DMA_ERR IRQ_HS_DMA_ERROR
-
-#define IVG7 7
-#define IVG8 8
-#define IVG9 9
-#define IVG10 10
-#define IVG11 11
-#define IVG12 12
-#define IVG13 13
-#define IVG14 14
-#define IVG15 15
-
/* IAR0 BIT FIELDS */
#define IRQ_PLL_WAKEUP_POS 0
#define IRQ_DMAC0_ERR_POS 4
#endif
-#endif /* _BF548_IRQ_H_ */
+#endif
.offset = MTDPART_OFS_APPEND,
}, {
.name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
+ .size = 0x800000 - 0x40000 - 0x1C0000 - 0x2000 * 8,
+ .offset = MTDPART_OFS_APPEND,
+ }, {
+ .name = "config(nor)",
+ .size = 0x2000 * 7,
+ .offset = MTDPART_OFS_APPEND,
+ }, {
+ .name = "u-boot env(nor)",
+ .size = 0x2000,
.offset = MTDPART_OFS_APPEND,
}
};
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
- * - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List
+ * - Revision R, 05/25/2010; ADSP-BF561 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1)
+/* SCKELOW Feature Is Not Functional */
+#define ANOMALY_05000458 (1)
/* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1)
+/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
+#define ANOMALY_05000462 (1)
+/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
+#define ANOMALY_05000471 (1)
/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
#define ANOMALY_05000473 (1)
/* Possible Lockup Condition whem Modifying PLL from External Memory */
-#define ANOMALY_05000475 (__SILICON_REVISION__ < 4)
+#define ANOMALY_05000475 (1)
/* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000353 (1)
#define ANOMALY_05000364 (0)
#define ANOMALY_05000380 (0)
+#define ANOMALY_05000383 (0)
#define ANOMALY_05000386 (1)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000430 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
+#define ANOMALY_05000440 (0)
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0)
#define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0)
+#define ANOMALY_05000480 (0)
#define ANOMALY_05000485 (0)
#endif
#ifndef _BF561_IRQ_H_
#define _BF561_IRQ_H_
-/***********************************************************************
- * Interrupt source definitions:
- Event Source Core Event Name IRQ No
- (highest priority)
- Emulation Events EMU 0
- Reset RST 1
- NMI NMI 2
- Exception EVX 3
- Reserved -- 4
- Hardware Error IVHW 5
- Core Timer IVTMR 6 *
-
- PLL Wakeup Interrupt IVG7 7
- DMA1 Error (generic) IVG7 8
- DMA2 Error (generic) IVG7 9
- IMDMA Error (generic) IVG7 10
- PPI1 Error Interrupt IVG7 11
- PPI2 Error Interrupt IVG7 12
- SPORT0 Error Interrupt IVG7 13
- SPORT1 Error Interrupt IVG7 14
- SPI Error Interrupt IVG7 15
- UART Error Interrupt IVG7 16
- Reserved Interrupt IVG7 17
-
- DMA1 0 Interrupt(PPI1) IVG8 18
- DMA1 1 Interrupt(PPI2) IVG8 19
- DMA1 2 Interrupt IVG8 20
- DMA1 3 Interrupt IVG8 21
- DMA1 4 Interrupt IVG8 22
- DMA1 5 Interrupt IVG8 23
- DMA1 6 Interrupt IVG8 24
- DMA1 7 Interrupt IVG8 25
- DMA1 8 Interrupt IVG8 26
- DMA1 9 Interrupt IVG8 27
- DMA1 10 Interrupt IVG8 28
- DMA1 11 Interrupt IVG8 29
-
- DMA2 0 (SPORT0 RX) IVG9 30
- DMA2 1 (SPORT0 TX) IVG9 31
- DMA2 2 (SPORT1 RX) IVG9 32
- DMA2 3 (SPORT2 TX) IVG9 33
- DMA2 4 (SPI) IVG9 34
- DMA2 5 (UART RX) IVG9 35
- DMA2 6 (UART TX) IVG9 36
- DMA2 7 Interrupt IVG9 37
- DMA2 8 Interrupt IVG9 38
- DMA2 9 Interrupt IVG9 39
- DMA2 10 Interrupt IVG9 40
- DMA2 11 Interrupt IVG9 41
-
- TIMER 0 Interrupt IVG10 42
- TIMER 1 Interrupt IVG10 43
- TIMER 2 Interrupt IVG10 44
- TIMER 3 Interrupt IVG10 45
- TIMER 4 Interrupt IVG10 46
- TIMER 5 Interrupt IVG10 47
- TIMER 6 Interrupt IVG10 48
- TIMER 7 Interrupt IVG10 49
- TIMER 8 Interrupt IVG10 50
- TIMER 9 Interrupt IVG10 51
- TIMER 10 Interrupt IVG10 52
- TIMER 11 Interrupt IVG10 53
-
- Programmable Flags0 A (8) IVG11 54
- Programmable Flags0 B (8) IVG11 55
- Programmable Flags1 A (8) IVG11 56
- Programmable Flags1 B (8) IVG11 57
- Programmable Flags2 A (8) IVG11 58
- Programmable Flags2 B (8) IVG11 59
-
- MDMA1 0 write/read INT IVG8 60
- MDMA1 1 write/read INT IVG8 61
-
- MDMA2 0 write/read INT IVG9 62
- MDMA2 1 write/read INT IVG9 63
-
- IMDMA 0 write/read INT IVG12 64
- IMDMA 1 write/read INT IVG12 65
-
- Watch Dog Timer IVG13 66
-
- Reserved interrupt IVG7 67
- Reserved interrupt IVG7 68
- Supplemental interrupt 0 IVG7 69
- supplemental interrupt 1 IVG7 70
-
- Softirq IVG14
- System Call --
- (lowest priority) IVG15
-
- **********************************************************************/
-
-#define SYS_IRQS 71
-#define NR_PERI_INTS 64
-
-/*
- * The ABSTRACT IRQ definitions
- * the first seven of the following are fixed,
- * the rest you change if you need to.
- */
-/* IVG 0-6*/
-#define IRQ_EMU 0 /* Emulation */
-#define IRQ_RST 1 /* Reset */
-#define IRQ_NMI 2 /* Non Maskable Interrupt */
-#define IRQ_EVX 3 /* Exception */
-#define IRQ_UNUSED 4 /* Reserved interrupt */
-#define IRQ_HWERR 5 /* Hardware Error */
-#define IRQ_CORETMR 6 /* Core timer */
-
-#define IVG_BASE 7
-/* IVG 7 */
-#define IRQ_PLL_WAKEUP (IVG_BASE + 0) /* PLL Wakeup Interrupt */
-#define IRQ_DMA1_ERROR (IVG_BASE + 1) /* DMA1 Error (general) */
-#define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */
-#define IRQ_DMA2_ERROR (IVG_BASE + 2) /* DMA2 Error (general) */
-#define IRQ_IMDMA_ERROR (IVG_BASE + 3) /* IMDMA Error Interrupt */
-#define IRQ_PPI1_ERROR (IVG_BASE + 4) /* PPI1 Error Interrupt */
-#define IRQ_PPI_ERROR IRQ_PPI1_ERROR /* PPI1 Error Interrupt */
-#define IRQ_PPI2_ERROR (IVG_BASE + 5) /* PPI2 Error Interrupt */
-#define IRQ_SPORT0_ERROR (IVG_BASE + 6) /* SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERROR (IVG_BASE + 7) /* SPORT1 Error Interrupt */
-#define IRQ_SPI_ERROR (IVG_BASE + 8) /* SPI Error Interrupt */
-#define IRQ_UART_ERROR (IVG_BASE + 9) /* UART Error Interrupt */
-#define IRQ_RESERVED_ERROR (IVG_BASE + 10) /* Reversed Interrupt */
-/* IVG 8 */
-#define IRQ_DMA1_0 (IVG_BASE + 11) /* DMA1 0 Interrupt(PPI1) */
-#define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
-#define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
-#define IRQ_DMA1_1 (IVG_BASE + 12) /* DMA1 1 Interrupt(PPI2) */
-#define IRQ_PPI1 IRQ_DMA1_1 /* DMA1 1 Interrupt(PPI2) */
-#define IRQ_DMA1_2 (IVG_BASE + 13) /* DMA1 2 Interrupt */
-#define IRQ_DMA1_3 (IVG_BASE + 14) /* DMA1 3 Interrupt */
-#define IRQ_DMA1_4 (IVG_BASE + 15) /* DMA1 4 Interrupt */
-#define IRQ_DMA1_5 (IVG_BASE + 16) /* DMA1 5 Interrupt */
-#define IRQ_DMA1_6 (IVG_BASE + 17) /* DMA1 6 Interrupt */
-#define IRQ_DMA1_7 (IVG_BASE + 18) /* DMA1 7 Interrupt */
-#define IRQ_DMA1_8 (IVG_BASE + 19) /* DMA1 8 Interrupt */
-#define IRQ_DMA1_9 (IVG_BASE + 20) /* DMA1 9 Interrupt */
-#define IRQ_DMA1_10 (IVG_BASE + 21) /* DMA1 10 Interrupt */
-#define IRQ_DMA1_11 (IVG_BASE + 22) /* DMA1 11 Interrupt */
-/* IVG 9 */
-#define IRQ_DMA2_0 (IVG_BASE + 23) /* DMA2 0 (SPORT0 RX) */
-#define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */
-#define IRQ_DMA2_1 (IVG_BASE + 24) /* DMA2 1 (SPORT0 TX) */
-#define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */
-#define IRQ_DMA2_2 (IVG_BASE + 25) /* DMA2 2 (SPORT1 RX) */
-#define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */
-#define IRQ_DMA2_3 (IVG_BASE + 26) /* DMA2 3 (SPORT2 TX) */
-#define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */
-#define IRQ_DMA2_4 (IVG_BASE + 27) /* DMA2 4 (SPI) */
-#define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */
-#define IRQ_DMA2_5 (IVG_BASE + 28) /* DMA2 5 (UART RX) */
-#define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */
-#define IRQ_DMA2_6 (IVG_BASE + 29) /* DMA2 6 (UART TX) */
-#define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */
-#define IRQ_DMA2_7 (IVG_BASE + 30) /* DMA2 7 Interrupt */
-#define IRQ_DMA2_8 (IVG_BASE + 31) /* DMA2 8 Interrupt */
-#define IRQ_DMA2_9 (IVG_BASE + 32) /* DMA2 9 Interrupt */
-#define IRQ_DMA2_10 (IVG_BASE + 33) /* DMA2 10 Interrupt */
-#define IRQ_DMA2_11 (IVG_BASE + 34) /* DMA2 11 Interrupt */
-/* IVG 10 */
-#define IRQ_TIMER0 (IVG_BASE + 35) /* TIMER 0 Interrupt */
-#define IRQ_TIMER1 (IVG_BASE + 36) /* TIMER 1 Interrupt */
-#define IRQ_TIMER2 (IVG_BASE + 37) /* TIMER 2 Interrupt */
-#define IRQ_TIMER3 (IVG_BASE + 38) /* TIMER 3 Interrupt */
-#define IRQ_TIMER4 (IVG_BASE + 39) /* TIMER 4 Interrupt */
-#define IRQ_TIMER5 (IVG_BASE + 40) /* TIMER 5 Interrupt */
-#define IRQ_TIMER6 (IVG_BASE + 41) /* TIMER 6 Interrupt */
-#define IRQ_TIMER7 (IVG_BASE + 42) /* TIMER 7 Interrupt */
-#define IRQ_TIMER8 (IVG_BASE + 43) /* TIMER 8 Interrupt */
-#define IRQ_TIMER9 (IVG_BASE + 44) /* TIMER 9 Interrupt */
-#define IRQ_TIMER10 (IVG_BASE + 45) /* TIMER 10 Interrupt */
-#define IRQ_TIMER11 (IVG_BASE + 46) /* TIMER 11 Interrupt */
-/* IVG 11 */
-#define IRQ_PROG0_INTA (IVG_BASE + 47) /* Programmable Flags0 A (8) */
-#define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */
-#define IRQ_PROG0_INTB (IVG_BASE + 48) /* Programmable Flags0 B (8) */
-#define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */
-#define IRQ_PROG1_INTA (IVG_BASE + 49) /* Programmable Flags1 A (8) */
-#define IRQ_PROG1_INTB (IVG_BASE + 50) /* Programmable Flags1 B (8) */
-#define IRQ_PROG2_INTA (IVG_BASE + 51) /* Programmable Flags2 A (8) */
-#define IRQ_PROG2_INTB (IVG_BASE + 52) /* Programmable Flags2 B (8) */
-/* IVG 8 */
-#define IRQ_DMA1_WRRD0 (IVG_BASE + 53) /* MDMA1 0 write/read INT */
-#define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */
+#include <mach-common/irq.h>
+
+#define NR_PERI_INTS (2 * 32)
+
+#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
+#define IRQ_DMA1_ERROR BFIN_IRQ(1) /* DMA1 Error (general) */
+#define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */
+#define IRQ_DMA2_ERROR BFIN_IRQ(2) /* DMA2 Error (general) */
+#define IRQ_IMDMA_ERROR BFIN_IRQ(3) /* IMDMA Error Interrupt */
+#define IRQ_PPI1_ERROR BFIN_IRQ(4) /* PPI1 Error Interrupt */
+#define IRQ_PPI_ERROR IRQ_PPI1_ERROR /* PPI1 Error Interrupt */
+#define IRQ_PPI2_ERROR BFIN_IRQ(5) /* PPI2 Error Interrupt */
+#define IRQ_SPORT0_ERROR BFIN_IRQ(6) /* SPORT0 Error Interrupt */
+#define IRQ_SPORT1_ERROR BFIN_IRQ(7) /* SPORT1 Error Interrupt */
+#define IRQ_SPI_ERROR BFIN_IRQ(8) /* SPI Error Interrupt */
+#define IRQ_UART_ERROR BFIN_IRQ(9) /* UART Error Interrupt */
+#define IRQ_RESERVED_ERROR BFIN_IRQ(10) /* Reversed */
+#define IRQ_DMA1_0 BFIN_IRQ(11) /* DMA1 0 Interrupt(PPI1) */
+#define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
+#define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
+#define IRQ_DMA1_1 BFIN_IRQ(12) /* DMA1 1 Interrupt(PPI2) */
+#define IRQ_PPI1 IRQ_DMA1_1 /* DMA1 1 Interrupt(PPI2) */
+#define IRQ_DMA1_2 BFIN_IRQ(13) /* DMA1 2 Interrupt */
+#define IRQ_DMA1_3 BFIN_IRQ(14) /* DMA1 3 Interrupt */
+#define IRQ_DMA1_4 BFIN_IRQ(15) /* DMA1 4 Interrupt */
+#define IRQ_DMA1_5 BFIN_IRQ(16) /* DMA1 5 Interrupt */
+#define IRQ_DMA1_6 BFIN_IRQ(17) /* DMA1 6 Interrupt */
+#define IRQ_DMA1_7 BFIN_IRQ(18) /* DMA1 7 Interrupt */
+#define IRQ_DMA1_8 BFIN_IRQ(19) /* DMA1 8 Interrupt */
+#define IRQ_DMA1_9 BFIN_IRQ(20) /* DMA1 9 Interrupt */
+#define IRQ_DMA1_10 BFIN_IRQ(21) /* DMA1 10 Interrupt */
+#define IRQ_DMA1_11 BFIN_IRQ(22) /* DMA1 11 Interrupt */
+#define IRQ_DMA2_0 BFIN_IRQ(23) /* DMA2 0 (SPORT0 RX) */
+#define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */
+#define IRQ_DMA2_1 BFIN_IRQ(24) /* DMA2 1 (SPORT0 TX) */
+#define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */
+#define IRQ_DMA2_2 BFIN_IRQ(25) /* DMA2 2 (SPORT1 RX) */
+#define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */
+#define IRQ_DMA2_3 BFIN_IRQ(26) /* DMA2 3 (SPORT2 TX) */
+#define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */
+#define IRQ_DMA2_4 BFIN_IRQ(27) /* DMA2 4 (SPI) */
+#define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */
+#define IRQ_DMA2_5 BFIN_IRQ(28) /* DMA2 5 (UART RX) */
+#define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */
+#define IRQ_DMA2_6 BFIN_IRQ(29) /* DMA2 6 (UART TX) */
+#define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */
+#define IRQ_DMA2_7 BFIN_IRQ(30) /* DMA2 7 Interrupt */
+#define IRQ_DMA2_8 BFIN_IRQ(31) /* DMA2 8 Interrupt */
+#define IRQ_DMA2_9 BFIN_IRQ(32) /* DMA2 9 Interrupt */
+#define IRQ_DMA2_10 BFIN_IRQ(33) /* DMA2 10 Interrupt */
+#define IRQ_DMA2_11 BFIN_IRQ(34) /* DMA2 11 Interrupt */
+#define IRQ_TIMER0 BFIN_IRQ(35) /* TIMER 0 Interrupt */
+#define IRQ_TIMER1 BFIN_IRQ(36) /* TIMER 1 Interrupt */
+#define IRQ_TIMER2 BFIN_IRQ(37) /* TIMER 2 Interrupt */
+#define IRQ_TIMER3 BFIN_IRQ(38) /* TIMER 3 Interrupt */
+#define IRQ_TIMER4 BFIN_IRQ(39) /* TIMER 4 Interrupt */
+#define IRQ_TIMER5 BFIN_IRQ(40) /* TIMER 5 Interrupt */
+#define IRQ_TIMER6 BFIN_IRQ(41) /* TIMER 6 Interrupt */
+#define IRQ_TIMER7 BFIN_IRQ(42) /* TIMER 7 Interrupt */
+#define IRQ_TIMER8 BFIN_IRQ(43) /* TIMER 8 Interrupt */
+#define IRQ_TIMER9 BFIN_IRQ(44) /* TIMER 9 Interrupt */
+#define IRQ_TIMER10 BFIN_IRQ(45) /* TIMER 10 Interrupt */
+#define IRQ_TIMER11 BFIN_IRQ(46) /* TIMER 11 Interrupt */
+#define IRQ_PROG0_INTA BFIN_IRQ(47) /* Programmable Flags0 A (8) */
+#define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */
+#define IRQ_PROG0_INTB BFIN_IRQ(48) /* Programmable Flags0 B (8) */
+#define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */
+#define IRQ_PROG1_INTA BFIN_IRQ(49) /* Programmable Flags1 A (8) */
+#define IRQ_PROG1_INTB BFIN_IRQ(50) /* Programmable Flags1 B (8) */
+#define IRQ_PROG2_INTA BFIN_IRQ(51) /* Programmable Flags2 A (8) */
+#define IRQ_PROG2_INTB BFIN_IRQ(52) /* Programmable Flags2 B (8) */
+#define IRQ_DMA1_WRRD0 BFIN_IRQ(53) /* MDMA1 0 write/read INT */
+#define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */
#define IRQ_MEM_DMA0 IRQ_DMA1_WRRD0
-#define IRQ_DMA1_WRRD1 (IVG_BASE + 54) /* MDMA1 1 write/read INT */
-#define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */
+#define IRQ_DMA1_WRRD1 BFIN_IRQ(54) /* MDMA1 1 write/read INT */
+#define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */
#define IRQ_MEM_DMA1 IRQ_DMA1_WRRD1
-/* IVG 9 */
-#define IRQ_DMA2_WRRD0 (IVG_BASE + 55) /* MDMA2 0 write/read INT */
+#define IRQ_DMA2_WRRD0 BFIN_IRQ(55) /* MDMA2 0 write/read INT */
#define IRQ_MEM_DMA2 IRQ_DMA2_WRRD0
-#define IRQ_DMA2_WRRD1 (IVG_BASE + 56) /* MDMA2 1 write/read INT */
+#define IRQ_DMA2_WRRD1 BFIN_IRQ(56) /* MDMA2 1 write/read INT */
#define IRQ_MEM_DMA3 IRQ_DMA2_WRRD1
-/* IVG 12 */
-#define IRQ_IMDMA_WRRD0 (IVG_BASE + 57) /* IMDMA 0 write/read INT */
+#define IRQ_IMDMA_WRRD0 BFIN_IRQ(57) /* IMDMA 0 write/read INT */
#define IRQ_IMEM_DMA0 IRQ_IMDMA_WRRD0
-#define IRQ_IMDMA_WRRD1 (IVG_BASE + 58) /* IMDMA 1 write/read INT */
+#define IRQ_IMDMA_WRRD1 BFIN_IRQ(58) /* IMDMA 1 write/read INT */
#define IRQ_IMEM_DMA1 IRQ_IMDMA_WRRD1
-/* IVG 13 */
-#define IRQ_WATCH (IVG_BASE + 59) /* Watch Dog Timer */
-/* IVG 7 */
-#define IRQ_RESERVED_1 (IVG_BASE + 60) /* Reserved interrupt */
-#define IRQ_RESERVED_2 (IVG_BASE + 61) /* Reserved interrupt */
-#define IRQ_SUPPLE_0 (IVG_BASE + 62) /* Supplemental interrupt 0 */
-#define IRQ_SUPPLE_1 (IVG_BASE + 63) /* supplemental interrupt 1 */
+#define IRQ_WATCH BFIN_IRQ(59) /* Watch Dog Timer */
+#define IRQ_RESERVED_1 BFIN_IRQ(60) /* Reserved interrupt */
+#define IRQ_RESERVED_2 BFIN_IRQ(61) /* Reserved interrupt */
+#define IRQ_SUPPLE_0 BFIN_IRQ(62) /* Supplemental interrupt 0 */
+#define IRQ_SUPPLE_1 BFIN_IRQ(63) /* supplemental interrupt 1 */
+
+#define SYS_IRQS 71
#define IRQ_PF0 73
#define IRQ_PF1 74
#define GPIO_IRQ_BASE IRQ_PF0
#define NR_MACH_IRQS (IRQ_PF47 + 1)
-#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
-
-#define IVG7 7
-#define IVG8 8
-#define IVG9 9
-#define IVG10 10
-#define IVG11 11
-#define IVG12 12
-#define IVG13 13
-#define IVG14 14
-#define IVG15 15
-
-/*
- * DEFAULT PRIORITIES:
- */
-
-#define CONFIG_DEF_PLL_WAKEUP 7
-#define CONFIG_DEF_DMA1_ERROR 7
-#define CONFIG_DEF_DMA2_ERROR 7
-#define CONFIG_DEF_IMDMA_ERROR 7
-#define CONFIG_DEF_PPI1_ERROR 7
-#define CONFIG_DEF_PPI2_ERROR 7
-#define CONFIG_DEF_SPORT0_ERROR 7
-#define CONFIG_DEF_SPORT1_ERROR 7
-#define CONFIG_DEF_SPI_ERROR 7
-#define CONFIG_DEF_UART_ERROR 7
-#define CONFIG_DEF_RESERVED_ERROR 7
-#define CONFIG_DEF_DMA1_0 8
-#define CONFIG_DEF_DMA1_1 8
-#define CONFIG_DEF_DMA1_2 8
-#define CONFIG_DEF_DMA1_3 8
-#define CONFIG_DEF_DMA1_4 8
-#define CONFIG_DEF_DMA1_5 8
-#define CONFIG_DEF_DMA1_6 8
-#define CONFIG_DEF_DMA1_7 8
-#define CONFIG_DEF_DMA1_8 8
-#define CONFIG_DEF_DMA1_9 8
-#define CONFIG_DEF_DMA1_10 8
-#define CONFIG_DEF_DMA1_11 8
-#define CONFIG_DEF_DMA2_0 9
-#define CONFIG_DEF_DMA2_1 9
-#define CONFIG_DEF_DMA2_2 9
-#define CONFIG_DEF_DMA2_3 9
-#define CONFIG_DEF_DMA2_4 9
-#define CONFIG_DEF_DMA2_5 9
-#define CONFIG_DEF_DMA2_6 9
-#define CONFIG_DEF_DMA2_7 9
-#define CONFIG_DEF_DMA2_8 9
-#define CONFIG_DEF_DMA2_9 9
-#define CONFIG_DEF_DMA2_10 9
-#define CONFIG_DEF_DMA2_11 9
-#define CONFIG_DEF_TIMER0 10
-#define CONFIG_DEF_TIMER1 10
-#define CONFIG_DEF_TIMER2 10
-#define CONFIG_DEF_TIMER3 10
-#define CONFIG_DEF_TIMER4 10
-#define CONFIG_DEF_TIMER5 10
-#define CONFIG_DEF_TIMER6 10
-#define CONFIG_DEF_TIMER7 10
-#define CONFIG_DEF_TIMER8 10
-#define CONFIG_DEF_TIMER9 10
-#define CONFIG_DEF_TIMER10 10
-#define CONFIG_DEF_TIMER11 10
-#define CONFIG_DEF_PROG0_INTA 11
-#define CONFIG_DEF_PROG0_INTB 11
-#define CONFIG_DEF_PROG1_INTA 11
-#define CONFIG_DEF_PROG1_INTB 11
-#define CONFIG_DEF_PROG2_INTA 11
-#define CONFIG_DEF_PROG2_INTB 11
-#define CONFIG_DEF_DMA1_WRRD0 8
-#define CONFIG_DEF_DMA1_WRRD1 8
-#define CONFIG_DEF_DMA2_WRRD0 9
-#define CONFIG_DEF_DMA2_WRRD1 9
-#define CONFIG_DEF_IMDMA_WRRD0 12
-#define CONFIG_DEF_IMDMA_WRRD1 12
-#define CONFIG_DEF_WATCH 13
-#define CONFIG_DEF_RESERVED_1 7
-#define CONFIG_DEF_RESERVED_2 7
-#define CONFIG_DEF_SUPPLE_0 7
-#define CONFIG_DEF_SUPPLE_1 7
/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS 0
-#define IRQ_DMA1_ERROR_POS 4
-#define IRQ_DMA2_ERROR_POS 8
-#define IRQ_IMDMA_ERROR_POS 12
-#define IRQ_PPI0_ERROR_POS 16
-#define IRQ_PPI1_ERROR_POS 20
-#define IRQ_SPORT0_ERROR_POS 24
-#define IRQ_SPORT1_ERROR_POS 28
+#define IRQ_PLL_WAKEUP_POS 0
+#define IRQ_DMA1_ERROR_POS 4
+#define IRQ_DMA2_ERROR_POS 8
+#define IRQ_IMDMA_ERROR_POS 12
+#define IRQ_PPI0_ERROR_POS 16
+#define IRQ_PPI1_ERROR_POS 20
+#define IRQ_SPORT0_ERROR_POS 24
+#define IRQ_SPORT1_ERROR_POS 28
+
/* IAR1 BIT FIELDS */
-#define IRQ_SPI_ERROR_POS 0
-#define IRQ_UART_ERROR_POS 4
-#define IRQ_RESERVED_ERROR_POS 8
-#define IRQ_DMA1_0_POS 12
-#define IRQ_DMA1_1_POS 16
-#define IRQ_DMA1_2_POS 20
-#define IRQ_DMA1_3_POS 24
-#define IRQ_DMA1_4_POS 28
+#define IRQ_SPI_ERROR_POS 0
+#define IRQ_UART_ERROR_POS 4
+#define IRQ_RESERVED_ERROR_POS 8
+#define IRQ_DMA1_0_POS 12
+#define IRQ_DMA1_1_POS 16
+#define IRQ_DMA1_2_POS 20
+#define IRQ_DMA1_3_POS 24
+#define IRQ_DMA1_4_POS 28
+
/* IAR2 BIT FIELDS */
-#define IRQ_DMA1_5_POS 0
-#define IRQ_DMA1_6_POS 4
-#define IRQ_DMA1_7_POS 8
-#define IRQ_DMA1_8_POS 12
-#define IRQ_DMA1_9_POS 16
-#define IRQ_DMA1_10_POS 20
-#define IRQ_DMA1_11_POS 24
-#define IRQ_DMA2_0_POS 28
+#define IRQ_DMA1_5_POS 0
+#define IRQ_DMA1_6_POS 4
+#define IRQ_DMA1_7_POS 8
+#define IRQ_DMA1_8_POS 12
+#define IRQ_DMA1_9_POS 16
+#define IRQ_DMA1_10_POS 20
+#define IRQ_DMA1_11_POS 24
+#define IRQ_DMA2_0_POS 28
+
/* IAR3 BIT FIELDS */
-#define IRQ_DMA2_1_POS 0
-#define IRQ_DMA2_2_POS 4
-#define IRQ_DMA2_3_POS 8
-#define IRQ_DMA2_4_POS 12
-#define IRQ_DMA2_5_POS 16
-#define IRQ_DMA2_6_POS 20
-#define IRQ_DMA2_7_POS 24
-#define IRQ_DMA2_8_POS 28
+#define IRQ_DMA2_1_POS 0
+#define IRQ_DMA2_2_POS 4
+#define IRQ_DMA2_3_POS 8
+#define IRQ_DMA2_4_POS 12
+#define IRQ_DMA2_5_POS 16
+#define IRQ_DMA2_6_POS 20
+#define IRQ_DMA2_7_POS 24
+#define IRQ_DMA2_8_POS 28
+
/* IAR4 BIT FIELDS */
-#define IRQ_DMA2_9_POS 0
-#define IRQ_DMA2_10_POS 4
-#define IRQ_DMA2_11_POS 8
-#define IRQ_TIMER0_POS 12
-#define IRQ_TIMER1_POS 16
-#define IRQ_TIMER2_POS 20
-#define IRQ_TIMER3_POS 24
-#define IRQ_TIMER4_POS 28
+#define IRQ_DMA2_9_POS 0
+#define IRQ_DMA2_10_POS 4
+#define IRQ_DMA2_11_POS 8
+#define IRQ_TIMER0_POS 12
+#define IRQ_TIMER1_POS 16
+#define IRQ_TIMER2_POS 20
+#define IRQ_TIMER3_POS 24
+#define IRQ_TIMER4_POS 28
+
/* IAR5 BIT FIELDS */
-#define IRQ_TIMER5_POS 0
-#define IRQ_TIMER6_POS 4
-#define IRQ_TIMER7_POS 8
-#define IRQ_TIMER8_POS 12
-#define IRQ_TIMER9_POS 16
-#define IRQ_TIMER10_POS 20
-#define IRQ_TIMER11_POS 24
-#define IRQ_PROG0_INTA_POS 28
+#define IRQ_TIMER5_POS 0
+#define IRQ_TIMER6_POS 4
+#define IRQ_TIMER7_POS 8
+#define IRQ_TIMER8_POS 12
+#define IRQ_TIMER9_POS 16
+#define IRQ_TIMER10_POS 20
+#define IRQ_TIMER11_POS 24
+#define IRQ_PROG0_INTA_POS 28
+
/* IAR6 BIT FIELDS */
-#define IRQ_PROG0_INTB_POS 0
-#define IRQ_PROG1_INTA_POS 4
-#define IRQ_PROG1_INTB_POS 8
-#define IRQ_PROG2_INTA_POS 12
-#define IRQ_PROG2_INTB_POS 16
-#define IRQ_DMA1_WRRD0_POS 20
-#define IRQ_DMA1_WRRD1_POS 24
-#define IRQ_DMA2_WRRD0_POS 28
-/* IAR7 BIT FIELDS */
-#define IRQ_DMA2_WRRD1_POS 0
-#define IRQ_IMDMA_WRRD0_POS 4
-#define IRQ_IMDMA_WRRD1_POS 8
-#define IRQ_WDTIMER_POS 12
-#define IRQ_RESERVED_1_POS 16
-#define IRQ_RESERVED_2_POS 20
-#define IRQ_SUPPLE_0_POS 24
-#define IRQ_SUPPLE_1_POS 28
+#define IRQ_PROG0_INTB_POS 0
+#define IRQ_PROG1_INTA_POS 4
+#define IRQ_PROG1_INTB_POS 8
+#define IRQ_PROG2_INTA_POS 12
+#define IRQ_PROG2_INTB_POS 16
+#define IRQ_DMA1_WRRD0_POS 20
+#define IRQ_DMA1_WRRD1_POS 24
+#define IRQ_DMA2_WRRD0_POS 28
-#endif /* _BF561_IRQ_H_ */
+/* IAR7 BIT FIELDS */
+#define IRQ_DMA2_WRRD1_POS 0
+#define IRQ_IMDMA_WRRD0_POS 4
+#define IRQ_IMDMA_WRRD1_POS 8
+#define IRQ_WDTIMER_POS 12
+#define IRQ_RESERVED_1_POS 16
+#define IRQ_RESERVED_2_POS 20
+#define IRQ_SUPPLE_0_POS 24
+#define IRQ_SUPPLE_1_POS 28
+
+#endif
void __init platform_init_cpus(void)
{
- cpu_set(0, cpu_possible_map); /* CoreA */
- cpu_set(1, cpu_possible_map); /* CoreB */
+ struct cpumask mask;
+
+ cpumask_set_cpu(0, &mask); /* CoreA */
+ cpumask_set_cpu(1, &mask); /* CoreB */
+ init_cpu_possible(&mask);
}
void __init platform_prepare_cpus(unsigned int max_cpus)
{
+ struct cpumask mask;
+
bfin_relocate_coreb_l1_mem();
/* Both cores ought to be present on a bf561! */
- cpu_set(0, cpu_present_map); /* CoreA */
- cpu_set(1, cpu_present_map); /* CoreB */
+ cpumask_set_cpu(0, &mask); /* CoreA */
+ cpumask_set_cpu(1, &mask); /* CoreB */
+ init_cpu_present(&mask);
}
int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
bfin_write_SICB_IWR1(IWR_DISABLE_ALL);
SSYNC();
- /* Store CPU-private information to the cpu_data array. */
- bfin_setup_cpudata(cpu);
-
/* We are done with local CPU inits, unblock the boot CPU. */
set_cpu_online(cpu, true);
spin_lock(&boot_lock);
{
unsigned int cpu;
unsigned int this_cpu = smp_processor_id();
- cpumask_t mask = cpu_online_map;
+ cpumask_t mask;
- cpu_clear(this_cpu, mask);
- for_each_cpu_mask(cpu, mask)
+ cpumask_copy(&mask, cpu_online_mask);
+ cpumask_clear_cpu(this_cpu, &mask);
+ for_each_cpu(cpu, &mask)
platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
}
#ifdef CONFIG_IPIPE
#include <linux/ipipe.h>
#endif
-#ifdef CONFIG_KGDB
-#include <linux/kgdb.h>
-#endif
#include <asm/traps.h>
#include <asm/blackfin.h>
#include <asm/gpio.h>
#include <asm/irq_handler.h>
#include <asm/dpmc.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/bfin_sport.h>
-#include <asm/bfin_can.h>
#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
-#ifdef BF537_FAMILY
-# define BF537_GENERIC_ERROR_INT_DEMUX
-# define SPI_ERR_MASK (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */
-# define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORT_STAT */
-# define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */
-# define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
-# define UART_ERR_MASK (0x6) /* UART_IIR */
-# define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */
-#else
-# undef BF537_GENERIC_ERROR_INT_DEMUX
-#endif
-
/*
* NOTES:
* - we have separated the physical Hardware interrupt from the
EXPORT_SYMBOL(bfin_irq_flags);
#endif
-/* The number of spurious interrupts */
-atomic_t num_spurious;
-
#ifdef CONFIG_PM
unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
unsigned vr_wakeup;
#endif
-struct ivgx {
+static struct ivgx {
/* irq number for request_irq, available in mach-bf5xx/irq.h */
unsigned int irqno;
/* corresponding bit in the SIC_ISR register */
unsigned int isrflag;
} ivg_table[NR_PERI_INTS];
-struct ivg_slice {
+static struct ivg_slice {
/* position of first irq in ivg_table for given ivg */
struct ivgx *ifirst;
struct ivgx *istop;
* This is for core internal IRQs
*/
-static void bfin_ack_noop(struct irq_data *d)
+void bfin_ack_noop(struct irq_data *d)
{
/* Dummy function. */
}
return;
}
-static void bfin_internal_mask_irq(unsigned int irq)
+void bfin_internal_mask_irq(unsigned int irq)
{
- unsigned long flags;
+ unsigned long flags = hard_local_irq_save();
-#ifdef CONFIG_BF53x
- flags = hard_local_irq_save();
- bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
- ~(1 << SIC_SYSIRQ(irq)));
-#else
- unsigned mask_bank, mask_bit;
- flags = hard_local_irq_save();
- mask_bank = SIC_SYSIRQ(irq) / 32;
- mask_bit = SIC_SYSIRQ(irq) % 32;
+#ifdef SIC_IMASK0
+ unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
+ unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
~(1 << mask_bit));
-#ifdef CONFIG_SMP
+# ifdef CONFIG_SMP
bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
~(1 << mask_bit));
+# endif
+#else
+ bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
+ ~(1 << SIC_SYSIRQ(irq)));
#endif
-#endif
+
hard_local_irq_restore(flags);
}
static void bfin_internal_unmask_irq_affinity(unsigned int irq,
const struct cpumask *affinity)
#else
-static void bfin_internal_unmask_irq(unsigned int irq)
+void bfin_internal_unmask_irq(unsigned int irq)
#endif
{
- unsigned long flags;
+ unsigned long flags = hard_local_irq_save();
-#ifdef CONFIG_BF53x
- flags = hard_local_irq_save();
- bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
- (1 << SIC_SYSIRQ(irq)));
-#else
- unsigned mask_bank, mask_bit;
- flags = hard_local_irq_save();
- mask_bank = SIC_SYSIRQ(irq) / 32;
- mask_bit = SIC_SYSIRQ(irq) % 32;
-#ifdef CONFIG_SMP
+#ifdef SIC_IMASK0
+ unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
+ unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
+# ifdef CONFIG_SMP
if (cpumask_test_cpu(0, affinity))
-#endif
+# endif
bfin_write_SIC_IMASK(mask_bank,
bfin_read_SIC_IMASK(mask_bank) |
(1 << mask_bit));
-#ifdef CONFIG_SMP
+# ifdef CONFIG_SMP
if (cpumask_test_cpu(1, affinity))
bfin_write_SICB_IMASK(mask_bank,
bfin_read_SICB_IMASK(mask_bank) |
(1 << mask_bit));
+# endif
+#else
+ bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
+ (1 << SIC_SYSIRQ(irq)));
#endif
-#endif
+
hard_local_irq_restore(flags);
}
{
return bfin_internal_set_wake(d->irq, state);
}
+#else
+# define bfin_internal_set_wake_chip NULL
#endif
static struct irq_chip bfin_core_irqchip = {
#ifdef CONFIG_SMP
.irq_set_affinity = bfin_internal_set_affinity,
#endif
-#ifdef CONFIG_PM
.irq_set_wake = bfin_internal_set_wake_chip,
-#endif
};
-static void bfin_handle_irq(unsigned irq)
+void bfin_handle_irq(unsigned irq)
{
#ifdef CONFIG_IPIPE
struct pt_regs regs; /* Contents not used. */
#endif /* !CONFIG_IPIPE */
}
-#ifdef BF537_GENERIC_ERROR_INT_DEMUX
-static int error_int_mask;
-
-static void bfin_generic_error_mask_irq(struct irq_data *d)
-{
- error_int_mask &= ~(1L << (d->irq - IRQ_PPI_ERROR));
- if (!error_int_mask)
- bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
-}
-
-static void bfin_generic_error_unmask_irq(struct irq_data *d)
-{
- bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
- error_int_mask |= 1L << (d->irq - IRQ_PPI_ERROR);
-}
-
-static struct irq_chip bfin_generic_error_irqchip = {
- .name = "ERROR",
- .irq_ack = bfin_ack_noop,
- .irq_mask_ack = bfin_generic_error_mask_irq,
- .irq_mask = bfin_generic_error_mask_irq,
- .irq_unmask = bfin_generic_error_unmask_irq,
-};
-
-static void bfin_demux_error_irq(unsigned int int_err_irq,
- struct irq_desc *inta_desc)
-{
- int irq = 0;
-
-#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
- if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
- irq = IRQ_MAC_ERROR;
- else
-#endif
- if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
- irq = IRQ_SPORT0_ERROR;
- else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
- irq = IRQ_SPORT1_ERROR;
- else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
- irq = IRQ_PPI_ERROR;
- else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
- irq = IRQ_CAN_ERROR;
- else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
- irq = IRQ_SPI_ERROR;
- else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
- irq = IRQ_UART0_ERROR;
- else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
- irq = IRQ_UART1_ERROR;
-
- if (irq) {
- if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
- bfin_handle_irq(irq);
- else {
-
- switch (irq) {
- case IRQ_PPI_ERROR:
- bfin_write_PPI_STATUS(PPI_ERR_MASK);
- break;
-#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
- case IRQ_MAC_ERROR:
- bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
- break;
-#endif
- case IRQ_SPORT0_ERROR:
- bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
- break;
-
- case IRQ_SPORT1_ERROR:
- bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
- break;
-
- case IRQ_CAN_ERROR:
- bfin_write_CAN_GIS(CAN_ERR_MASK);
- break;
-
- case IRQ_SPI_ERROR:
- bfin_write_SPI_STAT(SPI_ERR_MASK);
- break;
-
- default:
- break;
- }
-
- pr_debug("IRQ %d:"
- " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
- irq);
- }
- } else
- printk(KERN_ERR
- "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
- " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
- __func__, __FILE__, __LINE__);
-
-}
-#endif /* BF537_GENERIC_ERROR_INT_DEMUX */
-
#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
static int mac_stat_int_mask;
unsigned int irq = d->irq;
mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
-#ifdef BF537_GENERIC_ERROR_INT_DEMUX
+#ifdef BF537_FAMILY
switch (irq) {
case IRQ_MAC_PHYINT:
bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
{
unsigned int irq = d->irq;
-#ifdef BF537_GENERIC_ERROR_INT_DEMUX
+#ifdef BF537_FAMILY
switch (irq) {
case IRQ_MAC_PHYINT:
bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
#ifdef CONFIG_PM
int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
{
-#ifdef BF537_GENERIC_ERROR_INT_DEMUX
+#ifdef BF537_FAMILY
return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
#else
return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
#endif
}
+#else
+# define bfin_mac_status_set_wake NULL
#endif
static struct irq_chip bfin_mac_status_irqchip = {
.irq_mask_ack = bfin_mac_status_mask_irq,
.irq_mask = bfin_mac_status_mask_irq,
.irq_unmask = bfin_mac_status_unmask_irq,
-#ifdef CONFIG_PM
.irq_set_wake = bfin_mac_status_set_wake,
-#endif
};
-static void bfin_demux_mac_status_irq(unsigned int int_err_irq,
- struct irq_desc *inta_desc)
+void bfin_demux_mac_status_irq(unsigned int int_err_irq,
+ struct irq_desc *inta_desc)
{
int i, irq = 0;
u32 status = bfin_read_EMAC_SYSTAT();
}
#ifdef CONFIG_PM
-int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
+static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
{
return gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
}
+#else
+# define bfin_gpio_set_wake NULL
#endif
-static void bfin_demux_gpio_irq(unsigned int inta_irq,
- struct irq_desc *desc)
+static void bfin_demux_gpio_block(unsigned int irq)
{
- unsigned int i, gpio, mask, irq, search = 0;
+ unsigned int gpio, mask;
+
+ gpio = irq_to_gpio(irq);
+ mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
+
+ while (mask) {
+ if (mask & 1)
+ bfin_handle_irq(irq);
+ irq++;
+ mask >>= 1;
+ }
+}
+
+void bfin_demux_gpio_irq(unsigned int inta_irq,
+ struct irq_desc *desc)
+{
+ unsigned int irq;
switch (inta_irq) {
-#if defined(CONFIG_BF53x)
- case IRQ_PROG_INTA:
- irq = IRQ_PF0;
- search = 1;
+#if defined(BF537_FAMILY)
+ case IRQ_PF_INTA_PG_INTA:
+ bfin_demux_gpio_block(IRQ_PF0);
+ irq = IRQ_PG0;
break;
-# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
- case IRQ_MAC_RX:
+ case IRQ_PH_INTA_MAC_RX:
irq = IRQ_PH0;
break;
-# endif
-#elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
+#elif defined(BF533_FAMILY)
+ case IRQ_PROG_INTA:
+ irq = IRQ_PF0;
+ break;
+#elif defined(BF538_FAMILY)
case IRQ_PORTF_INTA:
irq = IRQ_PF0;
break;
return;
}
- if (search) {
- for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
- irq += i;
-
- mask = get_gpiop_data(i) & get_gpiop_maska(i);
-
- while (mask) {
- if (mask & 1)
- bfin_handle_irq(irq);
- irq++;
- mask >>= 1;
- }
- }
- } else {
- gpio = irq_to_gpio(irq);
- mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
-
- do {
- if (mask & 1)
- bfin_handle_irq(irq);
- irq++;
- mask >>= 1;
- } while (mask);
- }
-
+ bfin_demux_gpio_block(irq);
}
#else /* CONFIG_BF54x */
}
#ifdef CONFIG_PM
-u32 pint_saved_masks[NR_PINT_SYS_IRQS];
-u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
-
-int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
+static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
{
u32 pint_irq;
u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
u32 bank = PINT_2_BANK(pint_val);
- u32 pintbit = PINT_BIT(pint_val);
switch (bank) {
case 0:
bfin_internal_set_wake(pint_irq, state);
- if (state)
- pint_wakeup_masks[bank] |= pintbit;
- else
- pint_wakeup_masks[bank] &= ~pintbit;
-
return 0;
}
-
-u32 bfin_pm_setup(void)
-{
- u32 val, i;
-
- for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
- val = pint[i]->mask_clear;
- pint_saved_masks[i] = val;
- if (val ^ pint_wakeup_masks[i]) {
- pint[i]->mask_clear = val;
- pint[i]->mask_set = pint_wakeup_masks[i];
- }
- }
-
- return 0;
-}
-
-void bfin_pm_restore(void)
-{
- u32 i, val;
-
- for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
- val = pint_saved_masks[i];
- if (val ^ pint_wakeup_masks[i]) {
- pint[i]->mask_clear = pint[i]->mask_clear;
- pint[i]->mask_set = val;
- }
- }
-}
+#else
+# define bfin_gpio_set_wake NULL
#endif
-static void bfin_demux_gpio_irq(unsigned int inta_irq,
- struct irq_desc *desc)
+void bfin_demux_gpio_irq(unsigned int inta_irq,
+ struct irq_desc *desc)
{
u32 bank, pint_val;
u32 request, irq;
.irq_set_type = bfin_gpio_irq_type,
.irq_startup = bfin_gpio_irq_startup,
.irq_shutdown = bfin_gpio_irq_shutdown,
-#ifdef CONFIG_PM
.irq_set_wake = bfin_gpio_set_wake,
-#endif
};
void __cpuinit init_exception_vectors(void)
{
int irq;
unsigned long ilat = 0;
+
/* Disable all the peripheral intrs - page 4-29 HW Ref manual */
-#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
- || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
+#ifdef SIC_IMASK0
bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
-# ifdef CONFIG_BF54x
+# ifdef SIC_IMASK2
bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
# endif
# ifdef CONFIG_SMP
local_irq_disable();
-#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
- /* Clear EMAC Interrupt Status bits so we can demux it later */
- bfin_write_EMAC_SYSTAT(-1);
-#endif
-
#ifdef CONFIG_BF54x
# ifdef CONFIG_PINTx_REASSIGN
pint[0]->assign = CONFIG_PINT0_ASSIGN;
irq_set_chip(irq, &bfin_internal_irqchip);
switch (irq) {
-#if defined(CONFIG_BF53x)
+#if defined(BF537_FAMILY)
+ case IRQ_PH_INTA_MAC_RX:
+ case IRQ_PF_INTA_PG_INTA:
+#elif defined(BF533_FAMILY)
case IRQ_PROG_INTA:
-# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
- case IRQ_MAC_RX:
-# endif
#elif defined(CONFIG_BF54x)
case IRQ_PINT0:
case IRQ_PINT1:
case IRQ_PROG0_INTA:
case IRQ_PROG1_INTA:
case IRQ_PROG2_INTA:
-#elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
+#elif defined(BF538_FAMILY)
case IRQ_PORTF_INTA:
#endif
irq_set_chained_handler(irq, bfin_demux_gpio_irq);
break;
-#ifdef BF537_GENERIC_ERROR_INT_DEMUX
- case IRQ_GENERIC_ERROR:
- irq_set_chained_handler(irq, bfin_demux_error_irq);
- break;
-#endif
#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
case IRQ_MAC_ERROR:
irq_set_chained_handler(irq,
case IRQ_CORETMR:
# ifdef CONFIG_SMP
irq_set_handler(irq, handle_percpu_irq);
- break;
# else
irq_set_handler(irq, handle_simple_irq);
- break;
# endif
+ break;
#endif
#ifdef CONFIG_TICKSOURCE_GPTMR0
break;
#endif
-#ifdef CONFIG_IPIPE
default:
+#ifdef CONFIG_IPIPE
irq_set_handler(irq, handle_level_irq);
- break;
-#else /* !CONFIG_IPIPE */
- default:
+#else
irq_set_handler(irq, handle_simple_irq);
+#endif
break;
-#endif /* !CONFIG_IPIPE */
}
}
-#ifdef BF537_GENERIC_ERROR_INT_DEMUX
- for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
- irq_set_chip_and_handler(irq, &bfin_generic_error_irqchip,
- handle_level_irq);
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
- irq_set_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
-#endif
-#endif
+ init_mach_irq();
#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
#ifdef CONFIG_DO_IRQ_L1
__attribute__((l1_text))
#endif
-void do_irq(int vec, struct pt_regs *fp)
+static int vec_to_irq(int vec)
{
- if (vec == EVT_IVTMR_P) {
- vec = IRQ_CORETMR;
- } else {
- struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
- struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
-#if defined(SIC_ISR0)
- unsigned long sic_status[3];
+ struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
+ struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
+ unsigned long sic_status[3];
+
+ if (likely(vec == EVT_IVTMR_P))
+ return IRQ_CORETMR;
- if (smp_processor_id()) {
+#ifdef SIC_ISR
+ sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
+#else
+ if (smp_processor_id()) {
# ifdef SICB_ISR0
- /* This will be optimized out in UP mode. */
- sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
- sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
-# endif
- } else {
- sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
- sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
- }
-# ifdef SIC_ISR2
- sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
+ /* This will be optimized out in UP mode. */
+ sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
+ sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
# endif
- for (;; ivg++) {
- if (ivg >= ivg_stop) {
- atomic_inc(&num_spurious);
- return;
- }
- if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
- break;
- }
-#else
- unsigned long sic_status;
-
- sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
+ } else {
+ sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
+ sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
+ }
+#endif
+#ifdef SIC_ISR2
+ sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
+#endif
- for (;; ivg++) {
- if (ivg >= ivg_stop) {
- atomic_inc(&num_spurious);
- return;
- } else if (sic_status & ivg->isrflag)
- break;
- }
+ for (;; ivg++) {
+ if (ivg >= ivg_stop)
+ return -1;
+#ifdef SIC_ISR
+ if (sic_status[0] & ivg->isrflag)
+#else
+ if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
#endif
- vec = ivg->irqno;
+ return ivg->irqno;
}
- asm_do_IRQ(vec, fp);
+}
+
+#ifdef CONFIG_DO_IRQ_L1
+__attribute__((l1_text))
+#endif
+void do_irq(int vec, struct pt_regs *fp)
+{
+ int irq = vec_to_irq(vec);
+ if (irq == -1)
+ return;
+ asm_do_IRQ(irq, fp);
}
#ifdef CONFIG_IPIPE
struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
int irq, s = 0;
- if (likely(vec == EVT_IVTMR_P))
- irq = IRQ_CORETMR;
- else {
-#if defined(SIC_ISR0)
- unsigned long sic_status[3];
-
- sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
- sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
-# ifdef SIC_ISR2
- sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
-# endif
- for (;; ivg++) {
- if (ivg >= ivg_stop) {
- atomic_inc(&num_spurious);
- return 0;
- }
- if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
- break;
- }
-#else
- unsigned long sic_status;
-
- sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
-
- for (;; ivg++) {
- if (ivg >= ivg_stop) {
- atomic_inc(&num_spurious);
- return 0;
- } else if (sic_status & ivg->isrflag)
- break;
- }
-#endif
- irq = ivg->irqno;
- }
+ irq = vec_to_irq(vec);
+ if (irq == -1)
+ return 0;
if (irq == IRQ_SYSTMR) {
#if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
#include <linux/slab.h>
#include <asm/atomic.h>
#include <asm/cacheflush.h>
+#include <asm/irq_handler.h>
#include <asm/mmu_context.h>
#include <asm/pgtable.h>
#include <asm/pgalloc.h>
dump_stack();
spin_unlock(&stop_lock);
- cpu_clear(cpu, cpu_online_map);
+ set_cpu_online(cpu, false);
local_irq_disable();
*/
resync_core_dcache();
#endif
- cpu_clear(cpu, *msg->call_struct.waitmask);
+ cpumask_clear_cpu(cpu, msg->call_struct.waitmask);
}
}
struct ipi_message_queue *msg_queue;
struct ipi_message *msg;
unsigned long flags, next_msg;
- cpumask_t waitmask = callmap; /* waitmask is shared by all cpus */
+ cpumask_t waitmask; /* waitmask is shared by all cpus */
- for_each_cpu_mask(cpu, callmap) {
+ cpumask_copy(&waitmask, &callmap);
+ for_each_cpu(cpu, &callmap) {
msg_queue = &per_cpu(ipi_msg_queue, cpu);
spin_lock_irqsave(&msg_queue->lock, flags);
if (msg_queue->count < BFIN_IPI_MSGQ_LEN) {
}
if (wait) {
- while (!cpus_empty(waitmask))
+ while (!cpumask_empty(&waitmask))
blackfin_dcache_invalidate_range(
(unsigned long)(&waitmask),
(unsigned long)(&waitmask));
cpumask_t callmap;
preempt_disable();
- callmap = cpu_online_map;
- cpu_clear(smp_processor_id(), callmap);
- if (!cpus_empty(callmap))
+ cpumask_copy(&callmap, cpu_online_mask);
+ cpumask_clear_cpu(smp_processor_id(), &callmap);
+ if (!cpumask_empty(&callmap))
smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
preempt_enable();
if (cpu_is_offline(cpu))
return 0;
- cpus_clear(callmap);
- cpu_set(cpu, callmap);
+ cpumask_clear(&callmap);
+ cpumask_set_cpu(cpu, &callmap);
smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
cpumask_t callmap;
preempt_disable();
- callmap = cpu_online_map;
- cpu_clear(smp_processor_id(), callmap);
- if (!cpus_empty(callmap))
+ cpumask_copy(&callmap, cpu_online_mask);
+ cpumask_clear_cpu(smp_processor_id(), &callmap);
+ if (!cpumask_empty(&callmap))
smp_send_message(callmap, BFIN_IPI_CPU_STOP, NULL, NULL, 0);
preempt_enable();
#include <linux/init.h>
#include <linux/poll.h>
#include <linux/proc_fs.h>
+#include <linux/seq_file.h>
#include <linux/spinlock.h>
#include <linux/rtc.h>
#include <linux/slab.h>
/* Need to keep line of output the same. Currently, that is 44 bytes
* (including newline).
*/
-static int _sram_proc_read(char *buf, int *len, int count, const char *desc,
+static int _sram_proc_show(struct seq_file *m, const char *desc,
struct sram_piece *pfree_head,
struct sram_piece *pused_head)
{
if (!pfree_head || !pused_head)
return -1;
- *len += sprintf(&buf[*len], "--- SRAM %-14s Size PID State \n", desc);
+ seq_printf(m, "--- SRAM %-14s Size PID State \n", desc);
/* search the relevant memory slot */
pslot = pused_head->next;
while (pslot != NULL) {
- *len += sprintf(&buf[*len], "%p-%p %10i %5i %-10s\n",
+ seq_printf(m, "%p-%p %10i %5i %-10s\n",
pslot->paddr, pslot->paddr + pslot->size,
pslot->size, pslot->pid, "ALLOCATED");
pslot = pfree_head->next;
while (pslot != NULL) {
- *len += sprintf(&buf[*len], "%p-%p %10i %5i %-10s\n",
+ seq_printf(m, "%p-%p %10i %5i %-10s\n",
pslot->paddr, pslot->paddr + pslot->size,
pslot->size, pslot->pid, "FREE");
return 0;
}
-static int sram_proc_read(char *buf, char **start, off_t offset, int count,
- int *eof, void *data)
+static int sram_proc_show(struct seq_file *m, void *v)
{
- int len = 0;
unsigned int cpu;
for (cpu = 0; cpu < num_possible_cpus(); ++cpu) {
- if (_sram_proc_read(buf, &len, count, "Scratchpad",
+ if (_sram_proc_show(m, "Scratchpad",
&per_cpu(free_l1_ssram_head, cpu), &per_cpu(used_l1_ssram_head, cpu)))
goto not_done;
#if L1_DATA_A_LENGTH != 0
- if (_sram_proc_read(buf, &len, count, "L1 Data A",
+ if (_sram_proc_show(m, "L1 Data A",
&per_cpu(free_l1_data_A_sram_head, cpu),
&per_cpu(used_l1_data_A_sram_head, cpu)))
goto not_done;
#endif
#if L1_DATA_B_LENGTH != 0
- if (_sram_proc_read(buf, &len, count, "L1 Data B",
+ if (_sram_proc_show(m, "L1 Data B",
&per_cpu(free_l1_data_B_sram_head, cpu),
&per_cpu(used_l1_data_B_sram_head, cpu)))
goto not_done;
#endif
#if L1_CODE_LENGTH != 0
- if (_sram_proc_read(buf, &len, count, "L1 Instruction",
+ if (_sram_proc_show(m, "L1 Instruction",
&per_cpu(free_l1_inst_sram_head, cpu),
&per_cpu(used_l1_inst_sram_head, cpu)))
goto not_done;
#endif
}
#if L2_LENGTH != 0
- if (_sram_proc_read(buf, &len, count, "L2", &free_l2_sram_head,
- &used_l2_sram_head))
+ if (_sram_proc_show(m, "L2", &free_l2_sram_head, &used_l2_sram_head))
goto not_done;
#endif
- *eof = 1;
not_done:
- return len;
+ return 0;
+}
+
+static int sram_proc_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, sram_proc_show, NULL);
}
+static const struct file_operations sram_proc_ops = {
+ .open = sram_proc_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
static int __init sram_proc_init(void)
{
struct proc_dir_entry *ptr;
- ptr = create_proc_entry("sram", S_IFREG | S_IRUGO, NULL);
+
+ ptr = proc_create("sram", S_IRUGO, NULL, &sram_proc_ops);
if (!ptr) {
printk(KERN_WARNING "unable to create /proc/sram\n");
return -1;
}
- ptr->read_proc = sram_proc_read;
return 0;
}
late_initcall(sram_proc_init);
git.openpandora.org / pandora-kernel.git / commitdiff