select HAVE_C_RECORDMCOUNT
select HAVE_GENERIC_HARDIRQS
select HAVE_SPARSE_IRQ
+ select GENERIC_IRQ_SHOW
help
The ARM series is a line of low-power-consumption RISC chip designs
licensed by ARM Ltd and targeted at embedded applications and
depends on !XIP_KERNEL && MMU
depends on !ARCH_REALVIEW || !SPARSEMEM
help
--- --- Patch phys-to-virt translation functions at runtime according to
--- --- the position of the kernel in system memory.
+++ +++ Patch phys-to-virt and virt-to-phys translation functions at
+++ +++ boot and module load time according to the position of the
+++ +++ kernel in system memory.
--- --- This can only be used with non-XIP with MMU kernels where
--- --- the base of physical memory is at a 16MB boundary.
+++ +++ This can only be used with non-XIP MMU kernels where the base
+++ +++ of physical memory is at a 16MB boundary, or theoretically 64K
+++ +++ for the MSM machine class.
config ARM_PATCH_PHYS_VIRT_16BIT
def_bool y
depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
+++ +++ help
+++ +++ This option extends the physical to virtual translation patching
+++ +++ to allow physical memory down to a theoretical minimum of 64K
+++ +++ boundaries.
source "init/Kconfig"
depends on MMU
select CPU_V6
select ARM_AMBA
++++++ select ARM_TIMER_SP804
select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS
select ARCH_WANT_OPTIONAL_GPIOLIB
select GENERIC_CLOCKEVENTS
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
++++++ select CLKSRC_MMIO
+ select HAVE_SCHED_CLOCK
help
Support for Freescale MXC/iMX-based family of processors
select GENERIC_CLOCKEVENTS
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
++++++ select CLKSRC_MMIO
help
Support for Freescale MXS-based family of processors
------config ARCH_STMP3XXX
------ bool "Freescale STMP3xxx"
------ select CPU_ARM926T
------ select CLKDEV_LOOKUP
------ select ARCH_REQUIRE_GPIOLIB
------ select GENERIC_CLOCKEVENTS
------ select USB_ARCH_HAS_EHCI
------ help
------ Support for systems based on the Freescale 3xxx CPUs.
------
config ARCH_NETX
bool "Hilscher NetX based"
++++++ select CLKSRC_MMIO
select CPU_ARM926T
select ARM_VIC
select GENERIC_CLOCKEVENTS
config ARCH_IXP4XX
bool "IXP4xx-based"
depends on MMU
++++++ select CLKSRC_MMIO
select CPU_XSCALE
select GENERIC_GPIO
select GENERIC_CLOCKEVENTS
config ARCH_LPC32XX
bool "NXP LPC32XX"
++++++ select CLKSRC_MMIO
select CPU_ARM926T
select ARCH_REQUIRE_GPIOLIB
select HAVE_IDE
Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
System-on-Chip devices.
----- -config ARCH_NS9XXX
----- - bool "NetSilicon NS9xxx"
----- - select CPU_ARM926T
----- - select GENERIC_GPIO
----- - select GENERIC_CLOCKEVENTS
----- - select HAVE_CLK
----- - help
----- - Say Y here if you intend to run this kernel on a NetSilicon NS9xxx
----- - System.
----- -
----- - <http://www.digi.com/products/microprocessors/index.jsp>
----- -
config ARCH_W90X900
bool "Nuvoton W90X900 CPU"
select CPU_ARM926T
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
++++++ select CLKSRC_MMIO
select GENERIC_CLOCKEVENTS
help
Support for Nuvoton (Winbond logic dept.) ARM9 processor,
config ARCH_TEGRA
bool "NVIDIA Tegra"
select CLKDEV_LOOKUP
++++++ select CLKSRC_MMIO
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
select GENERIC_GPIO
select ARCH_MTD_XIP
select ARCH_HAS_CPUFREQ
select CLKDEV_LOOKUP
++++++ select CLKSRC_MMIO
select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS
select HAVE_SCHED_CLOCK
config ARCH_SA1100
bool "SA1100-based"
++++++ select CLKSRC_MMIO
select CPU_SA1100
select ISA
select ARCH_SPARSEMEM_ENABLE
the Samsung SMDK2410 development board (and derivatives).
Note, the S3C2416 and the S3C2450 are so close that they even share
- the same SoC ID code. This means that there is no seperate machine
+ the same SoC ID code. This means that there is no separate machine
directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
config ARCH_S3C64XX
config ARCH_TCC_926
bool "Telechips TCC ARM926-based systems"
++++++ select CLKSRC_MMIO
select CPU_ARM926T
select HAVE_CLK
select CLKDEV_LOOKUP
config ARCH_U300
bool "ST-Ericsson U300 Series"
depends on MMU
++++++ select CLKSRC_MMIO
select CPU_ARM926T
select HAVE_SCHED_CLOCK
select HAVE_TCM
select ARM_AMBA
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
++++++ select CLKSRC_MMIO
select GENERIC_CLOCKEVENTS
select HAVE_CLK
help
source "arch/arm/mach-nomadik/Kconfig"
source "arch/arm/plat-nomadik/Kconfig"
----- -source "arch/arm/mach-ns9xxx/Kconfig"
----- -
source "arch/arm/mach-nuc93x/Kconfig"
source "arch/arm/plat-omap/Kconfig"
source "arch/arm/mach-shmobile/Kconfig"
------source "arch/arm/plat-stmp3xxx/Kconfig"
------
source "arch/arm/mach-tegra/Kconfig"
source "arch/arm/mach-u300/Kconfig"
config PLAT_ORION
bool
++++++ select CLKSRC_MMIO
select HAVE_SCHED_CLOCK
config PLAT_PXA
config ARM_TIMER_SP804
bool
++++++ select CLKSRC_MMIO
source arch/arm/mm/Kconfig
source "kernel/time/Kconfig"
config SMP
--- --- bool "Symmetric Multi-Processing (EXPERIMENTAL)"
--- --- depends on EXPERIMENTAL
+++ +++ bool "Symmetric Multi-Processing"
depends on CPU_V6K || CPU_V7
depends on GENERIC_CLOCKEVENTS
depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
def_bool ARCH_SPARSEMEM_ENABLE
config HIGHMEM
--- --- bool "High Memory Support (EXPERIMENTAL)"
--- --- depends on MMU && EXPERIMENTAL
+++ +++ bool "High Memory Support"
+++ +++ depends on MMU
help
The address space of ARM processors is only 4 Gigabytes large
and it has to accommodate user address space, kernel address
config HIGHPTE
bool "Allocate 2nd-level pagetables from highmem"
depends on HIGHMEM
- depends on !OUTER_CACHE
config HW_PERF_EVENTS
bool "Enable hardware performance counter support for perf events"
time by entering them here. As a minimum, you should specify the
memory size and the root device (e.g., mem=64M root=/dev/nfs).
+++ +++choice
+++ +++ prompt "Kernel command line type" if CMDLINE != ""
+++ +++ default CMDLINE_FROM_BOOTLOADER
+++ +++
+++ +++config CMDLINE_FROM_BOOTLOADER
+++ +++ bool "Use bootloader kernel arguments if available"
+++ +++ help
+++ +++ Uses the command-line options passed by the boot loader. If
+++ +++ the boot loader doesn't provide any, the default kernel command
+++ +++ string provided in CMDLINE will be used.
+++ +++
+++ +++config CMDLINE_EXTEND
+++ +++ bool "Extend bootloader kernel arguments"
+++ +++ help
+++ +++ The command-line arguments provided by the boot loader will be
+++ +++ appended to the default kernel command string.
+++ +++
config CMDLINE_FORCE
bool "Always use the default kernel command string"
--- --- depends on CMDLINE != ""
help
Always use the default kernel command string, even if the boot
loader passes other arguments to the kernel.
This is useful if you cannot or don't want to change the
command-line options your boot loader passes to the kernel.
--- ---
--- --- If unsure, say N.
+++ +++endchoice
config XIP_KERNEL
bool "Kernel Execute-In-Place from ROM"
source "kernel/power/Kconfig"
config ARCH_SUSPEND_POSSIBLE
-- --- depends on !ARCH_S5P64X0 && !ARCH_S5P6442
++ ++++ depends on !ARCH_S5P64X0 && !ARCH_S5P6442 && !ARCH_S5PC100
+ depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
+ CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
def_bool y
endmenu
#if defined(CONFIG_DEBUG_ICEDCC)
-#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
+#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
.macro loadsp, rb, tmp
.endm
.macro writeb, ch, rb
mcr p14, 0, \ch, c0, c5, 0
.endm
-#elif defined(CONFIG_CPU_V7)
- .macro loadsp, rb, tmp
- .endm
- .macro writeb, ch, rb
-wait: mrc p14, 0, pc, c0, c1, 0
- bcs wait
- mcr p14, 0, \ch, c0, c5, 0
- .endm
#elif defined(CONFIG_CPU_XSCALE)
.macro loadsp, rb, tmp
.endm
bl cache_on
restart: adr r0, LC0
- ---- ldmia r0, {r1, r2, r3, r5, r6, r9, r11, r12}
- ---- ldr sp, [r0, #32]
+ ++++ ldmia r0, {r1, r2, r3, r6, r9, r11, r12}
+ ++++ ldr sp, [r0, #28]
/*
* We might be running at a different address. We need
* to fix up various pointers.
*/
sub r0, r0, r1 @ calculate the delta offset
- ---- add r5, r5, r0 @ _start
add r6, r6, r0 @ _edata
#ifndef CONFIG_ZBOOT_ROM
/*
* Check to see if we will overwrite ourselves.
* r4 = final kernel address
- ---- * r5 = start of this image
* r9 = size of decompressed image
* r10 = end of this image, including bss/stack/malloc space if non XIP
* We basically want:
- ---- * r4 >= r10 -> OK
- ---- * r4 + image length <= r5 -> OK
+ ++++ * r4 - 16k page directory >= r10 -> OK
+ ++++ * r4 + image length <= current position (pc) -> OK
*/
+ ++++ add r10, r10, #16384
cmp r4, r10
bhs wont_overwrite
add r10, r4, r9
- ---- cmp r10, r5
+ ++++ ARM( cmp r10, pc )
+ ++++ THUMB( mov lr, pc )
+ ++++ THUMB( cmp r10, lr )
bls wont_overwrite
/*
* Relocate ourselves past the end of the decompressed kernel.
- ---- * r5 = start of this image
* r6 = _edata
* r10 = end of the decompressed kernel
* Because we always copy ahead, we need to do it from the end and go
* backward in case the source and destination overlap.
*/
- ---- /* Round up to next 256-byte boundary. */
- ---- add r10, r10, #256
+ ++++ /*
+ ++++ * Bump to the next 256-byte boundary with the size of
+ ++++ * the relocation code added. This avoids overwriting
+ ++++ * ourself when the offset is small.
+ ++++ */
+ ++++ add r10, r10, #((reloc_code_end - restart + 256) & ~255)
bic r10, r10, #255
+ ++++ /* Get start of code we want to copy and align it down. */
+ ++++ adr r5, restart
+ ++++ bic r5, r5, #31
+ ++++
sub r9, r6, r5 @ size to copy
add r9, r9, #31 @ rounded up to a multiple
bic r9, r9, #31 @ ... of 32 bytes
/* Preserve offset to relocated code. */
sub r6, r9, r6
+ ++++#ifndef CONFIG_ZBOOT_ROM
+ ++++ /* cache_clean_flush may use the stack, so relocate it */
+ ++++ add sp, sp, r6
+ ++++#endif
+ ++++
bl cache_clean_flush
adr r0, BSYM(restart)
LC0: .word LC0 @ r1
.word __bss_start @ r2
.word _end @ r3
- ---- .word _start @ r5
.word _edata @ r6
.word _image_size @ r9
.word _got_start @ r11
orr r1, r1, #3 << 10
add r2, r3, #16384
1: cmp r1, r9 @ if virt > start of RAM
+++ +++#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+++ +++ orrhs r1, r1, #0x08 @ set cacheable
+++ +++#else
orrhs r1, r1, #0x0c @ set cacheable, bufferable
+++ +++#endif
cmp r1, r10 @ if virt > end of RAM
bichs r1, r1, #0x0c @ clear cacheable, bufferable
str r1, [r0], #4 @ 1:1 mapping
mov pc, lr
ENDPROC(__setup_mmu)
+++ +++__arm926ejs_mmu_cache_on:
+++ +++#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+++ +++ mov r0, #4 @ put dcache in WT mode
+++ +++ mcr p15, 7, r0, c15, c0, 0
+++ +++#endif
+++ +++
__armv4_mmu_cache_on:
mov r12, lr
#ifdef CONFIG_MMU
W(b) __armv4_mpu_cache_on
W(b) __armv4_mpu_cache_off
W(b) __armv4_mpu_cache_flush
+ +
+++ +++ .word 0x41069260 @ ARM926EJ-S (v5TEJ)
+++ +++ .word 0xff0ffff0
+++ +++ b __arm926ejs_mmu_cache_on
+++ +++ b __armv4_mmu_cache_off
+++ +++ b __armv5tej_mmu_cache_flush
+ +++
.word 0x00007000 @ ARM7 IDs
.word 0x0000f000
mov pc, lr
#endif
.ltorg
+ ++++reloc_code_end:
.align
.section ".stack", "aw", %nobits
git.openpandora.org / pandora-kernel.git / commitdiff