[ARM] 4786/1: S3C2412: Add SPI FIFO controll constants

Add control constants for the S3C2412 SPI unit FIFO.

Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/include/asm-arm/plat-s3c24xx/regs-spi.h b/include/asm-arm/plat-s3c24xx/regs-spi.h
index 960907f..ea565b0 100644 (file)
--- a/include/asm-arm/plat-s3c24xx/regs-spi.h
+++ b/include/asm-arm/plat-s3c24xx/regs-spi.h
@@ -17,7 +17,21 @@
 
 #define S3C2410_SPCON  (0x00)
 
+#define S3C2412_SPCON_RXFIFO_RB2       (0<<14)
+#define S3C2412_SPCON_RXFIFO_RB4       (1<<14)
+#define S3C2412_SPCON_RXFIFO_RB12      (2<<14)
+#define S3C2412_SPCON_RXFIFO_RB14      (3<<14)
+#define S3C2412_SPCON_TXFIFO_RB2       (0<<12)
+#define S3C2412_SPCON_TXFIFO_RB4       (1<<12)
+#define S3C2412_SPCON_TXFIFO_RB12      (2<<12)
+#define S3C2412_SPCON_TXFIFO_RB14      (3<<12)
+#define S3C2412_SPCON_RXFIFO_RESET     (1<<11) /* RxFIFO reset */
+#define S3C2412_SPCON_TXFIFO_RESET     (1<<10) /* TxFIFO reset */
+#define S3C2412_SPCON_RXFIFO_EN                (1<<9)  /* RxFIFO Enable */
+#define S3C2412_SPCON_TXFIFO_EN                (1<<8)  /* TxFIFO Enable */
+
 #define S3C2412_SPCON_DIRC_RX    (1<<7)
+
 #define S3C2410_SPCON_SMOD_DMA   (2<<5)        /* DMA mode */
 #define S3C2410_SPCON_SMOD_INT   (1<<5)        /* interrupt mode */
 #define S3C2410_SPCON_SMOD_POLL   (0<<5)       /* polling mode */
@@ -35,6 +49,15 @@
 
 #define S3C2410_SPSTA   (0x04)
 
+#define S3C2412_SPSTA_RXFIFO_AE                (1<<11)
+#define S3C2412_SPSTA_TXFIFO_AE                (1<<10)
+#define S3C2412_SPSTA_RXFIFO_ERROR     (1<<9)
+#define S3C2412_SPSTA_TXFIFO_ERROR     (1<<8)
+#define S3C2412_SPSTA_RXFIFO_FIFO      (1<<7)
+#define S3C2412_SPSTA_RXFIFO_EMPTY     (1<<6)
+#define S3C2412_SPSTA_TXFIFO_NFULL     (1<<5)
+#define S3C2412_SPSTA_TXFIFO_EMPTY     (1<<4)
+
 #define S3C2410_SPSTA_DCOL       (1<<2)        /* Data Collision Error */
 #define S3C2410_SPSTA_MULD       (1<<1)        /* Multi Master Error */
 #define S3C2410_SPSTA_READY      (1<<0)        /* Data Tx/Rx ready */