drm/i915: split refclk code out of ironlake_crtc_mode_set

Just a cleanup to make the mode_set function more manageable.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-By: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-By: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Keith Packard <keithp@keithp.com>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6b1a1ed..3b62b91 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5241,6 +5241,40 @@ void ironlake_init_pch_refclk(struct drm_device *dev)
        }
 }
 
+static int ironlake_get_refclk(struct drm_crtc *crtc)
+{
+       struct drm_device *dev = crtc->dev;
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       struct intel_encoder *encoder;
+       struct drm_mode_config *mode_config = &dev->mode_config;
+       struct intel_encoder *edp_encoder = NULL;
+       int num_connectors = 0;
+       bool is_lvds = false;
+
+       list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
+               if (encoder->base.crtc != crtc)
+                       continue;
+
+               switch (encoder->type) {
+               case INTEL_OUTPUT_LVDS:
+                       is_lvds = true;
+                       break;
+               case INTEL_OUTPUT_EDP:
+                       edp_encoder = encoder;
+                       break;
+               }
+               num_connectors++;
+       }
+
+       if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
+               DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
+                             dev_priv->lvds_ssc_freq);
+               return dev_priv->lvds_ssc_freq * 1000;
+       }
+
+       return 120000;
+}
+
 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
                                  struct drm_display_mode *mode,
                                  struct drm_display_mode *adjusted_mode,
@@ -5300,10 +5334,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
                num_connectors++;
        }
 
-       /*
-        * Every reference clock in a PCH system is 120MHz
-        */
-       refclk = 120000;
+       refclk = ironlake_get_refclk(crtc);
 
        /*
         * Returns a set of divisors for the desired target clock with the given