drm/i915: set watermarks for third pipe on IVB

The watermark reg for the third pipe is in an unusual offset; add
support for it and set watermarks for 3 pipe configs.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-By: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-By: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Keith Packard <keithp@keithp.com>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c7ef323..5a09416 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2435,6 +2435,7 @@
 #define  WM0_PIPE_CURSOR_MASK  (0x1f)
 
 #define WM0_PIPEB_ILK          0x45104
+#define WM0_PIPEC_IVB          0x45200
 #define WM1_LP_ILK             0x45108
 #define  WM1_LP_SR_EN          (1<<31)
 #define  WM1_LP_LATENCY_SHIFT  24

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ad3a018..064c659 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4540,6 +4540,20 @@ static void sandybridge_update_wm(struct drm_device *dev)
                enabled |= 2;
        }
 
+       /* IVB has 3 pipes */
+       if (IS_IVYBRIDGE(dev) &&
+           g4x_compute_wm0(dev, 2,
+                           &sandybridge_display_wm_info, latency,
+                           &sandybridge_cursor_wm_info, latency,
+                           &plane_wm, &cursor_wm)) {
+               I915_WRITE(WM0_PIPEC_IVB,
+                          (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
+               DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
+                             " plane %d, cursor: %d\n",
+                             plane_wm, cursor_wm);
+               enabled |= 3;
+       }
+
        /*
         * Calculate and update the self-refresh watermark only when one
         * display plane is used.