drm/i915: tune Sandy Bridge DRPS constants

These make us increase our frequency much more readily, and decrease
them only after significant idle time, resulting in a 20% performance
increase for nexuiz.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index c31e818..5825a58 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -862,19 +862,44 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused)
                u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
                u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
                u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
+               u32 rpstat;
+               u32 rpupei, rpcurup, rpprevup;
+               u32 rpdownei, rpcurdown, rpprevdown;
                int max_freq;
 
                /* RPSTAT1 is in the GT power well */
                __gen6_force_wake_get(dev_priv);
 
+               rpstat = I915_READ(GEN6_RPSTAT1);
+               rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
+               rpcurup = I915_READ(GEN6_RP_CUR_UP);
+               rpprevup = I915_READ(GEN6_RP_PREV_UP);
+               rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
+               rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
+               rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
+
                seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
-               seq_printf(m, "RPSTAT1: 0x%08x\n", I915_READ(GEN6_RPSTAT1));
+               seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
                seq_printf(m, "Render p-state ratio: %d\n",
                           (gt_perf_status & 0xff00) >> 8);
                seq_printf(m, "Render p-state VID: %d\n",
                           gt_perf_status & 0xff);
                seq_printf(m, "Render p-state limit: %d\n",
                           rp_state_limits & 0xff);
+               seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >>
+                                               GEN6_CAGF_SHIFT) * 100);
+               seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
+                          GEN6_CURICONT_MASK);
+               seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
+                          GEN6_CURBSYTAVG_MASK);
+               seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
+                          GEN6_CURBSYTAVG_MASK);
+               seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
+                          GEN6_CURIAVG_MASK);
+               seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
+                          GEN6_CURBSYTAVG_MASK);
+               seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
+                          GEN6_CURBSYTAVG_MASK);
 
                max_freq = (rp_state_cap & 0xff0000) >> 16;
                seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e6b106b..810cfa8 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3283,15 +3283,28 @@
 #define GEN6_RP_DOWN_TIMEOUT                   0xA010
 #define GEN6_RP_INTERRUPT_LIMITS               0xA014
 #define GEN6_RPSTAT1                           0xA01C
+#define   GEN6_CAGF_SHIFT                      8
+#define   GEN6_CAGF_MASK                       (0x7f << GEN6_CAGF_SHIFT)
 #define GEN6_RP_CONTROL                                0xA024
 #define   GEN6_RP_MEDIA_TURBO                  (1<<11)
 #define   GEN6_RP_USE_NORMAL_FREQ              (1<<9)
 #define   GEN6_RP_MEDIA_IS_GFX                 (1<<8)
 #define   GEN6_RP_ENABLE                       (1<<7)
-#define   GEN6_RP_UP_BUSY_MAX                  (0x2<<3)
-#define   GEN6_RP_DOWN_BUSY_MIN                        (0x2<<0)
+#define   GEN6_RP_UP_IDLE_MIN                  (0x1<<3)
+#define   GEN6_RP_UP_BUSY_AVG                  (0x2<<3)
+#define   GEN6_RP_UP_BUSY_CONT                 (0x4<<3)
+#define   GEN6_RP_DOWN_IDLE_CONT               (0x1<<0)
 #define GEN6_RP_UP_THRESHOLD                   0xA02C
 #define GEN6_RP_DOWN_THRESHOLD                 0xA030
+#define GEN6_RP_CUR_UP_EI                      0xA050
+#define   GEN6_CURICONT_MASK                   0xffffff
+#define GEN6_RP_CUR_UP                         0xA054
+#define   GEN6_CURBSYTAVG_MASK                 0xffffff
+#define GEN6_RP_PREV_UP                                0xA058
+#define GEN6_RP_CUR_DOWN_EI                    0xA05C
+#define   GEN6_CURIAVG_MASK                    0xffffff
+#define GEN6_RP_CUR_DOWN                       0xA060
+#define GEN6_RP_PREV_DOWN                      0xA064
 #define GEN6_RP_UP_EI                          0xA068
 #define GEN6_RP_DOWN_EI                                0xA06C
 #define GEN6_RP_IDLE_HYSTERSIS                 0xA070

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index cb9d547..a90d65d 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6630,18 +6630,18 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
        I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
                   18 << 24 |
                   6 << 16);
-       I915_WRITE(GEN6_RP_UP_THRESHOLD, 90000);
-       I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 100000);
+       I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
+       I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
        I915_WRITE(GEN6_RP_UP_EI, 100000);
-       I915_WRITE(GEN6_RP_DOWN_EI, 300000);
+       I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
        I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
        I915_WRITE(GEN6_RP_CONTROL,
                   GEN6_RP_MEDIA_TURBO |
                   GEN6_RP_USE_NORMAL_FREQ |
                   GEN6_RP_MEDIA_IS_GFX |
                   GEN6_RP_ENABLE |
-                  GEN6_RP_UP_BUSY_MAX |
-                  GEN6_RP_DOWN_BUSY_MIN);
+                  GEN6_RP_UP_BUSY_AVG |
+                  GEN6_RP_DOWN_IDLE_CONT);
 
        if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
                     500))