ARM: Add option to allow userspace PLE access

This adds a Kconfig option to allow userspace to access the L2 preload
engine (PLE) found in Cortex-A8.

Signed-off-by: Mans Rullgard <mans@mansr.com>

diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index bff4c6e..8d82e13 100644 (file)
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -166,6 +166,10 @@ __enable_mmu:
 #endif
 #ifdef CONFIG_CPU_ICACHE_DISABLE
        bic     r0, r0, #CR_I
+#endif
+#ifdef CONFIG_USER_L2_PLE
+       mov     r5, #3
+       mcr     p15, 0, r5, c11, c1, 0
 #endif
        mov     r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
                      domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 546d7e7..bd45c28 100644 (file)
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -750,3 +750,11 @@ config CACHE_XSC3L2
        select OUTER_CACHE
        help
          This option enables the L2 cache on XScale3.
+
+config USER_L2_PLE
+       bool "Enable userspace access to the L2 PLE"
+       depends on CPU_V7
+       default n
+       help
+         Enable userspace access to the L2 preload engine (PLE) available
+         in Cortex-A series ARM processors.