Merge branch 'master' into sh/smp

Conflicts:
	arch/sh/mm/cache-sh4.c

diff --cc arch/sh/include/asm/processor.h
Simple merge

diff --cc arch/sh/include/asm/system.h
Simple merge

diff --cc arch/sh/include/asm/system_32.h
index 5ddd235,d3ab269..607d413
--- 1/arch/sh/include/asm/system_32.h
--- 2/arch/sh/include/asm/system_32.h
+++ b/arch/sh/include/asm/system_32.h
@@@ -208,13 -198,8 +208,13 @@@ do {                                                     
  })
  #endif
  
 +static inline reg_size_t register_align(void *val)
 +{
 +      return (unsigned long)(signed long)val;
 +}
 +
  int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
-                           struct mem_access *ma);
+                           struct mem_access *ma, int);
  
  asmlinkage void do_address_error(struct pt_regs *regs,
                                 unsigned long writeaccess,

diff --cc arch/sh/kernel/cpu/sh3/entry.S
Simple merge

diff --cc arch/sh/kernel/cpu/sh4/probe.c
Simple merge

diff --cc arch/sh/kernel/setup.c
Simple merge

diff --cc arch/sh/lib/__clear_user.S
Simple merge

diff --cc arch/sh/mm/cache-sh4.c
index 2775f84,b36a9c9..70fb906
--- 1/arch/sh/mm/cache-sh4.c
--- 2/arch/sh/mm/cache-sh4.c
+++ b/arch/sh/mm/cache-sh4.c
@@@ -647,41 -824,3 +689,47 @@@ static void __flush_dcache_segment_4way
                a3 += linesz;
        } while (a0 < a0e);
  }
-       switch (boot_cpu_data.dcache.ways) {
-       case 1:
-               __flush_dcache_segment_fn = __flush_dcache_segment_1way;
-               break;
-       case 2:
-               __flush_dcache_segment_fn = __flush_dcache_segment_2way;
-               break;
-       case 4:
-               __flush_dcache_segment_fn = __flush_dcache_segment_4way;
-               break;
-       default:
-               panic("unknown number of cache ways\n");
-               break;
 +
 +extern void __weak sh4__flush_region_init(void);
 +
 +/*
 + * SH-4 has virtually indexed and physically tagged cache.
 + */
 +void __init sh4_cache_init(void)
 +{
++      unsigned int wt_enabled = !!(__raw_readl(CCR) & CCR_CACHE_WT);
++
 +      printk("PVR=%08x CVR=%08x PRR=%08x\n",
 +              ctrl_inl(CCN_PVR),
 +              ctrl_inl(CCN_CVR),
 +              ctrl_inl(CCN_PRR));
 +
++      if (wt_enabled)
++              __flush_dcache_segment_fn = __flush_dcache_segment_writethrough;
++      else {
++              switch (boot_cpu_data.dcache.ways) {
++              case 1:
++                      __flush_dcache_segment_fn = __flush_dcache_segment_1way;
++                      break;
++              case 2:
++                      __flush_dcache_segment_fn = __flush_dcache_segment_2way;
++                      break;
++              case 4:
++                      __flush_dcache_segment_fn = __flush_dcache_segment_4way;
++                      break;
++              default:
++                      panic("unknown number of cache ways\n");
++                      break;
++              }
 +      }
 +
 +      local_flush_icache_range        = sh4_flush_icache_range;
 +      local_flush_dcache_page         = sh4_flush_dcache_page;
 +      local_flush_cache_all           = sh4_flush_cache_all;
 +      local_flush_cache_mm            = sh4_flush_cache_mm;
 +      local_flush_cache_dup_mm        = sh4_flush_cache_mm;
 +      local_flush_cache_page          = sh4_flush_cache_page;
 +      local_flush_cache_range         = sh4_flush_cache_range;
 +
 +      sh4__flush_region_init();
 +}

diff --cc arch/sh/mm/tlb-sh4.c
Simple merge