drm/radeon: update ib_execute for SI (v2)

When submitting a CONST_IB, emit a SWITCH_BUFFER
packet before the CONST_IB.  This isn't strictly necessary
(the driver will work fine without it), but is good practice
and allows for more flexible DE/CE sychronization options
in the future.  Current userspace drivers do not take
advantage of the CE yet.

v2: - clean up code flow a bit
    - no need to flush caches for CONST IB

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 53e313b..2b12cae 100644 (file)
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -1765,18 +1765,23 @@ void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
        struct radeon_ring *ring = &rdev->ring[ib->ring];
        u32 header;
 
-       if (ring->rptr_save_reg) {
-               uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
-               radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
-               radeon_ring_write(ring, ((ring->rptr_save_reg - 
-                                         PACKET3_SET_CONFIG_REG_START) >> 2));
-               radeon_ring_write(ring, next_rptr);
-       }
+       if (ib->is_const_ib) {
+               /* set switch buffer packet before const IB */
+               radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
+               radeon_ring_write(ring, 0);
 
-       if (ib->is_const_ib)
                header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
-       else
+       } else {
+               if (ring->rptr_save_reg) {
+                       uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
+                       radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+                       radeon_ring_write(ring, ((ring->rptr_save_reg -
+                                                 PACKET3_SET_CONFIG_REG_START) >> 2));
+                       radeon_ring_write(ring, next_rptr);
+               }
+
                header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
+       }
 
        radeon_ring_write(ring, header);
        radeon_ring_write(ring,
@@ -1787,18 +1792,20 @@ void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
        radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
        radeon_ring_write(ring, ib->length_dw | (ib->vm_id << 24));
 
-       /* flush read cache over gart for this vmid */
-       radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
-       radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
-       radeon_ring_write(ring, ib->vm_id);
-       radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
-       radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
-                         PACKET3_TC_ACTION_ENA |
-                         PACKET3_SH_KCACHE_ACTION_ENA |
-                         PACKET3_SH_ICACHE_ACTION_ENA);
-       radeon_ring_write(ring, 0xFFFFFFFF);
-       radeon_ring_write(ring, 0);
-       radeon_ring_write(ring, 10); /* poll interval */
+       if (!ib->is_const_ib) {
+               /* flush read cache over gart for this vmid */
+               radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+               radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
+               radeon_ring_write(ring, ib->vm_id);
+               radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
+               radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
+                                 PACKET3_TC_ACTION_ENA |
+                                 PACKET3_SH_KCACHE_ACTION_ENA |
+                                 PACKET3_SH_ICACHE_ACTION_ENA);
+               radeon_ring_write(ring, 0xFFFFFFFF);
+               radeon_ring_write(ring, 0);
+               radeon_ring_write(ring, 10); /* poll interval */
+       }
 }
 
 /*

diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index db40679..7869089 100644 (file)
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -901,5 +901,6 @@
 #define        PACKET3_WAIT_ON_DE_COUNTER_DIFF                 0x88
 #define        PACKET3_SET_CE_DE_COUNTERS                      0x89
 #define        PACKET3_WAIT_ON_AVAIL_BUFFER                    0x8A
+#define        PACKET3_SWITCH_BUFFER                           0x8B
 
 #endif