Merge branch 'fix' of git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux...

diff --combined arch/arm/Kconfig
index e8cbecc,fdc9d4d..377a7a5
--- 1/arch/arm/Kconfig
--- 2/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@@ -694,7 -694,7 +694,7 @@@ config ARCH_S3C241
          the Samsung SMDK2410 development board (and derivatives).
  
          Note, the S3C2416 and the S3C2450 are so close that they even share
-         the same SoC ID code. This means that there is no seperate machine
+         the same SoC ID code. This means that there is no separate machine
          directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
  
  config ARCH_S3C64XX
@@@ -1540,6 -1540,7 +1540,6 @@@ config HIGHME
  config HIGHPTE
        bool "Allocate 2nd-level pagetables from highmem"
        depends on HIGHMEM
 -      depends on !OUTER_CACHE
  
  config HW_PERF_EVENTS
        bool "Enable hardware performance counter support for perf events"
@@@ -2011,8 -2012,6 +2011,8 @@@ source "kernel/power/Kconfig
  
  config ARCH_SUSPEND_POSSIBLE
        depends on !ARCH_S5P64X0 && !ARCH_S5P6442
 +      depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
 +              CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
        def_bool y
  
  endmenu

diff --combined arch/arm/mm/proc-arm920.S
index 394b623,b46eb21..bf8a1d1
--- 1/arch/arm/mm/proc-arm920.S
--- 2/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@@ -53,7 -53,7 +53,7 @@@
  /*
   * This is the size at which it becomes more efficient to
   * clean the whole cache, rather than using the individual
-  * cache line maintainence instructions.
+  * cache line maintenance instructions.
   */
  #define CACHE_DLIMIT  65536
  
@@@ -390,7 -390,7 +390,7 @@@ ENTRY(cpu_arm920_set_pte_ext
  /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
  .globl        cpu_arm920_suspend_size
  .equ  cpu_arm920_suspend_size, 4 * 3
 -#ifdef CONFIG_PM
 +#ifdef CONFIG_PM_SLEEP
  ENTRY(cpu_arm920_do_suspend)
        stmfd   sp!, {r4 - r7, lr}
        mrc     p15, 0, r4, c13, c0, 0  @ PID

diff --combined arch/arm/mm/proc-v6.S
index 3874412,bfa0c9f..7c99cb4
--- 1/arch/arm/mm/proc-v6.S
--- 2/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@@ -124,7 -124,7 +124,7 @@@ ENTRY(cpu_v6_set_pte_ext
  /* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */
  .globl        cpu_v6_suspend_size
  .equ  cpu_v6_suspend_size, 4 * 8
 -#ifdef CONFIG_PM
 +#ifdef CONFIG_PM_SLEEP
  ENTRY(cpu_v6_do_suspend)
        stmfd   sp!, {r4 - r11, lr}
        mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
@@@ -132,7 -132,7 +132,7 @@@
        mrc     p15, 0, r6, c3, c0, 0   @ Domain ID
        mrc     p15, 0, r7, c2, c0, 0   @ Translation table base 0
        mrc     p15, 0, r8, c2, c0, 1   @ Translation table base 1
-       mrc     p15, 0, r9, c1, c0, 1   @ auxillary control register
+       mrc     p15, 0, r9, c1, c0, 1   @ auxiliary control register
        mrc     p15, 0, r10, c1, c0, 2  @ co-processor access control
        mrc     p15, 0, r11, c1, c0, 0  @ control register
        stmia   r0, {r4 - r11}
@@@ -151,7 -151,7 +151,7 @@@ ENTRY(cpu_v6_do_resume
        mcr     p15, 0, r6, c3, c0, 0   @ Domain ID
        mcr     p15, 0, r7, c2, c0, 0   @ Translation table base 0
        mcr     p15, 0, r8, c2, c0, 1   @ Translation table base 1
-       mcr     p15, 0, r9, c1, c0, 1   @ auxillary control register
+       mcr     p15, 0, r9, c1, c0, 1   @ auxiliary control register
        mcr     p15, 0, r10, c1, c0, 2  @ co-processor access control
        mcr     p15, 0, ip, c2, c0, 2   @ TTB control register
        mcr     p15, 0, ip, c7, c5, 4   @ ISB

diff --combined arch/arm/mm/proc-v7.S
index 713cea1,c35618e..babfba0
--- 1/arch/arm/mm/proc-v7.S
--- 2/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@@ -211,7 -211,7 +211,7 @@@ cpu_v7_name
  /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
  .globl        cpu_v7_suspend_size
  .equ  cpu_v7_suspend_size, 4 * 8
 -#ifdef CONFIG_PM
 +#ifdef CONFIG_PM_SLEEP
  ENTRY(cpu_v7_do_suspend)
        stmfd   sp!, {r4 - r11, lr}
        mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
@@@ -237,7 -237,7 +237,7 @@@ ENTRY(cpu_v7_do_resume
        mcr     p15, 0, r7, c2, c0, 0   @ TTB 0
        mcr     p15, 0, r8, c2, c0, 1   @ TTB 1
        mcr     p15, 0, ip, c2, c0, 2   @ TTB control register
-       mcr     p15, 0, r10, c1, c0, 1  @ Auxillary control register
+       mcr     p15, 0, r10, c1, c0, 1  @ Auxiliary control register
        mcr     p15, 0, r11, c1, c0, 2  @ Co-processor access control
        ldr     r4, =PRRR               @ PRRR
        ldr     r5, =NMRR               @ NMRR