* 'for-linus' of master.kernel.org:/pub/scm/linux/kernel/git/cooloney/blackfin-2.6:
Input Serio: Blackfin doesnt support I8042 - make sure it doesnt get selected
Blackfin arch: add BF54x I2C/TWI TWI0 driver support
Blackfin On-Chip RTC driver update for supporting BF54x
Blackfin Ethernet MAC driver: fix bug Report returned -ENOMEM upwards (in case L1/uncached memory alloc fails)
Blackfin arch: add error message when IRQ no available
Blackfin arch: Initialize the exception vectors early in the boot process
Blackfin arch: fix a compiling warning about dma-mapping
Blackfin arch: switch to using proper defines this time THREAD_SIZE and PAGE_SIZE instead of just PAGE_SIZE everywhere
Blackfin arch: fix bug which unaligns the init thread's stack and causes the current macro to fail.
Blackfin arch: Load P0 before storing through it
Blackfin arch: fix KGDB bug, dont forget last parameter.
Blackfin arch: add selections for BF544 and BF542
Blackfin arch: use bfin_read_SWRST() now that BF561 provides it
Blackfin arch: setup aliases for some core Core A MMRs
machine-$(CONFIG_BF534) := bf537
machine-$(CONFIG_BF536) := bf537
machine-$(CONFIG_BF537) := bf537
+machine-$(CONFIG_BF542) := bf548
+machine-$(CONFIG_BF544) := bf548
machine-$(CONFIG_BF548) := bf548
machine-$(CONFIG_BF549) := bf548
machine-$(CONFIG_BF561) := bf561
cpu-$(CONFIG_BF534) := bf534
cpu-$(CONFIG_BF536) := bf536
cpu-$(CONFIG_BF537) := bf537
+cpu-$(CONFIG_BF542) := bf542
+cpu-$(CONFIG_BF544) := bf544
cpu-$(CONFIG_BF548) := bf548
cpu-$(CONFIG_BF549) := bf549
cpu-$(CONFIG_BF561) := bf561
BUG_ON(direction == DMA_NONE);
for (i = 0; i < nents; i++, sg++) {
- sg->dma_address = page_address(sg->page) + sg->offset;
+ sg->dma_address = (dma_addr_t)(page_address(sg->page) +
+ sg->offset);
invalidate_dcache_range(sg_dma_address(sg),
sg_dma_address(sg) +
if (l1_length > L1_DATA_A_LENGTH)
panic("L1 data memory overflow\n");
-#ifdef BF561_FAMILY
- _bfin_swrst = bfin_read_SICA_SWRST();
-#else
_bfin_swrst = bfin_read_SWRST();
-#endif
/* Copy atomic sequences to their fixed location, and sanity check that
these locations are the ones that we advertise to userspace. */
BUG_ON((char *)&atomic_xor32 - (char *)&fixed_code_start
!= ATOMIC_XOR32 - FIXED_CODE_START);
+ init_exception_vectors();
bf53x_cache_init();
}
#ifdef CONFIG_KGDB
# define CHK_DEBUGGER_TRAP() \
do { \
- CHK_DEBUGGER(trapnr, sig, info.si_code, fp); \
+ CHK_DEBUGGER(trapnr, sig, info.si_code, fp, ); \
} while (0)
# define CHK_DEBUGGER_TRAP_MAYBE() \
do { \
#include <asm-generic/vmlinux.lds.h>
#include <asm/mem_map.h>
#include <asm/page.h>
+#include <asm/thread_info.h>
OUTPUT_FORMAT("elf32-bfin")
ENTRY(__start)
.data :
{
- . = ALIGN(PAGE_SIZE);
+ /* make sure the init_task is aligned to the
+ * kernel thread size so we can locate the kernel
+ * stack properly and quickly.
+ */
__sdata = .;
+ . = ALIGN(THREAD_SIZE);
*(.data.init_task)
DATA_DATA
CONSTRUCTORS
. = ALIGN(32);
*(.data.cacheline_aligned)
- . = ALIGN(PAGE_SIZE);
+ . = ALIGN(THREAD_SIZE);
__edata = .;
}
- . = ALIGN(PAGE_SIZE);
___init_begin = .;
.init :
{
+ . = ALIGN(PAGE_SIZE);
__sinittext = .;
*(.init.text)
__einittext = .;
__ebss_b_l1 = .;
}
- . = LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1);
- ___init_end = ALIGN(PAGE_SIZE);
+ ___init_end = LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1);
- .bss ___init_end :
+ .bss LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1) :
{
. = ALIGN(4);
___bss_start = .;
SSYNC;
/* make sure SYSCR is set to use BMODE */
- P0.h = hi(SICA_SYSCR);
- P0.l = lo(SICA_SYSCR);
- R0.l = 0x20;
+ P0.h = hi(SYSCR);
+ P0.l = lo(SYSCR);
+ R0.l = 0x20; /* on BF561, disable core b */
W[P0] = R0.l;
SSYNC;
/* issue a system soft reset */
- P1.h = hi(SICA_SWRST);
- P1.l = lo(SICA_SWRST);
+ P1.h = hi(SWRST);
+ P1.l = lo(SWRST);
R1.l = 0x0007;
W[P1] = R1;
SSYNC;
#if defined(CONFIG_BLKFIN_DCACHE)
ENTRY(_bfin_write_DMEM_CONTROL)
+ P0.l = (DMEM_CONTROL & 0xFFFF);
+ P0.h = (DMEM_CONTROL >> 16);
+
CLI R1;
SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
.align 8;
#endif /* CONFIG_IRQCHIP_DEMUX_GPIO */
-/*
- * This function should be called during kernel startup to initialize
- * the BFin IRQ handling routines.
- */
-int __init init_arch_irq(void)
+void __init init_exception_vectors(void)
{
- int irq;
- unsigned long ilat = 0;
- /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
- bfin_write_SICA_IMASK0(SIC_UNMASK_ALL);
- bfin_write_SICA_IMASK1(SIC_UNMASK_ALL);
SSYNC();
- bfin_write_SICA_IWR0(IWR_ENABLE_ALL);
- bfin_write_SICA_IWR1(IWR_ENABLE_ALL);
-
- local_irq_disable();
-
- init_exception_buff();
-
#ifndef CONFIG_KGDB
bfin_write_EVT0(evt_emulation);
#endif
bfin_write_EVT14(evt14_softirq);
bfin_write_EVT15(evt_system_call);
CSYNC();
+}
+
+/*
+ * This function should be called during kernel startup to initialize
+ * the BFin IRQ handling routines.
+ */
+int __init init_arch_irq(void)
+{
+ int irq;
+ unsigned long ilat = 0;
+ /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
+ bfin_write_SICA_IMASK0(SIC_UNMASK_ALL);
+ bfin_write_SICA_IMASK1(SIC_UNMASK_ALL);
+ SSYNC();
+
+ bfin_write_SICA_IWR0(IWR_ENABLE_ALL);
+ bfin_write_SICA_IWR1(IWR_ENABLE_ALL);
+
+ local_irq_disable();
+
+ init_exception_buff();
for (irq = 0; irq <= SYS_IRQS; irq++) {
if (irq <= IRQ_CORETMR)
u16 gpionr = irq - IRQ_PA0;
u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
- if (pint_val == IRQ_NOT_AVAIL)
+ if (pint_val == IRQ_NOT_AVAIL) {
+ printk(KERN_ERR
+ "GPIO IRQ %d :Not in PINT Assign table "
+ "Reconfigure Interrupt to Port Assignemt\n", irq);
return -ENODEV;
+ }
if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
ret = gpio_request(gpionr, NULL);
}
#endif /* CONFIG_IRQCHIP_DEMUX_GPIO */
+void __init init_exception_vectors(void)
+{
+ SSYNC();
+
+#ifndef CONFIG_KGDB
+ bfin_write_EVT0(evt_emulation);
+#endif
+ bfin_write_EVT2(evt_evt2);
+ bfin_write_EVT3(trap);
+ bfin_write_EVT5(evt_ivhw);
+ bfin_write_EVT6(evt_timer);
+ bfin_write_EVT7(evt_evt7);
+ bfin_write_EVT8(evt_evt8);
+ bfin_write_EVT9(evt_evt9);
+ bfin_write_EVT10(evt_evt10);
+ bfin_write_EVT11(evt_evt11);
+ bfin_write_EVT12(evt_evt12);
+ bfin_write_EVT13(evt_evt13);
+ bfin_write_EVT14(evt14_softirq);
+ bfin_write_EVT15(evt_system_call);
+ CSYNC();
+}
+
/*
* This function should be called during kernel startup to initialize
* the BFin IRQ handling routines.
bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
bfin_write_SIC_IWR(IWR_ENABLE_ALL);
#endif
-
SSYNC();
local_irq_disable();
-#ifndef CONFIG_KGDB
- bfin_write_EVT0(evt_emulation);
-#endif
- bfin_write_EVT2(evt_evt2);
- bfin_write_EVT3(trap);
- bfin_write_EVT5(evt_ivhw);
- bfin_write_EVT6(evt_timer);
- bfin_write_EVT7(evt_evt7);
- bfin_write_EVT8(evt_evt8);
- bfin_write_EVT9(evt_evt9);
- bfin_write_EVT10(evt_evt10);
- bfin_write_EVT11(evt_evt11);
- bfin_write_EVT12(evt_evt12);
- bfin_write_EVT13(evt_evt13);
- bfin_write_EVT14(evt14_softirq);
- bfin_write_EVT15(evt_system_call);
- CSYNC();
-
#if defined(CONFIG_IRQCHIP_DEMUX_GPIO) && defined(CONFIG_BF54x)
#ifdef CONFIG_PINTx_REASSIGN
pint[0]->assign = CONFIG_PINT0_ASSIGN;
config I2C_BLACKFIN_TWI
tristate "Blackfin TWI I2C support"
- depends on BF534 || BF536 || BF537
+ depends on BF534 || BF536 || BF537 || BF54x
help
- This is the TWI I2C device driver for Blackfin 534/536/537.
+ This is the TWI I2C device driver for Blackfin 534/536/537/54x.
This driver can also be built as a module. If so, the module
will be called i2c-bfin-twi.
config SERIO_I8042
tristate "i8042 PC Keyboard controller" if EMBEDDED || !X86
default y
- depends on !PARISC && (!ARM || ARCH_SHARK || FOOTBRIDGE_HOST) && !M68K
+ depends on !PARISC && (!ARM || ARCH_SHARK || FOOTBRIDGE_HOST) && !M68K && !BFIN
---help---
i8042 is the chip over which the standard AT keyboard and PS/2
mouse are connected to the computer. If you use these devices,
*/
static int bf537mac_open(struct net_device *dev)
{
+ int retval;
pr_debug("%s: %s\n", dev->name, __FUNCTION__);
/*
}
/* initial rx and tx list */
- desc_list_init();
+ retval = desc_list_init();
+
+ if (retval)
+ return retval;
bf537mac_setphy(dev);
setup_system_regs(dev);
/*
* Blackfin On-Chip Real Time Clock Driver
- * Supports BF531/BF532/BF533/BF534/BF536/BF537
+ * Supports BF53[123]/BF53[467]/BF54[2489]
*
* Copyright 2004-2007 Analog Devices Inc.
*
extern int read_iloc(void);
extern int bfin_console_init(void);
extern asmlinkage void lower_to_irq14(void);
+extern void init_exception_vectors(void);
extern void init_dma(void);
extern void program_IAR(void);
extern void evt14_softirq(void);
#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
+#define bfin_read_TWI_CLKDIV() bfin_read16(TWI0_CLKDIV)
+#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val)
+#define bfin_read_TWI_CONTROL() bfin_read16(TWI0_CONTROL)
+#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI0_CONTROL, val)
+#define bfin_read_TWI_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL)
+#define bfin_write_TWI_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val)
+#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT)
+#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
+#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
+#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
+#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI0_MASTER_CTRL)
+#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTRL, val)
+#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT)
+#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
+#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
+#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
+#define bfin_read_TWI_INT_STAT() bfin_read16(TWI0_INT_STAT)
+#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val)
+#define bfin_read_TWI_INT_MASK() bfin_read16(TWI0_INT_MASK)
+#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val)
+#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI0_FIFO_CTRL)
+#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTRL, val)
+#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT)
+#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
+#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8)
+#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
+#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16)
+#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
+#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8)
+#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
+#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
+#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
+
/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
/* SPORT1 Registers */
#define IRQ_ATAPI_TX BFIN_IRQ(44) /* ATAPI TX (DMA11) Interrupt */
#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 Interrupt */
#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 Interrupt */
+#define IRQ_TWI IRQ_TWI0 /* TWI Interrupt */
#define IRQ_CAN0_RX BFIN_IRQ(47) /* CAN0 Receive Interrupt */
#define IRQ_CAN0_TX BFIN_IRQ(48) /* CAN0 Transmit Interrupt */
#define IRQ_MDMAS2 BFIN_IRQ(49) /* MDMA Stream 2 Interrupt */
#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
#define bfin_read_CHIPID() bfin_read32(CHIPID)
+/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
+#define bfin_read_SWRST() bfin_read_SICA_SWRST()
+#define bfin_write_SWRST() bfin_write_SICA_SWRST()
+#define bfin_read_SYSCR() bfin_read_SICA_SYSCR()
+#define bfin_write_SYSCR() bfin_write_SICA_SYSCR()
+
/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST)
#define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST,val)
#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
#define CHIPID 0xFFC00014 /* Chip ID Register */
+/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
+#define SWRST SICA_SWRST
+#define SYSCR SICA_SYSCR
+
/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
#define SICA_SWRST 0xFFC00100 /* Software Reset register */
#define SICA_SYSCR 0xFFC00104 /* System Reset Configuration register */
*/
#define ALIGN_PAGE_MASK 0xffffe000
+/*
+ * Size of kernel stack for each process. This must be a power of 2...
+ */
+#define THREAD_SIZE 8192 /* 2 pages */
+
#ifndef __ASSEMBLY__
typedef unsigned long mm_segment_t;
#define init_thread_info (init_thread_union.thread_info)
#define init_stack (init_thread_union.stack)
-/*
- * Size of kernel stack for each process. This must be a power of 2...
- */
-#define THREAD_SIZE 8192 /* 2 pages */
-
/* How to get the thread information struct from C */
static inline struct thread_info *current_thread_info(void)
struct thread_info *ti;
__asm__("%0 = sp;": "=&d"(ti):
);
- return (struct thread_info *)((long)ti & ~8191UL);
+ return (struct thread_info *)((long)ti & ~((long)THREAD_SIZE-1));
}
/* thread information allocation */
git.openpandora.org / pandora-kernel.git / commitdiff