ARM: OMAP: Add DMTIMER definitions for posted mode

For OMAP2+ devices, when using DMTIMERs for system timers (clock-events and
clock-source) the posted mode configuration of the timers is used. To allow
the compiler to optimise the functions for configuring and reading the system
timers, the posted flag variable is hard-coded with the value 1. To make it
clear that posted mode is being used add some definitions so that it is more
readable.

Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Conflicts:

	arch/arm/plat-omap/include/plat/dmtimer.h

diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 3f7aa62..56b8e11 100644 (file)
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -99,7 +99,7 @@ static int omap2_gp_timer_set_next_event(unsigned long cycles,
                                         struct clock_event_device *evt)
 {
        __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
-                                               0xffffffff - cycles, 1);
+                                  0xffffffff - cycles, OMAP_TIMER_POSTED);
 
        return 0;
 }
@@ -109,7 +109,7 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
 {
        u32 period;
 
-       __omap_dm_timer_stop(&clkev, 1, clkev.rate);
+       __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
 
        switch (mode) {
        case CLOCK_EVT_MODE_PERIODIC:
@@ -117,10 +117,10 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
                period -= 1;
                /* Looks like we need to first set the load value separately */
                __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
-                                       0xffffffff - period, 1);
+                                     0xffffffff - period, OMAP_TIMER_POSTED);
                __omap_dm_timer_load_start(&clkev,
                                        OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
-                                               0xffffffff - period, 1);
+                                       0xffffffff - period, OMAP_TIMER_POSTED);
                break;
        case CLOCK_EVT_MODE_ONESHOT:
                break;
@@ -249,7 +249,8 @@ static struct omap_dm_timer clksrc;
  */
 static cycle_t clocksource_read_cycles(struct clocksource *cs)
 {
-       return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1);
+       return (cycle_t)__omap_dm_timer_read_counter(&clksrc,
+                                                    OMAP_TIMER_POSTED);
 }
 
 static struct clocksource clocksource_gpt = {
@@ -263,7 +264,8 @@ static struct clocksource clocksource_gpt = {
 static u32 notrace dmtimer_read_sched_clock(void)
 {
        if (clksrc.reserved)
-               return __omap_dm_timer_read_counter(&clksrc, 1);
+               return __omap_dm_timer_read_counter(&clksrc,
+                                                   OMAP_TIMER_POSTED);
 
        return 0;
 }
@@ -281,7 +283,8 @@ static void __init omap2_gp_clocksource_init(int gptimer_id,
                gptimer_id, clksrc.rate);
 
        __omap_dm_timer_load_start(&clksrc,
-                       OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
+                                  OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
+                                  OMAP_TIMER_POSTED);
        setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
 
        if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))

diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index ffa6ccf..b27d92a 100644 (file)
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -61,6 +61,10 @@
  */
 #define OMAP_TIMER_IP_VERSION_1                        0x1
 
+/* posted mode types */
+#define OMAP_TIMER_NONPOSTED                   0x00
+#define OMAP_TIMER_POSTED                      0x01
+
 /* timer capabilities used in hwmod database */
 #define OMAP_TIMER_SECURE                              0x80000000
 #define OMAP_TIMER_ALWON                               0x40000000