[ARM] S3C64XX: fix HCLK gate defines

A few typos seems to have sneaked into the HCLK gate defines, causing the
usb host clock to not get enabled. Fix them according to the reference
manual and throw in the 3d accel bit for good measure.

Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>

diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
index 52836d4..a8777a7 100644 (file)
--- a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
@@ -88,11 +88,11 @@
 #define S3C6400_CLKDIV2_SPI0_SHIFT     (0)
 
 /* HCLK GATE Registers */
-#define S3C_CLKCON_HCLK_BUS    (1<<30)
-#define S3C_CLKCON_HCLK_SECUR  (1<<29)
-#define S3C_CLKCON_HCLK_SDMA1  (1<<28)
-#define S3C_CLKCON_HCLK_SDMA2  (1<<27)
-#define S3C_CLKCON_HCLK_UHOST  (1<<26)
+#define S3C_CLKCON_HCLK_3DSE   (1<<31)
+#define S3C_CLKCON_HCLK_UHOST  (1<<29)
+#define S3C_CLKCON_HCLK_SECUR  (1<<28)
+#define S3C_CLKCON_HCLK_SDMA1  (1<<27)
+#define S3C_CLKCON_HCLK_SDMA0  (1<<26)
 #define S3C_CLKCON_HCLK_IROM   (1<<25)
 #define S3C_CLKCON_HCLK_DDR1   (1<<24)
 #define S3C_CLKCON_HCLK_DDR0   (1<<23)