Merge branch 'drm-patches' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied...

* 'drm-patches' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6:
  drm: remove drm_{alloc,free}_pages
  drm: sis fix compile warning
  drm: add new radeon PCI ids..
  drm: read breadcrumb in IRQ handler
  drm: fixup i915 breadcrumb read/write
  drm:  remove pointless checks in radeon_state
  drm: fixup improper cast.
  drm: rationalise some pci ids
  drm: Add general-purpose packet for manipulating scratch registers (r300)
  drm: rework radeon memory map (radeon 1.23)
  drm: update r300 register names
  drm: fixup PCI DMA support

diff --git a/drivers/char/drm/drmP.h b/drivers/char/drm/drmP.h
index 107df9f..edc72a6 100644 (file)
--- a/drivers/char/drm/drmP.h
+++ b/drivers/char/drm/drmP.h
@@ -357,6 +357,12 @@ typedef struct drm_freelist {
        spinlock_t lock;
 } drm_freelist_t;
 
+typedef struct drm_dma_handle {
+       dma_addr_t busaddr;
+       void *vaddr;
+       size_t size;
+} drm_dma_handle_t;
+
 /**
  * Buffer entry.  There is one of this for each buffer size order.
  */
@@ -366,7 +372,7 @@ typedef struct drm_buf_entry {
        drm_buf_t *buflist;             /**< buffer list */
        int seg_count;
        int page_order;
-       unsigned long *seglist;
+       drm_dma_handle_t **seglist;
 
        drm_freelist_t freelist;
 } drm_buf_entry_t;
@@ -483,12 +489,6 @@ typedef struct drm_sigdata {
        drm_hw_lock_t *lock;
 } drm_sigdata_t;
 
-typedef struct drm_dma_handle {
-       dma_addr_t busaddr;
-       void *vaddr;
-       size_t size;
-} drm_dma_handle_t;
-
 /**
  * Mappings list
  */
@@ -813,8 +813,6 @@ extern void drm_mem_init(void);
 extern int drm_mem_info(char *buf, char **start, off_t offset,
                        int request, int *eof, void *data);
 extern void *drm_realloc(void *oldpt, size_t oldsize, size_t size, int area);
-extern unsigned long drm_alloc_pages(int order, int area);
-extern void drm_free_pages(unsigned long address, int order, int area);
 extern void *drm_ioremap(unsigned long offset, unsigned long size,
                         drm_device_t * dev);
 extern void *drm_ioremap_nocache(unsigned long offset, unsigned long size,

diff --git a/drivers/char/drm/drm_bufs.c b/drivers/char/drm/drm_bufs.c
index e2637b4..8a9cf12 100644 (file)
--- a/drivers/char/drm/drm_bufs.c
+++ b/drivers/char/drm/drm_bufs.c
@@ -474,8 +474,7 @@ static void drm_cleanup_buf_error(drm_device_t * dev, drm_buf_entry_t * entry)
        if (entry->seg_count) {
                for (i = 0; i < entry->seg_count; i++) {
                        if (entry->seglist[i]) {
-                               drm_free_pages(entry->seglist[i],
-                                              entry->page_order, DRM_MEM_DMA);
+                               drm_pci_free(dev, entry->seglist[i]);
                        }
                }
                drm_free(entry->seglist,
@@ -678,7 +677,7 @@ int drm_addbufs_pci(drm_device_t * dev, drm_buf_desc_t * request)
        int total;
        int page_order;
        drm_buf_entry_t *entry;
-       unsigned long page;
+       drm_dma_handle_t *dmah;
        drm_buf_t *buf;
        int alignment;
        unsigned long offset;
@@ -781,8 +780,10 @@ int drm_addbufs_pci(drm_device_t * dev, drm_buf_desc_t * request)
        page_count = 0;
 
        while (entry->buf_count < count) {
-               page = drm_alloc_pages(page_order, DRM_MEM_DMA);
-               if (!page) {
+               
+               dmah = drm_pci_alloc(dev, PAGE_SIZE << page_order, 0x1000, 0xfffffffful);
+               
+               if (!dmah) {
                        /* Set count correctly so we free the proper amount. */
                        entry->buf_count = count;
                        entry->seg_count = count;
@@ -794,13 +795,13 @@ int drm_addbufs_pci(drm_device_t * dev, drm_buf_desc_t * request)
                        atomic_dec(&dev->buf_alloc);
                        return -ENOMEM;
                }
-               entry->seglist[entry->seg_count++] = page;
+               entry->seglist[entry->seg_count++] = dmah;
                for (i = 0; i < (1 << page_order); i++) {
                        DRM_DEBUG("page %d @ 0x%08lx\n",
                                  dma->page_count + page_count,
-                                 page + PAGE_SIZE * i);
+                                 (unsigned long)dmah->vaddr + PAGE_SIZE * i);
                        temp_pagelist[dma->page_count + page_count++]
-                           = page + PAGE_SIZE * i;
+                               = (unsigned long)dmah->vaddr + PAGE_SIZE * i;
                }
                for (offset = 0;
                     offset + size <= total && entry->buf_count < count;
@@ -811,7 +812,8 @@ int drm_addbufs_pci(drm_device_t * dev, drm_buf_desc_t * request)
                        buf->order = order;
                        buf->used = 0;
                        buf->offset = (dma->byte_count + byte_count + offset);
-                       buf->address = (void *)(page + offset);
+                       buf->address = (void *)(dmah->vaddr + offset);
+                       buf->bus_address = dmah->busaddr + offset;
                        buf->next = NULL;
                        buf->waiting = 0;
                        buf->pending = 0;

diff --git a/drivers/char/drm/drm_dma.c b/drivers/char/drm/drm_dma.c
index 2afab95..892db70 100644 (file)
--- a/drivers/char/drm/drm_dma.c
+++ b/drivers/char/drm/drm_dma.c
@@ -85,9 +85,7 @@ void drm_dma_takedown(drm_device_t * dev)
                                  dma->bufs[i].seg_count);
                        for (j = 0; j < dma->bufs[i].seg_count; j++) {
                                if (dma->bufs[i].seglist[j]) {
-                                       drm_free_pages(dma->bufs[i].seglist[j],
-                                                      dma->bufs[i].page_order,
-                                                      DRM_MEM_DMA);
+                                       drm_pci_free(dev, dma->bufs[i].seglist[j]);
                                }
                        }
                        drm_free(dma->bufs[i].seglist,

diff --git a/drivers/char/drm/drm_memory.c b/drivers/char/drm/drm_memory.c
index 8074771..dddf8de 100644 (file)
--- a/drivers/char/drm/drm_memory.c
+++ b/drivers/char/drm/drm_memory.c
@@ -79,65 +79,6 @@ void *drm_realloc(void *oldpt, size_t oldsize, size_t size, int area)
        return pt;
 }
 
-/**
- * Allocate pages.
- *
- * \param order size order.
- * \param area memory area. (Not used.)
- * \return page address on success, or zero on failure.
- *
- * Allocate and reserve free pages.
- */
-unsigned long drm_alloc_pages(int order, int area)
-{
-       unsigned long address;
-       unsigned long bytes = PAGE_SIZE << order;
-       unsigned long addr;
-       unsigned int sz;
-
-       address = __get_free_pages(GFP_KERNEL|__GFP_COMP, order);
-       if (!address)
-               return 0;
-
-       /* Zero */
-       memset((void *)address, 0, bytes);
-
-       /* Reserve */
-       for (addr = address, sz = bytes;
-            sz > 0; addr += PAGE_SIZE, sz -= PAGE_SIZE) {
-               SetPageReserved(virt_to_page(addr));
-       }
-
-       return address;
-}
-
-/**
- * Free pages.
- *
- * \param address address of the pages to free.
- * \param order size order.
- * \param area memory area. (Not used.)
- *
- * Unreserve and free pages allocated by alloc_pages().
- */
-void drm_free_pages(unsigned long address, int order, int area)
-{
-       unsigned long bytes = PAGE_SIZE << order;
-       unsigned long addr;
-       unsigned int sz;
-
-       if (!address)
-               return;
-
-       /* Unreserve */
-       for (addr = address, sz = bytes;
-            sz > 0; addr += PAGE_SIZE, sz -= PAGE_SIZE) {
-               ClearPageReserved(virt_to_page(addr));
-       }
-
-       free_pages(address, order);
-}
-
 #if __OS_HAS_AGP
 /** Wrapper around agp_allocate_memory() */
 DRM_AGP_MEM *drm_alloc_agp(drm_device_t * dev, int pages, u32 type)

diff --git a/drivers/char/drm/drm_memory_debug.h b/drivers/char/drm/drm_memory_debug.h
index e84605f..7868341 100644 (file)
--- a/drivers/char/drm/drm_memory_debug.h
+++ b/drivers/char/drm/drm_memory_debug.h
@@ -206,76 +206,6 @@ void drm_free (void *pt, size_t size, int area) {
        }
 }
 
-unsigned long drm_alloc_pages (int order, int area) {
-       unsigned long address;
-       unsigned long bytes = PAGE_SIZE << order;
-       unsigned long addr;
-       unsigned int sz;
-
-       spin_lock(&drm_mem_lock);
-       if ((drm_ram_used >> PAGE_SHIFT)
-           > (DRM_RAM_PERCENT * drm_ram_available) / 100) {
-               spin_unlock(&drm_mem_lock);
-               return 0;
-       }
-       spin_unlock(&drm_mem_lock);
-
-       address = __get_free_pages(GFP_KERNEL|__GFP_COMP, order);
-       if (!address) {
-               spin_lock(&drm_mem_lock);
-               ++drm_mem_stats[area].fail_count;
-               spin_unlock(&drm_mem_lock);
-               return 0;
-       }
-       spin_lock(&drm_mem_lock);
-       ++drm_mem_stats[area].succeed_count;
-       drm_mem_stats[area].bytes_allocated += bytes;
-       drm_ram_used += bytes;
-       spin_unlock(&drm_mem_lock);
-
-       /* Zero outside the lock */
-       memset((void *)address, 0, bytes);
-
-       /* Reserve */
-       for (addr = address, sz = bytes;
-            sz > 0; addr += PAGE_SIZE, sz -= PAGE_SIZE) {
-               SetPageReserved(virt_to_page(addr));
-       }
-
-       return address;
-}
-
-void drm_free_pages (unsigned long address, int order, int area) {
-       unsigned long bytes = PAGE_SIZE << order;
-       int alloc_count;
-       int free_count;
-       unsigned long addr;
-       unsigned int sz;
-
-       if (!address) {
-               DRM_MEM_ERROR(area, "Attempt to free address 0\n");
-       } else {
-               /* Unreserve */
-               for (addr = address, sz = bytes;
-                    sz > 0; addr += PAGE_SIZE, sz -= PAGE_SIZE) {
-                       ClearPageReserved(virt_to_page(addr));
-               }
-               free_pages(address, order);
-       }
-
-       spin_lock(&drm_mem_lock);
-       free_count = ++drm_mem_stats[area].free_count;
-       alloc_count = drm_mem_stats[area].succeed_count;
-       drm_mem_stats[area].bytes_freed += bytes;
-       drm_ram_used -= bytes;
-       spin_unlock(&drm_mem_lock);
-       if (free_count > alloc_count) {
-               DRM_MEM_ERROR(area,
-                             "Excess frees: %d frees, %d allocs\n",
-                             free_count, alloc_count);
-       }
-}
-
 void *drm_ioremap (unsigned long offset, unsigned long size,
                    drm_device_t * dev) {
        void *pt;

diff --git a/drivers/char/drm/drm_pci.c b/drivers/char/drm/drm_pci.c
index 1fd7ff1..b28ca9c 100644 (file)
--- a/drivers/char/drm/drm_pci.c
+++ b/drivers/char/drm/drm_pci.c
@@ -50,6 +50,10 @@ drm_dma_handle_t *drm_pci_alloc(drm_device_t * dev, size_t size, size_t align,
                                dma_addr_t maxaddr)
 {
        drm_dma_handle_t *dmah;
+#if 1
+       unsigned long addr;
+       size_t sz;
+#endif
 #ifdef DRM_DEBUG_MEMORY
        int area = DRM_MEM_DMA;
 
@@ -79,7 +83,7 @@ drm_dma_handle_t *drm_pci_alloc(drm_device_t * dev, size_t size, size_t align,
                return NULL;
 
        dmah->size = size;
-       dmah->vaddr = pci_alloc_consistent(dev->pdev, size, &dmah->busaddr);
+       dmah->vaddr = dma_alloc_coherent(&dev->pdev->dev, size, &dmah->busaddr, GFP_KERNEL | __GFP_COMP);
 
 #ifdef DRM_DEBUG_MEMORY
        if (dmah->vaddr == NULL) {
@@ -104,18 +108,29 @@ drm_dma_handle_t *drm_pci_alloc(drm_device_t * dev, size_t size, size_t align,
 
        memset(dmah->vaddr, 0, size);
 
+       /* XXX - Is virt_to_page() legal for consistent mem? */
+       /* Reserve */
+       for (addr = (unsigned long)dmah->vaddr, sz = size;
+            sz > 0; addr += PAGE_SIZE, sz -= PAGE_SIZE) {
+               SetPageReserved(virt_to_page(addr));
+       }
+
        return dmah;
 }
 
 EXPORT_SYMBOL(drm_pci_alloc);
 
 /**
- * \brief Free a PCI consistent memory block with freeing its descriptor.
+ * \brief Free a PCI consistent memory block without freeing its descriptor.
  *
  * This function is for internal use in the Linux-specific DRM core code.
  */
 void __drm_pci_free(drm_device_t * dev, drm_dma_handle_t * dmah)
 {
+#if 1
+       unsigned long addr;
+       size_t sz;
+#endif
 #ifdef DRM_DEBUG_MEMORY
        int area = DRM_MEM_DMA;
        int alloc_count;
@@ -127,8 +142,14 @@ void __drm_pci_free(drm_device_t * dev, drm_dma_handle_t * dmah)
                DRM_MEM_ERROR(area, "Attempt to free address 0\n");
 #endif
        } else {
-               pci_free_consistent(dev->pdev, dmah->size, dmah->vaddr,
-                                   dmah->busaddr);
+               /* XXX - Is virt_to_page() legal for consistent mem? */
+               /* Unreserve */
+               for (addr = (unsigned long)dmah->vaddr, sz = dmah->size;
+                    sz > 0; addr += PAGE_SIZE, sz -= PAGE_SIZE) {
+                       ClearPageReserved(virt_to_page(addr));
+               }
+               dma_free_coherent(&dev->pdev->dev, dmah->size, dmah->vaddr,
+                                 dmah->busaddr);
        }
 
 #ifdef DRM_DEBUG_MEMORY

diff --git a/drivers/char/drm/drm_pciids.h b/drivers/char/drm/drm_pciids.h
index 2c17e88..b1bb3c7 100644 (file)
--- a/drivers/char/drm/drm_pciids.h
+++ b/drivers/char/drm/drm_pciids.h
@@ -3,49 +3,69 @@
    Please contact dri-devel@lists.sf.net to add new cards to this list
 */
 #define radeon_PCI_IDS \
-       {0x1002, 0x3150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350},\
+       {0x1002, 0x3150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|CHIP_IS_MOBILITY}, \
+       {0x1002, 0x3152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|CHIP_IS_MOBILITY|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x3154, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|CHIP_IS_MOBILITY|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x3E50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x3E54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|CHIP_NEW_MEMMAP}, \
        {0x1002, 0x4136, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS100|CHIP_IS_IGP}, \
        {0x1002, 0x4137, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|CHIP_IS_IGP}, \
        {0x1002, 0x4144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
        {0x1002, 0x4145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
        {0x1002, 0x4146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
        {0x1002, 0x4147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
+       {0x1002, 0x4148, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
+       {0x1002, 0x4149, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
+       {0x1002, 0x414A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
+       {0x1002, 0x414B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
        {0x1002, 0x4150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
        {0x1002, 0x4151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
        {0x1002, 0x4152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
        {0x1002, 0x4153, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
        {0x1002, 0x4154, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
+       {0x1002, 0x4155, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
        {0x1002, 0x4156, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
-       {0x1002, 0x4237, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS250|CHIP_IS_IGP}, \
+       {0x1002, 0x4237, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|CHIP_IS_IGP}, \
        {0x1002, 0x4242, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
        {0x1002, 0x4243, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
        {0x1002, 0x4336, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS100|CHIP_IS_IGP|CHIP_IS_MOBILITY}, \
        {0x1002, 0x4337, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|CHIP_IS_IGP|CHIP_IS_MOBILITY}, \
-       {0x1002, 0x4437, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS250|CHIP_IS_IGP|CHIP_IS_MOBILITY}, \
-       {0x1002, 0x4964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R250}, \
-       {0x1002, 0x4965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R250}, \
-       {0x1002, 0x4966, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R250}, \
-       {0x1002, 0x4967, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R250}, \
-       {0x1002, 0x4A49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420}, \
-       {0x1002, 0x4A4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420}, \
+       {0x1002, 0x4437, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|CHIP_IS_IGP|CHIP_IS_MOBILITY}, \
+       {0x1002, 0x4966, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250}, \
+       {0x1002, 0x4967, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250}, \
+       {0x1002, 0x4A48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x4A49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x4A4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x4A4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x4A4C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x4A4D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x4A4E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_IS_MOBILITY|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x4A4F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x4A50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x4A54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x4B49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x4B4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x4B4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x4B4C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
        {0x1002, 0x4C57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200|CHIP_IS_MOBILITY}, \
        {0x1002, 0x4C58, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200|CHIP_IS_MOBILITY}, \
        {0x1002, 0x4C59, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100|CHIP_IS_MOBILITY}, \
        {0x1002, 0x4C5A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100|CHIP_IS_MOBILITY}, \
-       {0x1002, 0x4C64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R250|CHIP_IS_MOBILITY}, \
-       {0x1002, 0x4C65, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R250|CHIP_IS_MOBILITY}, \
-       {0x1002, 0x4C66, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R250|CHIP_IS_MOBILITY}, \
-       {0x1002, 0x4C67, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R250|CHIP_IS_MOBILITY}, \
+       {0x1002, 0x4C64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|CHIP_IS_MOBILITY}, \
+       {0x1002, 0x4C66, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|CHIP_IS_MOBILITY}, \
+       {0x1002, 0x4C67, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|CHIP_IS_MOBILITY}, \
        {0x1002, 0x4E44, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
        {0x1002, 0x4E45, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
-       {0x1002, 0x4E46, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
+       {0x1002, 0x4E46, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
        {0x1002, 0x4E47, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
        {0x1002, 0x4E48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
        {0x1002, 0x4E49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
-       {0x1002, 0x4E4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
+       {0x1002, 0x4E4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
        {0x1002, 0x4E4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
        {0x1002, 0x4E50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|CHIP_IS_MOBILITY}, \
        {0x1002, 0x4E51, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|CHIP_IS_MOBILITY}, \
+       {0x1002, 0x4E52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|CHIP_IS_MOBILITY}, \
+       {0x1002, 0x4E53, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|CHIP_IS_MOBILITY}, \
        {0x1002, 0x4E54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|CHIP_IS_MOBILITY}, \
        {0x1002, 0x4E56, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|CHIP_IS_MOBILITY}, \
        {0x1002, 0x5144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|CHIP_SINGLE_CRTC}, \
@@ -53,44 +73,66 @@
        {0x1002, 0x5146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|CHIP_SINGLE_CRTC}, \
        {0x1002, 0x5147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|CHIP_SINGLE_CRTC}, \
        {0x1002, 0x5148, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
-       {0x1002, 0x5149, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
-       {0x1002, 0x514A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
-       {0x1002, 0x514B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
        {0x1002, 0x514C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
        {0x1002, 0x514D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
-       {0x1002, 0x514E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
-       {0x1002, 0x514F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
        {0x1002, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200}, \
        {0x1002, 0x5158, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200}, \
        {0x1002, 0x5159, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
        {0x1002, 0x515A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
        {0x1002, 0x515E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
-       {0x1002, 0x5168, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
-       {0x1002, 0x5169, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
-       {0x1002, 0x516A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
-       {0x1002, 0x516B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
-       {0x1002, 0x516C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
-       {0x1002, 0x5460, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
-       {0x1002, 0x554F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
+       {0x1002, 0x5460, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|CHIP_IS_MOBILITY}, \
+       {0x1002, 0x5462, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|CHIP_IS_MOBILITY}, \
+       {0x1002, 0x5464, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|CHIP_IS_MOBILITY}, \
+       {0x1002, 0x5548, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x5549, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x554A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x554B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x554C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x554D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x554E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x554F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x5550, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x5551, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x5552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x5554, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x564A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|CHIP_IS_MOBILITY|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x564B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|CHIP_IS_MOBILITY|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x564F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|CHIP_IS_MOBILITY|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x5652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|CHIP_IS_MOBILITY|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x5653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|CHIP_IS_MOBILITY|CHIP_NEW_MEMMAP}, \
        {0x1002, 0x5834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|CHIP_IS_IGP}, \
        {0x1002, 0x5835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|CHIP_IS_IGP|CHIP_IS_MOBILITY}, \
-       {0x1002, 0x5836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|CHIP_IS_IGP}, \
-       {0x1002, 0x5837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|CHIP_IS_IGP}, \
        {0x1002, 0x5960, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
        {0x1002, 0x5961, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
        {0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
-       {0x1002, 0x5963, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
        {0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
-       {0x1002, 0x5968, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
+       {0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
        {0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
-       {0x1002, 0x596A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
-       {0x1002, 0x596B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
+       {0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x5b64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x5b65, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|CHIP_NEW_MEMMAP}, \
        {0x1002, 0x5c61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|CHIP_IS_MOBILITY}, \
-       {0x1002, 0x5c62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
        {0x1002, 0x5c63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|CHIP_IS_MOBILITY}, \
-       {0x1002, 0x5c64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
-       {0x1002, 0x5d4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
-       {0x1002, 0x5e4b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420}, \
+       {0x1002, 0x5d48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_IS_MOBILITY|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x5d49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_IS_MOBILITY|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x5d4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_IS_MOBILITY|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x5d4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x5d4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x5d4e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x5d4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x5d50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x5d52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x5d57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x5e48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x5e4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x5e4b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x5e4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x5e4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x5e4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x7834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|CHIP_IS_IGP|CHIP_NEW_MEMMAP}, \
+       {0x1002, 0x7835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|CHIP_IS_IGP|CHIP_IS_MOBILITY|CHIP_NEW_MEMMAP}, \
        {0, 0, 0}
 
 #define r128_PCI_IDS \

diff --git a/drivers/char/drm/i915_dma.c b/drivers/char/drm/i915_dma.c
index 1ff4c7c..9f4b8ce 100644 (file)
--- a/drivers/char/drm/i915_dma.c
+++ b/drivers/char/drm/i915_dma.c
@@ -495,8 +495,6 @@ static int i915_dispatch_batchbuffer(drm_device_t * dev,
                }
        }
 
-       dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
-
        i915_emit_breadcrumb(dev);
 
        return 0;

diff --git a/drivers/char/drm/i915_irq.c b/drivers/char/drm/i915_irq.c
index d3879ac..a752afd 100644 (file)
--- a/drivers/char/drm/i915_irq.c
+++ b/drivers/char/drm/i915_irq.c
@@ -53,6 +53,8 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 
        I915_WRITE16(I915REG_INT_IDENTITY_R, temp);
 
+       dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
+
        if (temp & USER_INT_FLAG)
                DRM_WAKEUP(&dev_priv->irq_queue);
 

diff --git a/drivers/char/drm/r300_cmdbuf.c b/drivers/char/drm/r300_cmdbuf.c
index c08fa50..b108c7f 100644 (file)
--- a/drivers/char/drm/r300_cmdbuf.c
+++ b/drivers/char/drm/r300_cmdbuf.c
@@ -214,13 +214,13 @@ void r300_init_reg_flags(void)
        ADD_RANGE(0x4F54, 1);
 
        ADD_RANGE(R300_TX_FILTER_0, 16);
-       ADD_RANGE(R300_TX_UNK1_0, 16);
+       ADD_RANGE(R300_TX_FILTER1_0, 16);
        ADD_RANGE(R300_TX_SIZE_0, 16);
        ADD_RANGE(R300_TX_FORMAT_0, 16);
        ADD_RANGE(R300_TX_PITCH_0, 16);
        /* Texture offset is dangerous and needs more checking */
        ADD_RANGE_MARK(R300_TX_OFFSET_0, 16, MARK_CHECK_OFFSET);
-       ADD_RANGE(R300_TX_UNK4_0, 16);
+       ADD_RANGE(R300_TX_CHROMA_KEY_0, 16);
        ADD_RANGE(R300_TX_BORDER_COLOR_0, 16);
 
        /* Sporadic registers used as primitives are emitted */
@@ -242,8 +242,10 @@ static __inline__ int r300_check_range(unsigned reg, int count)
        return 0;
 }
 
-  /* we expect offsets passed to the framebuffer to be either within video memory or
-     within AGP space */
+/*
+ * we expect offsets passed to the framebuffer to be either within video 
+ * memory or within AGP space 
+ */
 static __inline__ int r300_check_offset(drm_radeon_private_t *dev_priv,
                                        u32 offset)
 {
@@ -251,11 +253,11 @@ static __inline__ int r300_check_offset(drm_radeon_private_t *dev_priv,
           but this value is not being kept.
           This code is correct for now (does the same thing as the
           code that sets MC_FB_LOCATION) in radeon_cp.c */
-       if ((offset >= dev_priv->fb_location) &&
-           (offset < dev_priv->gart_vm_start))
+       if (offset >= dev_priv->fb_location &&
+           offset < (dev_priv->fb_location + dev_priv->fb_size))
                return 0;
-       if ((offset >= dev_priv->gart_vm_start) &&
-           (offset < dev_priv->gart_vm_start + dev_priv->gart_size))
+       if (offset >= dev_priv->gart_vm_start &&
+           offset < (dev_priv->gart_vm_start + dev_priv->gart_size))
                return 0;
        return 1;
 }
@@ -490,6 +492,7 @@ static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t *dev_priv,
 
        return 0;
 }
+
 static __inline__ int r300_emit_bitblt_multi(drm_radeon_private_t *dev_priv,
                                             drm_radeon_kcmd_buffer_t *cmdbuf)
 {
@@ -701,6 +704,64 @@ static void r300_discard_buffer(drm_device_t * dev, drm_buf_t * buf)
        buf->used = 0;
 }
 
+static int r300_scratch(drm_radeon_private_t *dev_priv,
+                       drm_radeon_kcmd_buffer_t *cmdbuf,
+                       drm_r300_cmd_header_t header)
+{
+       u32 *ref_age_base;
+       u32 i, buf_idx, h_pending;
+       RING_LOCALS;
+       
+       if (cmdbuf->bufsz < 
+           (sizeof(u64) + header.scratch.n_bufs * sizeof(buf_idx))) {
+               return DRM_ERR(EINVAL);
+       }
+       
+       if (header.scratch.reg >= 5) {
+               return DRM_ERR(EINVAL);
+       }
+       
+       dev_priv->scratch_ages[header.scratch.reg]++;
+       
+       ref_age_base = *(u32 **)cmdbuf->buf;
+       
+       cmdbuf->buf += sizeof(u64);
+       cmdbuf->bufsz -= sizeof(u64);
+       
+       for (i=0; i < header.scratch.n_bufs; i++) {
+               buf_idx = *(u32 *)cmdbuf->buf;
+               buf_idx *= 2; /* 8 bytes per buf */
+               
+               if (DRM_COPY_TO_USER(ref_age_base + buf_idx, &dev_priv->scratch_ages[header.scratch.reg], sizeof(u32))) {
+                       return DRM_ERR(EINVAL);
+               }
+                                       
+               if (DRM_COPY_FROM_USER(&h_pending, ref_age_base + buf_idx + 1, sizeof(u32))) {
+                       return DRM_ERR(EINVAL);
+               }
+                                       
+               if (h_pending == 0) {
+                       return DRM_ERR(EINVAL);
+               }
+                                       
+               h_pending--;
+                                               
+               if (DRM_COPY_TO_USER(ref_age_base + buf_idx + 1, &h_pending, sizeof(u32))) {
+                       return DRM_ERR(EINVAL);
+               }
+                                       
+               cmdbuf->buf += sizeof(buf_idx);
+               cmdbuf->bufsz -= sizeof(buf_idx);
+       }
+       
+       BEGIN_RING(2);
+       OUT_RING(CP_PACKET0(RADEON_SCRATCH_REG0 + header.scratch.reg * 4, 0));
+       OUT_RING(dev_priv->scratch_ages[header.scratch.reg]);
+       ADVANCE_RING();
+       
+       return 0;
+}
+
 /**
  * Parses and validates a user-supplied command buffer and emits appropriate
  * commands on the DMA ring buffer.
@@ -838,6 +899,15 @@ int r300_do_cp_cmdbuf(drm_device_t *dev,
                        }
                        break;
 
+               case R300_CMD_SCRATCH:
+                       DRM_DEBUG("R300_CMD_SCRATCH\n");
+                       ret = r300_scratch(dev_priv, cmdbuf, header);
+                       if (ret) {
+                               DRM_ERROR("r300_scratch failed\n");
+                               goto cleanup;
+                       }
+                       break;
+                       
                default:
                        DRM_ERROR("bad cmd_type %i at %p\n",
                                  header.header.cmd_type,

diff --git a/drivers/char/drm/r300_reg.h b/drivers/char/drm/r300_reg.h
index d1e1995..a881f96 100644 (file)
--- a/drivers/char/drm/r300_reg.h
+++ b/drivers/char/drm/r300_reg.h
@@ -711,8 +711,22 @@ I am fairly certain that they are correct unless stated otherwise in comments.
 #      define R300_TX_MAX_ANISO_16_TO_1 (8 << 21)
 #      define R300_TX_MAX_ANISO_MASK    (14 << 21)
 
-#define R300_TX_UNK1_0                      0x4440
+#define R300_TX_FILTER1_0                      0x4440
+#      define R300_CHROMA_KEY_MODE_DISABLE    0
+#      define R300_CHROMA_KEY_FORCE           1
+#      define R300_CHROMA_KEY_BLEND           2
+#      define R300_MC_ROUND_NORMAL            (0<<2)
+#      define R300_MC_ROUND_MPEG4             (1<<2)
 #      define R300_LOD_BIAS_MASK           0x1fff
+#      define R300_EDGE_ANISO_EDGE_DIAG       (0<<13)
+#      define R300_EDGE_ANISO_EDGE_ONLY       (1<<13)
+#      define R300_MC_COORD_TRUNCATE_DISABLE  (0<<14)
+#      define R300_MC_COORD_TRUNCATE_MPEG     (1<<14)
+#      define R300_TX_TRI_PERF_0_8            (0<<15)
+#      define R300_TX_TRI_PERF_1_8            (1<<15)
+#      define R300_TX_TRI_PERF_1_4            (2<<15)
+#      define R300_TX_TRI_PERF_3_8            (3<<15)
+#      define R300_ANISO_THRESHOLD_MASK       (7<<17)
 
 #define R300_TX_SIZE_0                      0x4480
 #       define R300_TX_WIDTHMASK_SHIFT           0
@@ -722,6 +736,8 @@ I am fairly certain that they are correct unless stated otherwise in comments.
 #       define R300_TX_UNK23                     (1 << 23)
 #       define R300_TX_SIZE_SHIFT                26    /* largest of width, height */
 #       define R300_TX_SIZE_MASK                 (15 << 26)
+#       define R300_TX_SIZE_PROJECTED                     (1<<30)
+#       define R300_TX_SIZE_TXPITCH_EN                     (1<<31)
 #define R300_TX_FORMAT_0                    0x44C0
        /* The interpretation of the format word by Wladimir van der Laan */
        /* The X, Y, Z and W refer to the layout of the components.
@@ -750,7 +766,8 @@ I am fairly certain that they are correct unless stated otherwise in comments.
 #      define R300_TX_FORMAT_B8G8_B8G8             0x14        /* no swizzle */
 #      define R300_TX_FORMAT_G8R8_G8B8             0x15        /* no swizzle */
                                                  /* 0x16 - some 16 bit green format.. ?? */
-#      define R300_TX_FORMAT_UNK25                (1 << 25)    /* no swizzle */
+#      define R300_TX_FORMAT_UNK25                (1 << 25) /* no swizzle */
+#      define R300_TX_FORMAT_CUBIC_MAP            (1 << 26)
 
        /* gap */
        /* Floating point formats */
@@ -800,18 +817,20 @@ I am fairly certain that they are correct unless stated otherwise in comments.
 
 #      define R300_TX_FORMAT_YUV_MODE          0x00800000
 
-#define R300_TX_PITCH_0                            0x4500
+#define R300_TX_PITCH_0                            0x4500 /* obvious missing in gap */
 #define R300_TX_OFFSET_0                    0x4540
 /* BEGIN: Guess from R200 */
 #       define R300_TXO_ENDIAN_NO_SWAP           (0 << 0)
 #       define R300_TXO_ENDIAN_BYTE_SWAP         (1 << 0)
 #       define R300_TXO_ENDIAN_WORD_SWAP         (2 << 0)
 #       define R300_TXO_ENDIAN_HALFDW_SWAP       (3 << 0)
+#       define R300_TXO_MACRO_TILE               (1 << 2)
+#       define R300_TXO_MICRO_TILE               (1 << 3)
 #       define R300_TXO_OFFSET_MASK              0xffffffe0
 #       define R300_TXO_OFFSET_SHIFT             5
 /* END */
-#define R300_TX_UNK4_0                      0x4580
-#define R300_TX_BORDER_COLOR_0              0x45C0     //ff00ff00 == { 0, 1.0, 0, 1.0 }
+#define R300_TX_CHROMA_KEY_0                      0x4580 /* 32 bit chroma key */
+#define R300_TX_BORDER_COLOR_0              0x45C0 //ff00ff00 == { 0, 1.0, 0, 1.0 }
 
 /* END */
 
@@ -868,7 +887,9 @@ I am fairly certain that they are correct unless stated otherwise in comments.
 #       define R300_PFS_NODE_TEX_OFFSET_MASK     (31 << 12)
 #       define R300_PFS_NODE_TEX_END_SHIFT       17
 #       define R300_PFS_NODE_TEX_END_MASK        (31 << 17)
-#       define R300_PFS_NODE_LAST_NODE           (1 << 22)
+/*#       define R300_PFS_NODE_LAST_NODE           (1 << 22) */
+#              define R300_PFS_NODE_OUTPUT_COLOR        (1 << 22)
+#              define R300_PFS_NODE_OUTPUT_DEPTH        (1 << 23)
 
 /* TEX
 // As far as I can tell, texture instructions cannot write into output
@@ -887,6 +908,7 @@ I am fairly certain that they are correct unless stated otherwise in comments.
  */
 #              define R300_FPITX_OPCODE_SHIFT                  15
 #                      define R300_FPITX_OP_TEX                        1
+#                      define R300_FPITX_OP_KIL                        2
 #                      define R300_FPITX_OP_TXP                        3
 #                      define R300_FPITX_OP_TXB                        4
 
@@ -962,9 +984,11 @@ I am fairly certain that they are correct unless stated otherwise in comments.
 #       define R300_FPI1_SRC2C_CONST             (1 << 17)
 #       define R300_FPI1_DSTC_SHIFT              18
 #       define R300_FPI1_DSTC_MASK               (31 << 18)
+#              define R300_FPI1_DSTC_REG_MASK_SHIFT     23
 #       define R300_FPI1_DSTC_REG_X              (1 << 23)
 #       define R300_FPI1_DSTC_REG_Y              (1 << 24)
 #       define R300_FPI1_DSTC_REG_Z              (1 << 25)
+#              define R300_FPI1_DSTC_OUTPUT_MASK_SHIFT  26
 #       define R300_FPI1_DSTC_OUTPUT_X           (1 << 26)
 #       define R300_FPI1_DSTC_OUTPUT_Y           (1 << 27)
 #       define R300_FPI1_DSTC_OUTPUT_Z           (1 << 28)
@@ -983,6 +1007,7 @@ I am fairly certain that they are correct unless stated otherwise in comments.
 #       define R300_FPI3_DSTA_MASK               (31 << 18)
 #       define R300_FPI3_DSTA_REG                (1 << 23)
 #       define R300_FPI3_DSTA_OUTPUT             (1 << 24)
+#              define R300_FPI3_DSTA_DEPTH              (1 << 27)
 
 #define R300_PFS_INSTR0_0                   0x48C0
 #       define R300_FPI0_ARGC_SRC0C_XYZ          0
@@ -1036,7 +1061,7 @@ I am fairly certain that they are correct unless stated otherwise in comments.
 #       define R300_FPI0_OUTC_FRC                (9 << 23)
 #       define R300_FPI0_OUTC_REPL_ALPHA         (10 << 23)
 #       define R300_FPI0_OUTC_SAT                (1 << 30)
-#       define R300_FPI0_UNKNOWN_31              (1 << 31)
+#       define R300_FPI0_INSERT_NOP              (1 << 31)
 
 #define R300_PFS_INSTR2_0                   0x49C0
 #       define R300_FPI2_ARGA_SRC0C_X            0

diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c
index 9bb8ae0..7f949c9 100644 (file)
--- a/drivers/char/drm/radeon_cp.c
+++ b/drivers/char/drm/radeon_cp.c
@@ -1118,14 +1118,20 @@ static void radeon_cp_init_ring_buffer(drm_device_t * dev,
 {
        u32 ring_start, cur_read_ptr;
        u32 tmp;
-
-       /* Initialize the memory controller */
-       RADEON_WRITE(RADEON_MC_FB_LOCATION,
-                    ((dev_priv->gart_vm_start - 1) & 0xffff0000)
-                    | (dev_priv->fb_location >> 16));
+       
+       /* Initialize the memory controller. With new memory map, the fb location
+        * is not changed, it should have been properly initialized already. Part
+        * of the problem is that the code below is bogus, assuming the GART is
+        * always appended to the fb which is not necessarily the case
+        */
+       if (!dev_priv->new_memmap)
+               RADEON_WRITE(RADEON_MC_FB_LOCATION,
+                            ((dev_priv->gart_vm_start - 1) & 0xffff0000)
+                            | (dev_priv->fb_location >> 16));
 
 #if __OS_HAS_AGP
        if (dev_priv->flags & CHIP_IS_AGP) {
+               RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
                RADEON_WRITE(RADEON_MC_AGP_LOCATION,
                             (((dev_priv->gart_vm_start - 1 +
                                dev_priv->gart_size) & 0xffff0000) |
@@ -1153,8 +1159,6 @@ static void radeon_cp_init_ring_buffer(drm_device_t * dev,
 
 #if __OS_HAS_AGP
        if (dev_priv->flags & CHIP_IS_AGP) {
-               /* set RADEON_AGP_BASE here instead of relying on X from user space */
-               RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
                RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
                             dev_priv->ring_rptr->offset
                             - dev->agp->base + dev_priv->gart_vm_start);
@@ -1174,6 +1178,17 @@ static void radeon_cp_init_ring_buffer(drm_device_t * dev,
                          entry->handle + tmp_ofs);
        }
 
+       /* Set ring buffer size */
+#ifdef __BIG_ENDIAN
+       RADEON_WRITE(RADEON_CP_RB_CNTL,
+                    dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT);
+#else
+       RADEON_WRITE(RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw);
+#endif
+
+       /* Start with assuming that writeback doesn't work */
+       dev_priv->writeback_works = 0;
+
        /* Initialize the scratch register pointer.  This will cause
         * the scratch register values to be written out to memory
         * whenever they are updated.
@@ -1190,28 +1205,9 @@ static void radeon_cp_init_ring_buffer(drm_device_t * dev,
 
        RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
 
-       /* Writeback doesn't seem to work everywhere, test it first */
-       DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
-       RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
-
-       for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
-               if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
-                   0xdeadbeef)
-                       break;
-               DRM_UDELAY(1);
-       }
-
-       if (tmp < dev_priv->usec_timeout) {
-               dev_priv->writeback_works = 1;
-               DRM_DEBUG("writeback test succeeded, tmp=%d\n", tmp);
-       } else {
-               dev_priv->writeback_works = 0;
-               DRM_DEBUG("writeback test failed\n");
-       }
-       if (radeon_no_wb == 1) {
-               dev_priv->writeback_works = 0;
-               DRM_DEBUG("writeback forced off\n");
-       }
+       /* Turn on bus mastering */
+       tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
+       RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 
        dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
        RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
@@ -1223,26 +1219,45 @@ static void radeon_cp_init_ring_buffer(drm_device_t * dev,
        dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
        RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
 
-       /* Set ring buffer size */
-#ifdef __BIG_ENDIAN
-       RADEON_WRITE(RADEON_CP_RB_CNTL,
-                    dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT);
-#else
-       RADEON_WRITE(RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw);
-#endif
-
        radeon_do_wait_for_idle(dev_priv);
 
-       /* Turn on bus mastering */
-       tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
-       RADEON_WRITE(RADEON_BUS_CNTL, tmp);
-
        /* Sync everything up */
        RADEON_WRITE(RADEON_ISYNC_CNTL,
                     (RADEON_ISYNC_ANY2D_IDLE3D |
                      RADEON_ISYNC_ANY3D_IDLE2D |
                      RADEON_ISYNC_WAIT_IDLEGUI |
                      RADEON_ISYNC_CPSCRATCH_IDLEGUI));
+
+}
+
+static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
+{
+       u32 tmp;
+
+       /* Writeback doesn't seem to work everywhere, test it here and possibly
+        * enable it if it appears to work
+        */
+       DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
+       RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
+
+       for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
+               if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
+                   0xdeadbeef)
+                       break;
+               DRM_UDELAY(1);
+       }
+
+       if (tmp < dev_priv->usec_timeout) {
+               dev_priv->writeback_works = 1;
+               DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
+       } else {
+               dev_priv->writeback_works = 0;
+               DRM_INFO("writeback test failed\n");
+       }
+       if (radeon_no_wb == 1) {
+               dev_priv->writeback_works = 0;
+               DRM_INFO("writeback forced off\n");
+       }
 }
 
 /* Enable or disable PCI-E GART on the chip */
@@ -1317,6 +1332,14 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
 
        DRM_DEBUG("\n");
 
+       /* if we require new memory map but we don't have it fail */
+       if ((dev_priv->flags & CHIP_NEW_MEMMAP) && !dev_priv->new_memmap)
+       {
+               DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX\n");
+               radeon_do_cleanup_cp(dev);
+               return DRM_ERR(EINVAL);
+       }
+
        if (init->is_pci && (dev_priv->flags & CHIP_IS_AGP))
        {
                DRM_DEBUG("Forcing AGP card to PCI mode\n");
@@ -1496,6 +1519,9 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
 
        dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION)
                                 & 0xffff) << 16;
+       dev_priv->fb_size = 
+               ((RADEON_READ(RADEON_MC_FB_LOCATION) & 0xffff0000u) + 0x10000)
+               - dev_priv->fb_location;
 
        dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
                                        ((dev_priv->front_offset
@@ -1510,8 +1536,46 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
                                          + dev_priv->fb_location) >> 10));
 
        dev_priv->gart_size = init->gart_size;
-       dev_priv->gart_vm_start = dev_priv->fb_location
-           + RADEON_READ(RADEON_CONFIG_APER_SIZE);
+
+       /* New let's set the memory map ... */
+       if (dev_priv->new_memmap) {
+               u32 base = 0;
+
+               DRM_INFO("Setting GART location based on new memory map\n");
+
+               /* If using AGP, try to locate the AGP aperture at the same
+                * location in the card and on the bus, though we have to
+                * align it down.
+                */
+#if __OS_HAS_AGP
+               if (dev_priv->flags & CHIP_IS_AGP) {
+                       base = dev->agp->base;
+                       /* Check if valid */
+                       if ((base + dev_priv->gart_size) > dev_priv->fb_location &&
+                           base < (dev_priv->fb_location + dev_priv->fb_size)) {
+                               DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
+                                        dev->agp->base);
+                               base = 0;
+                       }
+               }
+#endif
+               /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
+               if (base == 0) {
+                       base = dev_priv->fb_location + dev_priv->fb_size;
+                       if (((base + dev_priv->gart_size) & 0xfffffffful)
+                           < base)
+                               base = dev_priv->fb_location
+                                       - dev_priv->gart_size;
+               }               
+               dev_priv->gart_vm_start = base & 0xffc00000u;
+               if (dev_priv->gart_vm_start != base)
+                       DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
+                                base, dev_priv->gart_vm_start);
+       } else {
+               DRM_INFO("Setting GART location based on old memory map\n");
+               dev_priv->gart_vm_start = dev_priv->fb_location +
+                       RADEON_READ(RADEON_CONFIG_APER_SIZE);
+       }
 
 #if __OS_HAS_AGP
        if (dev_priv->flags & CHIP_IS_AGP)
@@ -1596,6 +1660,7 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
        dev_priv->last_buf = 0;
 
        radeon_do_engine_reset(dev);
+       radeon_test_writeback(dev_priv);
 
        return 0;
 }

diff --git a/drivers/char/drm/radeon_drm.h b/drivers/char/drm/radeon_drm.h
index 9c177a6..c8e279e 100644 (file)
--- a/drivers/char/drm/radeon_drm.h
+++ b/drivers/char/drm/radeon_drm.h
@@ -222,6 +222,7 @@ typedef union {
 #      define R300_WAIT_3D             0x2
 #      define R300_WAIT_2D_CLEAN       0x3
 #      define R300_WAIT_3D_CLEAN       0x4
+#define R300_CMD_SCRATCH               8
 
 typedef union {
        unsigned int u;
@@ -247,6 +248,9 @@ typedef union {
        struct {
                unsigned char cmd_type, flags, pad0, pad1;
        } wait;
+       struct {
+               unsigned char cmd_type, reg, n_bufs, flags;
+       } scratch;
 } drm_r300_cmd_header_t;
 
 #define RADEON_FRONT                   0x1
@@ -697,6 +701,7 @@ typedef struct drm_radeon_setparam {
 #define RADEON_SETPARAM_FB_LOCATION    1       /* determined framebuffer location */
 #define RADEON_SETPARAM_SWITCH_TILING  2       /* enable/disable color tiling */
 #define RADEON_SETPARAM_PCIGART_LOCATION 3     /* PCI Gart Location */
+#define RADEON_SETPARAM_NEW_MEMMAP 4           /* Use new memory map */
 
 /* 1.14: Clients can allocate/free a surface
  */

diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h
index 1f7d2ab..78345ce 100644 (file)
--- a/drivers/char/drm/radeon_drv.h
+++ b/drivers/char/drm/radeon_drv.h
@@ -38,7 +38,7 @@
 
 #define DRIVER_NAME            "radeon"
 #define DRIVER_DESC            "ATI Radeon"
-#define DRIVER_DATE            "20051229"
+#define DRIVER_DATE            "20060225"
 
 /* Interface history:
  *
@@ -91,9 +91,11 @@
  * 1.20- Add support for r300 texrect
  * 1.21- Add support for card type getparam
  * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
+ * 1.23- Add new radeon memory map work from benh
+ * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
  */
 #define DRIVER_MAJOR           1
-#define DRIVER_MINOR           22
+#define DRIVER_MINOR           24
 #define DRIVER_PATCHLEVEL      0
 
 /*
@@ -101,20 +103,21 @@
  */
 enum radeon_family {
        CHIP_R100,
-       CHIP_RS100,
        CHIP_RV100,
+       CHIP_RS100,
        CHIP_RV200,
-       CHIP_R200,
        CHIP_RS200,
-       CHIP_R250,
-       CHIP_RS250,
+       CHIP_R200,
        CHIP_RV250,
+       CHIP_RS300,
        CHIP_RV280,
        CHIP_R300,
-       CHIP_RS300,
        CHIP_R350,
        CHIP_RV350,
+       CHIP_RV380,
        CHIP_R420,
+       CHIP_RV410,
+       CHIP_RS400,
        CHIP_LAST,
 };
 
@@ -136,9 +139,11 @@ enum radeon_chip_flags {
        CHIP_IS_AGP = 0x00080000UL,
        CHIP_HAS_HIERZ = 0x00100000UL,
        CHIP_IS_PCIE = 0x00200000UL,
+       CHIP_NEW_MEMMAP = 0x00400000UL,
 };
 
-#define GET_RING_HEAD(dev_priv)                DRM_READ32(  (dev_priv)->ring_rptr, 0 )
+#define GET_RING_HEAD(dev_priv)        (dev_priv->writeback_works ? \
+        DRM_READ32(  (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR))
 #define SET_RING_HEAD(dev_priv,val)    DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
 
 typedef struct drm_radeon_freelist {
@@ -199,6 +204,8 @@ typedef struct drm_radeon_private {
        drm_radeon_sarea_t *sarea_priv;
 
        u32 fb_location;
+       u32 fb_size;
+       int new_memmap;
 
        int gart_size;
        u32 gart_vm_start;
@@ -272,6 +279,8 @@ typedef struct drm_radeon_private {
        unsigned long pcigart_offset;
        drm_ati_pcigart_info gart_info;
 
+       u32 scratch_ages[5];
+
        /* starting from here on, data is preserved accross an open */
        uint32_t flags;         /* see radeon_chip_flags */
 } drm_radeon_private_t;

diff --git a/drivers/char/drm/radeon_state.c b/drivers/char/drm/radeon_state.c
index 7bc2751..c5b8f77 100644 (file)
--- a/drivers/char/drm/radeon_state.c
+++ b/drivers/char/drm/radeon_state.c
@@ -45,22 +45,53 @@ static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t *
        u32 off = *offset;
        struct drm_radeon_driver_file_fields *radeon_priv;
 
-       if (off >= dev_priv->fb_location &&
-           off < (dev_priv->gart_vm_start + dev_priv->gart_size))
-               return 0;
-
-       radeon_priv = filp_priv->driver_priv;
-       off += radeon_priv->radeon_fb_delta;
+       /* Hrm ... the story of the offset ... So this function converts
+        * the various ideas of what userland clients might have for an
+        * offset in the card address space into an offset into the card
+        * address space :) So with a sane client, it should just keep
+        * the value intact and just do some boundary checking. However,
+        * not all clients are sane. Some older clients pass us 0 based
+        * offsets relative to the start of the framebuffer and some may
+        * assume the AGP aperture it appended to the framebuffer, so we
+        * try to detect those cases and fix them up.
+        *
+        * Note: It might be a good idea here to make sure the offset lands
+        * in some "allowed" area to protect things like the PCIE GART...
+        */
 
-       DRM_DEBUG("offset fixed up to 0x%x\n", off);
+       /* First, the best case, the offset already lands in either the
+        * framebuffer or the GART mapped space
+        */
+       if ((off >= dev_priv->fb_location &&
+            off < (dev_priv->fb_location + dev_priv->fb_size)) ||
+           (off >= dev_priv->gart_vm_start &&
+            off < (dev_priv->gart_vm_start + dev_priv->gart_size)))
+               return 0;
 
-       if (off < dev_priv->fb_location ||
-           off >= (dev_priv->gart_vm_start + dev_priv->gart_size))
-               return DRM_ERR(EINVAL);
+       /* Ok, that didn't happen... now check if we have a zero based
+        * offset that fits in the framebuffer + gart space, apply the
+        * magic offset we get from SETPARAM or calculated from fb_location
+        */
+       if (off < (dev_priv->fb_size + dev_priv->gart_size)) {
+               radeon_priv = filp_priv->driver_priv;
+               off += radeon_priv->radeon_fb_delta;
+       }
 
-       *offset = off;
+       /* Finally, assume we aimed at a GART offset if beyond the fb */
+       if (off > (dev_priv->fb_location + dev_priv->fb_size))
+               off = off - (dev_priv->fb_location + dev_priv->fb_size) +
+                       dev_priv->gart_vm_start;
 
-       return 0;
+       /* Now recheck and fail if out of bounds */
+       if ((off >= dev_priv->fb_location &&
+            off < (dev_priv->fb_location + dev_priv->fb_size)) ||
+           (off >= dev_priv->gart_vm_start &&
+            off < (dev_priv->gart_vm_start + dev_priv->gart_size))) {
+               DRM_DEBUG("offset fixed up to 0x%x\n", off);
+               *offset = off;
+               return 0;
+       }
+       return DRM_ERR(EINVAL);
 }
 
 static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
@@ -1939,11 +1970,6 @@ static int radeon_surface_alloc(DRM_IOCTL_ARGS)
        drm_radeon_private_t *dev_priv = dev->dev_private;
        drm_radeon_surface_alloc_t alloc;
 
-       if (!dev_priv) {
-               DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
-               return DRM_ERR(EINVAL);
-       }
-
        DRM_COPY_FROM_USER_IOCTL(alloc,
                                 (drm_radeon_surface_alloc_t __user *) data,
                                 sizeof(alloc));
@@ -1960,12 +1986,7 @@ static int radeon_surface_free(DRM_IOCTL_ARGS)
        drm_radeon_private_t *dev_priv = dev->dev_private;
        drm_radeon_surface_free_t memfree;
 
-       if (!dev_priv) {
-               DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
-               return DRM_ERR(EINVAL);
-       }
-
-       DRM_COPY_FROM_USER_IOCTL(memfree, (drm_radeon_mem_free_t __user *) data,
+       DRM_COPY_FROM_USER_IOCTL(memfree, (drm_radeon_surface_free_t __user *) data,
                                 sizeof(memfree));
 
        if (free_surface(filp, dev_priv, memfree.address))
@@ -2100,11 +2121,6 @@ static int radeon_cp_vertex(DRM_IOCTL_ARGS)
 
        LOCK_TEST_WITH_RETURN(dev, filp);
 
-       if (!dev_priv) {
-               DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
-               return DRM_ERR(EINVAL);
-       }
-
        DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
 
        DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex_t __user *) data,
@@ -2189,11 +2205,6 @@ static int radeon_cp_indices(DRM_IOCTL_ARGS)
 
        LOCK_TEST_WITH_RETURN(dev, filp);
 
-       if (!dev_priv) {
-               DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
-               return DRM_ERR(EINVAL);
-       }
-
        DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
 
        DRM_COPY_FROM_USER_IOCTL(elts, (drm_radeon_indices_t __user *) data,
@@ -2340,11 +2351,6 @@ static int radeon_cp_indirect(DRM_IOCTL_ARGS)
 
        LOCK_TEST_WITH_RETURN(dev, filp);
 
-       if (!dev_priv) {
-               DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
-               return DRM_ERR(EINVAL);
-       }
-
        DRM_COPY_FROM_USER_IOCTL(indirect,
                                 (drm_radeon_indirect_t __user *) data,
                                 sizeof(indirect));
@@ -2417,11 +2423,6 @@ static int radeon_cp_vertex2(DRM_IOCTL_ARGS)
 
        LOCK_TEST_WITH_RETURN(dev, filp);
 
-       if (!dev_priv) {
-               DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
-               return DRM_ERR(EINVAL);
-       }
-
        DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
 
        DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex2_t __user *) data,
@@ -2738,11 +2739,6 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS)
 
        LOCK_TEST_WITH_RETURN(dev, filp);
 
-       if (!dev_priv) {
-               DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
-               return DRM_ERR(EINVAL);
-       }
-
        DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
 
        DRM_COPY_FROM_USER_IOCTL(cmdbuf,
@@ -2897,11 +2893,6 @@ static int radeon_cp_getparam(DRM_IOCTL_ARGS)
        drm_radeon_getparam_t param;
        int value;
 
-       if (!dev_priv) {
-               DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
-               return DRM_ERR(EINVAL);
-       }
-
        DRM_COPY_FROM_USER_IOCTL(param, (drm_radeon_getparam_t __user *) data,
                                 sizeof(param));
 
@@ -2981,11 +2972,6 @@ static int radeon_cp_setparam(DRM_IOCTL_ARGS)
        drm_radeon_setparam_t sp;
        struct drm_radeon_driver_file_fields *radeon_priv;
 
-       if (!dev_priv) {
-               DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
-               return DRM_ERR(EINVAL);
-       }
-
        DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
 
        DRM_COPY_FROM_USER_IOCTL(sp, (drm_radeon_setparam_t __user *) data,
@@ -3012,6 +2998,9 @@ static int radeon_cp_setparam(DRM_IOCTL_ARGS)
        case RADEON_SETPARAM_PCIGART_LOCATION:
                dev_priv->pcigart_offset = sp.value;
                break;
+       case RADEON_SETPARAM_NEW_MEMMAP:
+               dev_priv->new_memmap = sp.value;
+               break;
        default:
                DRM_DEBUG("Invalid parameter %d\n", sp.param);
                return DRM_ERR(EINVAL);

diff --git a/drivers/char/drm/sis_mm.c b/drivers/char/drm/sis_mm.c
index 6774d2f..5e9936b 100644 (file)
--- a/drivers/char/drm/sis_mm.c
+++ b/drivers/char/drm/sis_mm.c
@@ -110,7 +110,7 @@ static int sis_fb_alloc(DRM_IOCTL_ARGS)
 
        DRM_COPY_TO_USER_IOCTL(argp, fb, sizeof(fb));
 
-       DRM_DEBUG("alloc fb, size = %d, offset = %ld\n", fb.size, req.offset);
+       DRM_DEBUG("alloc fb, size = %d, offset = %d\n", fb.size, req.offset);
 
        return retval;
 }