DSS2: DSI: calculate VP_CLK_RATIO properly

diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
index 4442931..aecb89d 100644 (file)
--- a/drivers/video/omap2/dss/dsi.c
+++ b/drivers/video/omap2/dss/dsi.c
@@ -1104,7 +1104,10 @@ int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv)
        enable_clocks(1);
        dsi_enable_pll_clock(1);
 
-       /* configure dispc fck and pixel clock to something sane */
+       /* XXX this should be calculated depending on the screen size,
+        * required framerate and DSI speed.
+        * For now 48MHz is enough for 864x480@60 with 360Mbps/lane
+        * with two lanes */
        r = dispc_calc_clock_div(1, 48 * 1000 * 1000, &cinfo);
        if (r)
                goto err0;
@@ -1119,7 +1122,7 @@ int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv)
        if (r)
                goto err0;
 
-       /* PLL does not come out of reset without this... */
+       /* XXX PLL does not come out of reset without this... */
        dispc_pck_free_enable(1);
 
        if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
@@ -1128,8 +1131,8 @@ int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv)
                goto err1;
        }
 
-       /* ... but if left on, we get problems when planes do not
-        * fill the whole display. No idea about this XXX */
+       /* XXX ... but if left on, we get problems when planes do not
+        * fill the whole display. No idea about this */
        dispc_pck_free_enable(0);
 
        if (enable_hsclk && enable_hsdiv)
@@ -2214,6 +2217,7 @@ static int dsi_proto_config(struct omap_display *display)
 {
        u32 r;
        int buswidth = 0;
+       int div;
 
        dsi_config_tx_fifo(DSI_FIFO_SIZE_128,
                        DSI_FIFO_SIZE_0,
@@ -2254,8 +2258,9 @@ static int dsi_proto_config(struct omap_display *display)
        r = FLD_MOD(r, 1, 1, 1);        /* CS_RX_EN */
        r = FLD_MOD(r, 1, 2, 2);        /* ECC_RX_EN */
        r = FLD_MOD(r, 1, 3, 3);        /* TX_FIFO_ARBITRATION */
-       /* XXX what should the ratio be */
-       r = FLD_MOD(r, 0, 4, 4);        /* VP_CLK_RATIO, VP_PCLK = VP_CLK/2 */
+
+       div = dispc_lclk_rate() / dispc_pclk_rate();
+       r = FLD_MOD(r, div == 2 ? 0 : 1, 4, 4); /* VP_CLK_RATIO */
        r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
        r = FLD_MOD(r, 0, 8, 8);        /* VP_CLK_POL */
        r = FLD_MOD(r, 2, 13, 12);      /* LINE_BUFFER, 2 lines */