Merge branch 'upstream-greg' of gregkh@master.kernel.org:/pub/scm/linux/kernel/git...
authorGreg Kroah-Hartman <gregkh@suse.de>
Thu, 24 Aug 2006 04:58:48 +0000 (21:58 -0700)
committerGreg Kroah-Hartman <gregkh@suse.de>
Thu, 24 Aug 2006 04:58:48 +0000 (21:58 -0700)
81 files changed:
arch/ppc/platforms/85xx/mpc8560_ads.c
arch/ppc/platforms/85xx/mpc85xx_ads_common.h
arch/ppc/platforms/mpc8272ads_setup.c
arch/ppc/platforms/mpc866ads_setup.c
arch/ppc/platforms/mpc885ads_setup.c
arch/ppc/platforms/pq2ads_pd.h
arch/ppc/syslib/mpc85xx_devices.c
arch/ppc/syslib/mpc8xx_devices.c
arch/ppc/syslib/mpc8xx_sys.c
arch/ppc/syslib/pq2_devices.c
arch/ppc/syslib/pq2_sys.c
drivers/net/3c515.c
drivers/net/82596.c
drivers/net/Kconfig
drivers/net/Makefile
drivers/net/ac3200.c
drivers/net/appletalk/cops.c
drivers/net/at1700.c
drivers/net/cs89x0.c
drivers/net/dm9000.c
drivers/net/e1000/e1000_hw.c
drivers/net/e1000/e1000_hw.h
drivers/net/e1000/e1000_main.c
drivers/net/e2100.c
drivers/net/eepro.c
drivers/net/eexpress.c
drivers/net/es3210.c
drivers/net/eth16i.c
drivers/net/fealnx.c
drivers/net/fs_enet/Makefile
drivers/net/fs_enet/fec.h [new file with mode: 0644]
drivers/net/fs_enet/fs_enet-main.c
drivers/net/fs_enet/fs_enet-mii.c [deleted file]
drivers/net/fs_enet/fs_enet.h
drivers/net/fs_enet/mac-fcc.c
drivers/net/fs_enet/mac-fec.c
drivers/net/fs_enet/mac-scc.c
drivers/net/fs_enet/mii-bitbang.c
drivers/net/fs_enet/mii-fec.c [new file with mode: 0644]
drivers/net/fs_enet/mii-fixed.c [deleted file]
drivers/net/lance.c
drivers/net/lne390.c
drivers/net/ni52.c
drivers/net/ni65.c
drivers/net/pcmcia/xirc2ps_cs.c
drivers/net/pcnet32.c
drivers/net/phy/Kconfig
drivers/net/phy/Makefile
drivers/net/phy/fixed.c [new file with mode: 0644]
drivers/net/phy/mdio_bus.c
drivers/net/phy/phy_device.c
drivers/net/s2io.c
drivers/net/seeq8005.c
drivers/net/skge.c
drivers/net/sky2.c
drivers/net/smc911x.c
drivers/net/smc91x.c
drivers/net/smc91x.h
drivers/net/spider_net.c
drivers/net/spider_net.h
drivers/net/spider_net_ethtool.c
drivers/net/sundance.c
drivers/net/tokenring/ibmtr.c
drivers/net/tokenring/smctr.c
drivers/net/tulip/winbond-840.c
drivers/net/tulip/xircom_cb.c
drivers/net/ucc_geth.c [new file with mode: 0644]
drivers/net/ucc_geth.h [new file with mode: 0644]
drivers/net/ucc_geth_phy.c [new file with mode: 0644]
drivers/net/ucc_geth_phy.h [new file with mode: 0644]
drivers/net/via-rhine.c
drivers/net/wan/c101.c
drivers/net/wd.c
drivers/net/wireless/hostap/hostap_hw.c
drivers/net/wireless/spectrum_cs.c
drivers/s390/net/qeth_main.c
include/asm-ppc/cpm2.h
include/asm-ppc/mpc8260.h
include/asm-ppc/mpc8xx.h
include/linux/fs_enet_pd.h
include/linux/phy.h

index d90cd24..94badaf 100644 (file)
@@ -29,6 +29,7 @@
 #include <linux/initrd.h>
 #include <linux/module.h>
 #include <linux/fsl_devices.h>
+#include <linux/fs_enet_pd.h>
 
 #include <asm/system.h>
 #include <asm/pgtable.h>
  * Setup the architecture
  *
  */
+static void init_fcc_ioports(void)
+{
+       struct immap *immap;
+       struct io_port *io;
+       u32 tempval;
+
+       immap = cpm2_immr;
+
+       io = &immap->im_ioport;
+       /* FCC2/3 are on the ports B/C. */
+       tempval = in_be32(&io->iop_pdirb);
+       tempval &= ~PB2_DIRB0;
+       tempval |= PB2_DIRB1;
+       out_be32(&io->iop_pdirb, tempval);
+
+       tempval = in_be32(&io->iop_psorb);
+       tempval &= ~PB2_PSORB0;
+       tempval |= PB2_PSORB1;
+       out_be32(&io->iop_psorb, tempval);
+
+       tempval = in_be32(&io->iop_pparb);
+       tempval |= (PB2_DIRB0 | PB2_DIRB1);
+       out_be32(&io->iop_pparb, tempval);
+
+       tempval = in_be32(&io->iop_pdirb);
+       tempval &= ~PB3_DIRB0;
+       tempval |= PB3_DIRB1;
+       out_be32(&io->iop_pdirb, tempval);
+
+       tempval = in_be32(&io->iop_psorb);
+       tempval &= ~PB3_PSORB0;
+       tempval |= PB3_PSORB1;
+       out_be32(&io->iop_psorb, tempval);
+
+       tempval = in_be32(&io->iop_pparb);
+       tempval |= (PB3_DIRB0 | PB3_DIRB1);
+       out_be32(&io->iop_pparb, tempval);
+
+        tempval = in_be32(&io->iop_pdirc);
+        tempval |= PC3_DIRC1;
+        out_be32(&io->iop_pdirc, tempval);
+
+        tempval = in_be32(&io->iop_pparc);
+        tempval |= PC3_DIRC1;
+        out_be32(&io->iop_pparc, tempval);
+
+       /* Port C has clocks......  */
+       tempval = in_be32(&io->iop_psorc);
+       tempval &= ~(CLK_TRX);
+       out_be32(&io->iop_psorc, tempval);
+
+       tempval = in_be32(&io->iop_pdirc);
+       tempval &= ~(CLK_TRX);
+       out_be32(&io->iop_pdirc, tempval);
+       tempval = in_be32(&io->iop_pparc);
+       tempval |= (CLK_TRX);
+       out_be32(&io->iop_pparc, tempval);
+
+       /* Configure Serial Interface clock routing.
+        * First,  clear all FCC bits to zero,
+        * then set the ones we want.
+        */
+       immap->im_cpmux.cmx_fcr &= ~(CPMUX_CLK_MASK);
+       immap->im_cpmux.cmx_fcr |= CPMUX_CLK_ROUTE;
+}
 
 static void __init
 mpc8560ads_setup_arch(void)
@@ -66,6 +132,7 @@ mpc8560ads_setup_arch(void)
        unsigned int freq;
        struct gianfar_platform_data *pdata;
        struct gianfar_mdio_data *mdata;
+       struct fs_platform_info *fpi;
 
        cpm2_reset();
 
@@ -110,6 +177,28 @@ mpc8560ads_setup_arch(void)
                memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
        }
 
+       init_fcc_ioports();
+       ppc_sys_device_remove(MPC85xx_CPM_FCC1);
+
+       fpi = (struct fs_platform_info *) ppc_sys_get_pdata(MPC85xx_CPM_FCC2);
+       if (fpi) {
+               memcpy(fpi->macaddr, binfo->bi_enet2addr, 6);
+               fpi->bus_id = "0:02";
+               fpi->phy_addr = 2;
+               fpi->dpram_offset = (u32)cpm2_immr->im_dprambase;
+               fpi->fcc_regs_c = (u32)&cpm2_immr->im_fcc_c[1];
+       }
+
+       fpi = (struct fs_platform_info *) ppc_sys_get_pdata(MPC85xx_CPM_FCC3);
+       if (fpi) {
+               memcpy(fpi->macaddr, binfo->bi_enet2addr, 6);
+               fpi->macaddr[5] += 1;
+               fpi->bus_id = "0:03";
+               fpi->phy_addr = 3;
+               fpi->dpram_offset = (u32)cpm2_immr->im_dprambase;
+               fpi->fcc_regs_c = (u32)&cpm2_immr->im_fcc_c[2];
+       }
+
 #ifdef CONFIG_BLK_DEV_INITRD
        if (initrd_start)
                ROOT_DEV = Root_RAM0;
index abf3228..c8c322f 100644 (file)
@@ -45,4 +45,23 @@ extern void mpc85xx_ads_map_io(void) __init;
 
 #define MPC85XX_PCI1_IO_SIZE   0x01000000
 
+/* FCC1 Clock Source Configuration.  These can be
+ * redefined in the board specific file.
+ *    Can only choose from CLK9-12 */
+#define F1_RXCLK       12
+#define F1_TXCLK       11
+
+/* FCC2 Clock Source Configuration.  These can be
+ * redefined in the board specific file.
+ *    Can only choose from CLK13-16 */
+#define F2_RXCLK       13
+#define F2_TXCLK       14
+
+/* FCC3 Clock Source Configuration.  These can be
+ * redefined in the board specific file.
+ *    Can only choose from CLK13-16 */
+#define F3_RXCLK       15
+#define F3_TXCLK       16
+
+
 #endif                         /* __MACH_MPC85XX_ADS_H__ */
index abb7154..2a35fe2 100644 (file)
@@ -56,64 +56,51 @@ static struct fs_uart_platform_info mpc8272_uart_pdata[] = {
        },
 };
 
-static struct fs_mii_bus_info mii_bus_info = {
-       .method                 = fsmii_bitbang,
-       .id                     = 0,
-       .i.bitbang = {
-               .mdio_port      = fsiop_portc,
-               .mdio_bit       = 18,
-               .mdc_port       = fsiop_portc,
-               .mdc_bit        = 19,
-               .delay          = 1,
-       },
-};
-
-static struct fs_platform_info mpc82xx_fcc1_pdata = {
-       .fs_no          = fsid_fcc1,
-       .cp_page        = CPM_CR_FCC1_PAGE,
-       .cp_block       = CPM_CR_FCC1_SBLOCK,
-       .clk_trx        = (PC_F1RXCLK | PC_F1TXCLK),
-       .clk_route      = CMX1_CLK_ROUTE,
-       .clk_mask       = CMX1_CLK_MASK,
-       .init_ioports   = init_fcc1_ioports,
-
-       .phy_addr       = 0,
-#ifdef PHY_INTERRUPT
-       .phy_irq        = PHY_INTERRUPT,
-#else
-       .phy_irq        = -1;
-#endif
-       .mem_offset     = FCC1_MEM_OFFSET,
-       .bus_info       = &mii_bus_info,
-       .rx_ring        = 32,
-       .tx_ring        = 32,
-       .rx_copybreak   = 240,
-       .use_napi       = 0,
-       .napi_weight    = 17,
+static struct fs_mii_bb_platform_info m82xx_mii_bb_pdata = {
+       .mdio_dat.bit   = 18,
+       .mdio_dir.bit   = 18,
+       .mdc_dat.bit    = 19,
+       .delay          = 1,
 };
 
-static struct fs_platform_info mpc82xx_fcc2_pdata = {
-       .fs_no          = fsid_fcc2,
-       .cp_page        = CPM_CR_FCC2_PAGE,
-       .cp_block       = CPM_CR_FCC2_SBLOCK,
-       .clk_trx        = (PC_F2RXCLK | PC_F2TXCLK),
-       .clk_route      = CMX2_CLK_ROUTE,
-       .clk_mask       = CMX2_CLK_MASK,
-       .init_ioports   = init_fcc2_ioports,
-
-       .phy_addr       = 3,
-#ifdef PHY_INTERRUPT
-       .phy_irq        = PHY_INTERRUPT,
-#else
-       .phy_irq        = -1;
-#endif
-       .mem_offset     = FCC2_MEM_OFFSET,
-       .bus_info       = &mii_bus_info,
-       .rx_ring        = 32,
-       .tx_ring        = 32,
-       .rx_copybreak   = 240,
-       .use_napi       = 0,
-       .napi_weight    = 17,
+static struct fs_platform_info mpc82xx_enet_pdata[] = {
+       [fsid_fcc1] = {
+               .fs_no          = fsid_fcc1,
+               .cp_page        = CPM_CR_FCC1_PAGE,
+               .cp_block       = CPM_CR_FCC1_SBLOCK,
+
+               .clk_trx        = (PC_F1RXCLK | PC_F1TXCLK),
+               .clk_route      = CMX1_CLK_ROUTE,
+               .clk_mask       = CMX1_CLK_MASK,
+               .init_ioports   = init_fcc1_ioports,
+
+               .mem_offset     = FCC1_MEM_OFFSET,
+
+               .rx_ring        = 32,
+               .tx_ring        = 32,
+               .rx_copybreak   = 240,
+               .use_napi       = 0,
+               .napi_weight    = 17,
+               .bus_id         = "0:00",
+       },
+       [fsid_fcc2] = {
+               .fs_no          = fsid_fcc2,
+               .cp_page        = CPM_CR_FCC2_PAGE,
+               .cp_block       = CPM_CR_FCC2_SBLOCK,
+               .clk_trx        = (PC_F2RXCLK | PC_F2TXCLK),
+               .clk_route      = CMX2_CLK_ROUTE,
+               .clk_mask       = CMX2_CLK_MASK,
+               .init_ioports   = init_fcc2_ioports,
+
+               .mem_offset     = FCC2_MEM_OFFSET,
+
+               .rx_ring        = 32,
+               .tx_ring        = 32,
+               .rx_copybreak   = 240,
+               .use_napi       = 0,
+               .napi_weight    = 17,
+               .bus_id         = "0:03",
+       },
 };
 
 static void init_fcc1_ioports(void)
@@ -209,20 +196,21 @@ static void __init mpc8272ads_fixup_enet_pdata(struct platform_device *pdev,
        bd_t* bi = (void*)__res;
        int fs_no = fsid_fcc1+pdev->id-1;
 
-       mpc82xx_fcc1_pdata.dpram_offset = mpc82xx_fcc2_pdata.dpram_offset = (u32)cpm2_immr->im_dprambase;
-       mpc82xx_fcc1_pdata.fcc_regs_c = mpc82xx_fcc2_pdata.fcc_regs_c = (u32)cpm2_immr->im_fcc_c;
-
-       switch(fs_no) {
-               case fsid_fcc1:
-                       memcpy(&mpc82xx_fcc1_pdata.macaddr,bi->bi_enetaddr,6);
-                       pdev->dev.platform_data = &mpc82xx_fcc1_pdata;
-               break;
-               case fsid_fcc2:
-                       memcpy(&mpc82xx_fcc2_pdata.macaddr,bi->bi_enetaddr,6);
-                       mpc82xx_fcc2_pdata.macaddr[5] ^= 1;
-                       pdev->dev.platform_data = &mpc82xx_fcc2_pdata;
-               break;
+       if(fs_no > ARRAY_SIZE(mpc82xx_enet_pdata)) {
+               return;
        }
+
+       mpc82xx_enet_pdata[fs_no].dpram_offset=
+                       (u32)cpm2_immr->im_dprambase;
+       mpc82xx_enet_pdata[fs_no].fcc_regs_c =
+                       (u32)cpm2_immr->im_fcc_c;
+       memcpy(&mpc82xx_enet_pdata[fs_no].macaddr,bi->bi_enetaddr,6);
+
+       /* prevent dup mac */
+       if(fs_no == fsid_fcc2)
+               mpc82xx_enet_pdata[fs_no].macaddr[5] ^= 1;
+
+       pdev->dev.platform_data = &mpc82xx_enet_pdata[fs_no];
 }
 
 static void mpc8272ads_fixup_uart_pdata(struct platform_device *pdev,
@@ -274,6 +262,29 @@ static void init_scc4_uart_ioports(void)
        iounmap(immap);
 }
 
+static void __init mpc8272ads_fixup_mdio_pdata(struct platform_device *pdev,
+                                             int idx)
+{
+       m82xx_mii_bb_pdata.irq[0] = PHY_INTERRUPT;
+       m82xx_mii_bb_pdata.irq[1] = -1;
+       m82xx_mii_bb_pdata.irq[2] = -1;
+       m82xx_mii_bb_pdata.irq[3] = PHY_INTERRUPT;
+       m82xx_mii_bb_pdata.irq[31] = -1;
+
+
+       m82xx_mii_bb_pdata.mdio_dat.offset =
+                               (u32)&cpm2_immr->im_ioport.iop_pdatc;
+
+       m82xx_mii_bb_pdata.mdio_dir.offset =
+                               (u32)&cpm2_immr->im_ioport.iop_pdirc;
+
+       m82xx_mii_bb_pdata.mdc_dat.offset =
+                               (u32)&cpm2_immr->im_ioport.iop_pdatc;
+
+
+       pdev->dev.platform_data = &m82xx_mii_bb_pdata;
+}
+
 static int mpc8272ads_platform_notify(struct device *dev)
 {
        static const struct platform_notify_dev_map dev_map[] = {
@@ -285,6 +296,10 @@ static int mpc8272ads_platform_notify(struct device *dev)
                        .bus_id = "fsl-cpm-scc:uart",
                        .rtn = mpc8272ads_fixup_uart_pdata,
                },
+               {
+                       .bus_id = "fsl-bb-mdio",
+                       .rtn = mpc8272ads_fixup_mdio_pdata,
+               },
                {
                        .bus_id = NULL
                }
@@ -319,6 +334,7 @@ int __init mpc8272ads_init(void)
        ppc_sys_device_enable(MPC82xx_CPM_SCC4);
 #endif
 
+       ppc_sys_device_enable(MPC82xx_MDIO_BB);
 
        return 0;
 }
index f19b616..e12cece 100644 (file)
@@ -1,10 +1,10 @@
-/*arch/ppc/platforms/mpc885ads-setup.c
+/*arch/ppc/platforms/mpc866ads-setup.c
  *
- * Platform setup for the Freescale mpc885ads board
+ * Platform setup for the Freescale mpc866ads board
  *
  * Vitaly Bordug <vbordug@ru.mvista.com>
  *
- * Copyright 2005 MontaVista Software Inc.
+ * Copyright 2005-2006 MontaVista Software Inc.
  *
  * This file is licensed under the terms of the GNU General Public License
  * version 2. This program is licensed "as is" without any warranty of any
@@ -42,49 +42,36 @@ static void setup_scc1_ioports(void);
 static void setup_smc1_ioports(void);
 static void setup_smc2_ioports(void);
 
-static struct fs_mii_bus_info fec_mii_bus_info = {
-       .method = fsmii_fec,
-       .id = 0,
-};
-
-static struct fs_mii_bus_info scc_mii_bus_info = {
-       .method = fsmii_fixed,
-       .id = 0,
-       .i.fixed.speed = 10,
-       .i.fixed.duplex = 0,
-};
+static struct fs_mii_fec_platform_info mpc8xx_mdio_fec_pdata;
 
-static struct fs_platform_info mpc8xx_fec_pdata[] = {
-       {
-        .rx_ring = 128,
-        .tx_ring = 16,
-        .rx_copybreak = 240,
+static struct fs_mii_fec_platform_info mpc8xx_mdio_fec_pdata;
 
-        .use_napi = 1,
-        .napi_weight = 17,
+static struct fs_platform_info mpc8xx_enet_pdata[] = {
+       [fsid_fec1] = {
+               .rx_ring = 128,
+               .tx_ring = 16,
+               .rx_copybreak = 240,
 
-        .phy_addr = 15,
-        .phy_irq = -1,
+               .use_napi = 1,
+               .napi_weight = 17,
 
-        .use_rmii = 0,
+               .init_ioports = setup_fec1_ioports,
 
-        .bus_info = &fec_mii_bus_info,
-        }
-};
+               .bus_id = "0:0f",
+               .has_phy = 1,
+       },
+       [fsid_scc1] = {
+               .rx_ring = 64,
+               .tx_ring = 8,
+               .rx_copybreak = 240,
+               .use_napi = 1,
+               .napi_weight = 17,
 
-static struct fs_platform_info mpc8xx_scc_pdata = {
-       .rx_ring = 64,
-       .tx_ring = 8,
-       .rx_copybreak = 240,
 
-       .use_napi = 1,
-       .napi_weight = 17,
-
-       .phy_addr = -1,
-       .phy_irq = -1,
-
-       .bus_info = &scc_mii_bus_info,
+               .init_ioports = setup_scc1_ioports,
 
+               .bus_id = "fixed@100:1",
+       },
 };
 
 static struct fs_uart_platform_info mpc866_uart_pdata[] = {
@@ -207,63 +194,6 @@ static void setup_scc1_ioports(void)
 
 }
 
-static void mpc866ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no)
-{
-       struct fs_platform_info *fpi = pdev->dev.platform_data;
-
-       volatile cpm8xx_t *cp;
-       bd_t *bd = (bd_t *) __res;
-       char *e;
-       int i;
-
-       /* Get pointer to Communication Processor */
-       cp = cpmp;
-       switch (fs_no) {
-       case fsid_fec1:
-               fpi = &mpc8xx_fec_pdata[0];
-               fpi->init_ioports = &setup_fec1_ioports;
-
-               break;
-       case fsid_scc1:
-               fpi = &mpc8xx_scc_pdata;
-               fpi->init_ioports = &setup_scc1_ioports;
-
-               break;
-       default:
-               printk(KERN_WARNING"Device %s is not supported!\n", pdev->name);
-               return;
-       }
-
-       pdev->dev.platform_data = fpi;
-       fpi->fs_no = fs_no;
-
-       e = (unsigned char *)&bd->bi_enetaddr;
-       for (i = 0; i < 6; i++)
-               fpi->macaddr[i] = *e++;
-
-       fpi->macaddr[5 - pdev->id]++;
-
-}
-
-static void mpc866ads_fixup_fec_enet_pdata(struct platform_device *pdev,
-                                          int idx)
-{
-       /* This is for FEC devices only */
-       if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-fec")))
-               return;
-       mpc866ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1);
-}
-
-static void mpc866ads_fixup_scc_enet_pdata(struct platform_device *pdev,
-                                          int idx)
-{
-       /* This is for SCC devices only */
-       if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-scc")))
-               return;
-
-       mpc866ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1);
-}
-
 static void setup_smc1_ioports(void)
 {
        immap_t *immap = (immap_t *) IMAP_ADDR;
@@ -315,6 +245,56 @@ static void setup_smc2_ioports(void)
 
 }
 
+static int ma_count = 0;
+
+static void mpc866ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no)
+{
+       struct fs_platform_info *fpi;
+
+       volatile cpm8xx_t *cp;
+       bd_t *bd = (bd_t *) __res;
+       char *e;
+       int i;
+
+       /* Get pointer to Communication Processor */
+       cp = cpmp;
+
+       if(fs_no > ARRAY_SIZE(mpc8xx_enet_pdata)) {
+               printk(KERN_ERR"No network-suitable #%d device on bus", fs_no);
+               return;
+       }
+
+
+       fpi = &mpc8xx_enet_pdata[fs_no];
+       fpi->fs_no = fs_no;
+       pdev->dev.platform_data = fpi;
+
+       e = (unsigned char *)&bd->bi_enetaddr;
+       for (i = 0; i < 6; i++)
+               fpi->macaddr[i] = *e++;
+
+       fpi->macaddr[5] += ma_count++;
+}
+
+static void mpc866ads_fixup_fec_enet_pdata(struct platform_device *pdev,
+                                          int idx)
+{
+       /* This is for FEC devices only */
+       if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-fec")))
+               return;
+       mpc866ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1);
+}
+
+static void mpc866ads_fixup_scc_enet_pdata(struct platform_device *pdev,
+                                          int idx)
+{
+       /* This is for SCC devices only */
+       if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-scc")))
+               return;
+
+       mpc866ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1);
+}
+
 static void __init mpc866ads_fixup_uart_pdata(struct platform_device *pdev,
                                               int idx)
 {
@@ -359,6 +339,9 @@ static int mpc866ads_platform_notify(struct device *dev)
 
 int __init mpc866ads_init(void)
 {
+       bd_t *bd = (bd_t *) __res;
+       struct fs_mii_fec_platform_info* fmpi;
+
        printk(KERN_NOTICE "mpc866ads: Init\n");
 
        platform_notify = mpc866ads_platform_notify;
@@ -366,11 +349,20 @@ int __init mpc866ads_init(void)
        ppc_sys_device_initfunc();
        ppc_sys_device_disable_all();
 
-#ifdef MPC8xx_SECOND_ETH_SCC1
+#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC1
        ppc_sys_device_enable(MPC8xx_CPM_SCC1);
 #endif
        ppc_sys_device_enable(MPC8xx_CPM_FEC1);
 
+       ppc_sys_device_enable(MPC8xx_MDIO_FEC);
+
+       fmpi = ppc_sys_platform_devices[MPC8xx_MDIO_FEC].dev.platform_data =
+               &mpc8xx_mdio_fec_pdata;
+
+       fmpi->mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1;
+       /* No PHY interrupt line here */
+       fmpi->irq[0xf] = -1;
+
 /* Since either of the uarts could be used as console, they need to ready */
 #ifdef CONFIG_SERIAL_CPM_SMC1
        ppc_sys_device_enable(MPC8xx_CPM_SMC1);
@@ -381,6 +373,14 @@ int __init mpc866ads_init(void)
        ppc_sys_device_enable(MPC8xx_CPM_SMC2);
        ppc_sys_device_setfunc(MPC8xx_CPM_SMC2, PPC_SYS_FUNC_UART);
 #endif
+       ppc_sys_device_enable(MPC8xx_MDIO_FEC);
+
+       fmpi = ppc_sys_platform_devices[MPC8xx_MDIO_FEC].dev.platform_data =
+               &mpc8xx_mdio_fec_pdata;
+
+       fmpi->mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1;
+       /* No PHY interrupt line here */
+       fmpi->irq[0xf] = -1;
 
        return 0;
 }
index c1fc4a1..5dfa4e6 100644 (file)
@@ -38,7 +38,10 @@ extern unsigned char __res[];
 static void setup_smc1_ioports(void);
 static void setup_smc2_ioports(void);
 
-static void __init mpc885ads_scc_phy_init(char);
+static struct fs_mii_fec_platform_info mpc8xx_mdio_fec_pdata;
+static void setup_fec1_ioports(void);
+static void setup_fec2_ioports(void);
+static void setup_scc3_ioports(void);
 
 static struct fs_uart_platform_info mpc885_uart_pdata[] = {
        [fsid_smc1_uart] = {
@@ -61,23 +64,8 @@ static struct fs_uart_platform_info mpc885_uart_pdata[] = {
        },
 };
 
-static struct fs_mii_bus_info fec_mii_bus_info = {
-       .method = fsmii_fec,
-       .id = 0,
-};
-
-static struct fs_mii_bus_info scc_mii_bus_info = {
-#ifdef CONFIG_SCC_ENET_8xx_FIXED
-       .method = fsmii_fixed,
-#else
-       .method = fsmii_fec,
-#endif
-
-       .id = 0,
-};
-
-static struct fs_platform_info mpc8xx_fec_pdata[] = {
-       {
+static struct fs_platform_info mpc8xx_enet_pdata[] = {
+       [fsid_fec1] = {
         .rx_ring = 128,
         .tx_ring = 16,
         .rx_copybreak = 240,
@@ -85,11 +73,12 @@ static struct fs_platform_info mpc8xx_fec_pdata[] = {
         .use_napi = 1,
         .napi_weight = 17,
 
-        .phy_addr = 0,
-        .phy_irq = SIU_IRQ7,
+        .init_ioports = setup_fec1_ioports,
 
-        .bus_info = &fec_mii_bus_info,
-        }, {
+          .bus_id = "0:00",
+          .has_phy = 1,
+        },
+       [fsid_fec2] = {
             .rx_ring = 128,
             .tx_ring = 16,
             .rx_copybreak = 240,
@@ -97,35 +86,32 @@ static struct fs_platform_info mpc8xx_fec_pdata[] = {
             .use_napi = 1,
             .napi_weight = 17,
 
-            .phy_addr = 1,
-            .phy_irq = SIU_IRQ7,
-
-            .bus_info = &fec_mii_bus_info,
-            }
-};
+            .init_ioports = setup_fec2_ioports,
 
-static struct fs_platform_info mpc8xx_scc_pdata = {
-       .rx_ring = 64,
-       .tx_ring = 8,
-       .rx_copybreak = 240,
+            .bus_id = "0:01",
+            .has_phy = 1,
+            },
+       [fsid_scc3] = {
+               .rx_ring = 64,
+               .tx_ring = 8,
+               .rx_copybreak = 240,
 
-       .use_napi = 1,
-       .napi_weight = 17,
+               .use_napi = 1,
+               .napi_weight = 17,
 
-       .phy_addr = 2,
-#ifdef CONFIG_MPC8xx_SCC_ENET_FIXED
-       .phy_irq = -1,
+               .init_ioports = setup_scc3_ioports,
+#ifdef CONFIG_FIXED_MII_10_FDX
+               .bus_id = "fixed@100:1",
 #else
-       .phy_irq = SIU_IRQ7,
-#endif
-
-       .bus_info = &scc_mii_bus_info,
+               .bus_id = "0:02",
+ #endif
+       },
 };
 
 void __init board_init(void)
 {
-       volatile cpm8xx_t *cp = cpmp;
-       unsigned int *bcsr_io;
+       cpm8xx_t *cp = cpmp;
+       unsigned int *bcsr_io;
 
 #ifdef CONFIG_FS_ENET
        immap_t *immap = (immap_t *) IMAP_ADDR;
@@ -164,6 +150,14 @@ void __init board_init(void)
        /* use MDC for MII (common) */
        setbits16(&immap->im_ioport.iop_pdpar, 0x0080);
        clrbits16(&immap->im_ioport.iop_pddir, 0x0080);
+       bcsr_io = ioremap(BCSR5, sizeof(unsigned long));
+       clrbits32(bcsr_io,BCSR5_MII1_EN);
+       clrbits32(bcsr_io,BCSR5_MII1_RST);
+#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
+       clrbits32(bcsr_io,BCSR5_MII2_EN);
+       clrbits32(bcsr_io,BCSR5_MII2_RST);
+#endif
+       iounmap(bcsr_io);
 #endif
 }
 
@@ -194,8 +188,8 @@ static void setup_fec2_ioports(void)
        /* configure FEC2 pins */
        setbits32(&immap->im_cpm.cp_pepar, 0x0003fffc);
        setbits32(&immap->im_cpm.cp_pedir, 0x0003fffc);
-       setbits32(&immap->im_cpm.cp_peso, 0x00037800);
        clrbits32(&immap->im_cpm.cp_peso, 0x000087fc);
+       setbits32(&immap->im_cpm.cp_peso, 0x00037800);
        clrbits32(&immap->im_cpm.cp_cptr, 0x00000080);
 }
 
@@ -213,6 +207,8 @@ static void setup_scc3_ioports(void)
 
        /* Enable the PHY.
         */
+       clrbits32(bcsr_io+4, BCSR4_ETH10_RST);
+       udelay(1000);
        setbits32(bcsr_io+4, BCSR4_ETH10_RST);
        /* Configure port A pins for Txd and Rxd.
         */
@@ -254,37 +250,38 @@ static void setup_scc3_ioports(void)
        clrbits32(&immap->im_cpm.cp_pedir, PE_ENET_TENA);
        setbits32(&immap->im_cpm.cp_peso, PE_ENET_TENA);
 
-       setbits32(bcsr_io+1, BCSR1_ETHEN);
+       setbits32(bcsr_io+4, BCSR1_ETHEN);
        iounmap(bcsr_io);
 }
 
+static int mac_count = 0;
+
 static void mpc885ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no)
 {
-       struct fs_platform_info *fpi = pdev->dev.platform_data;
-
-       volatile cpm8xx_t *cp;
+       struct fs_platform_info *fpi;
        bd_t *bd = (bd_t *) __res;
        char *e;
        int i;
 
-       /* Get pointer to Communication Processor */
-       cp = cpmp;
+       if(fs_no > ARRAY_SIZE(mpc8xx_enet_pdata)) {
+               printk(KERN_ERR"No network-suitable #%d device on bus", fs_no);
+               return;
+       }
+
+       fpi = &mpc8xx_enet_pdata[fs_no];
+
        switch (fs_no) {
        case fsid_fec1:
-               fpi = &mpc8xx_fec_pdata[0];
                fpi->init_ioports = &setup_fec1_ioports;
                break;
        case fsid_fec2:
-               fpi = &mpc8xx_fec_pdata[1];
                fpi->init_ioports = &setup_fec2_ioports;
                break;
        case fsid_scc3:
-               fpi = &mpc8xx_scc_pdata;
                fpi->init_ioports = &setup_scc3_ioports;
-               mpc885ads_scc_phy_init(fpi->phy_addr);
                break;
        default:
-               printk(KERN_WARNING"Device %s is not supported!\n", pdev->name);
+               printk(KERN_WARNING "Device %s is not supported!\n", pdev->name);
                return;
        }
 
@@ -295,7 +292,7 @@ static void mpc885ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no)
        for (i = 0; i < 6; i++)
                fpi->macaddr[i] = *e++;
 
-       fpi->macaddr[5 - pdev->id]++;
+       fpi->macaddr[5] += mac_count++;
 
 }
 
@@ -318,58 +315,6 @@ static void __init mpc885ads_fixup_scc_enet_pdata(struct platform_device *pdev,
        mpc885ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1);
 }
 
-/* SCC ethernet controller does not have MII management channel. FEC1 MII
- * channel is used to communicate with the 10Mbit PHY.
- */
-
-#define MII_ECNTRL_PINMUX        0x4
-#define FEC_ECNTRL_PINMUX        0x00000004
-#define FEC_RCNTRL_MII_MODE        0x00000004
-
-/* Make MII read/write commands.
- */
-#define mk_mii_write(REG, VAL, PHY_ADDR)    (0x50020000 | (((REG) & 0x1f) << 18) | \
-                ((VAL) & 0xffff) | ((PHY_ADDR) << 23))
-
-static void mpc885ads_scc_phy_init(char phy_addr)
-{
-       volatile immap_t *immap;
-       volatile fec_t *fecp;
-       bd_t *bd;
-
-       bd = (bd_t *) __res;
-       immap = (immap_t *) IMAP_ADDR;  /* pointer to internal registers */
-       fecp = &(immap->im_cpm.cp_fec);
-
-       /* Enable MII pins of the FEC1
-        */
-       setbits16(&immap->im_ioport.iop_pdpar, 0x0080);
-       clrbits16(&immap->im_ioport.iop_pddir, 0x0080);
-       /* Set MII speed to 2.5 MHz
-        */
-       out_be32(&fecp->fec_mii_speed,
-                ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1);
-
-       /* Enable FEC pin MUX
-        */
-       setbits32(&fecp->fec_ecntrl, MII_ECNTRL_PINMUX);
-       setbits32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE);
-
-       out_be32(&fecp->fec_mii_data,
-                mk_mii_write(MII_BMCR, BMCR_ISOLATE, phy_addr));
-       udelay(100);
-       out_be32(&fecp->fec_mii_data,
-                mk_mii_write(MII_ADVERTISE,
-                             ADVERTISE_10HALF | ADVERTISE_CSMA, phy_addr));
-       udelay(100);
-
-       /* Disable FEC MII settings
-        */
-       clrbits32(&fecp->fec_ecntrl, MII_ECNTRL_PINMUX);
-       clrbits32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE);
-       out_be32(&fecp->fec_mii_speed, 0);
-}
-
 static void setup_smc1_ioports(void)
 {
         immap_t *immap = (immap_t *) IMAP_ADDR;
@@ -462,6 +407,9 @@ static int mpc885ads_platform_notify(struct device *dev)
 
 int __init mpc885ads_init(void)
 {
+       struct fs_mii_fec_platform_info* fmpi;
+       bd_t *bd = (bd_t *) __res;
+
        printk(KERN_NOTICE "mpc885ads: Init\n");
 
        platform_notify = mpc885ads_platform_notify;
@@ -471,8 +419,17 @@ int __init mpc885ads_init(void)
 
        ppc_sys_device_enable(MPC8xx_CPM_FEC1);
 
+       ppc_sys_device_enable(MPC8xx_MDIO_FEC);
+       fmpi = ppc_sys_platform_devices[MPC8xx_MDIO_FEC].dev.platform_data =
+               &mpc8xx_mdio_fec_pdata;
+
+       fmpi->mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1;
+
+       /* No PHY interrupt line here */
+       fmpi->irq[0xf] = SIU_IRQ7;
+
 #ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
-       ppc_sys_device_enable(MPC8xx_CPM_SCC1);
+       ppc_sys_device_enable(MPC8xx_CPM_SCC3);
 
 #endif
 #ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
index 8f14a43..672483d 100644 (file)
 #define F3_RXCLK       13
 #define F3_TXCLK       14
 
-/* Automatically generates register configurations */
-#define PC_CLK(x)      ((uint)(1<<(x-1)))      /* FCC CLK I/O ports */
-
-#define CMXFCR_RF1CS(x)        ((uint)((x-5)<<27))     /* FCC1 Receive Clock Source */
-#define CMXFCR_TF1CS(x)        ((uint)((x-5)<<24))     /* FCC1 Transmit Clock Source */
-#define CMXFCR_RF2CS(x)        ((uint)((x-9)<<19))     /* FCC2 Receive Clock Source */
-#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16))    /* FCC2 Transmit Clock Source */
-#define CMXFCR_RF3CS(x)        ((uint)((x-9)<<11))     /* FCC3 Receive Clock Source */
-#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8))     /* FCC3 Transmit Clock Source */
-
-#define PC_F1RXCLK     PC_CLK(F1_RXCLK)
-#define PC_F1TXCLK     PC_CLK(F1_TXCLK)
-#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK))
-#define CMX1_CLK_MASK  ((uint)0xff000000)
-
-#define PC_F2RXCLK     PC_CLK(F2_RXCLK)
-#define PC_F2TXCLK     PC_CLK(F2_TXCLK)
-#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK))
-#define CMX2_CLK_MASK  ((uint)0x00ff0000)
-
-#define PC_F3RXCLK     PC_CLK(F3_RXCLK)
-#define PC_F3TXCLK     PC_CLK(F3_TXCLK)
-#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK))
-#define CMX3_CLK_MASK  ((uint)0x0000ff00)
-
-/* I/O Pin assignment for FCC1.  I don't yet know the best way to do this,
- * but there is little variation among the choices.
- */
-#define PA1_COL                0x00000001U
-#define PA1_CRS                0x00000002U
-#define PA1_TXER       0x00000004U
-#define PA1_TXEN       0x00000008U
-#define PA1_RXDV       0x00000010U
-#define PA1_RXER       0x00000020U
-#define PA1_TXDAT      0x00003c00U
-#define PA1_RXDAT      0x0003c000U
-#define PA1_PSORA0     (PA1_RXDAT | PA1_TXDAT)
-#define PA1_PSORA1     (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
-               PA1_RXDV | PA1_RXER)
-#define PA1_DIRA0      (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
-#define PA1_DIRA1      (PA1_TXDAT | PA1_TXEN | PA1_TXER)
-
-
-/* I/O Pin assignment for FCC2.  I don't yet know the best way to do this,
- * but there is little variation among the choices.
- */
-#define PB2_TXER       0x00000001U
-#define PB2_RXDV       0x00000002U
-#define PB2_TXEN       0x00000004U
-#define PB2_RXER       0x00000008U
-#define PB2_COL                0x00000010U
-#define PB2_CRS                0x00000020U
-#define PB2_TXDAT      0x000003c0U
-#define PB2_RXDAT      0x00003c00U
-#define PB2_PSORB0     (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
-               PB2_RXER | PB2_RXDV | PB2_TXER)
-#define PB2_PSORB1     (PB2_TXEN)
-#define PB2_DIRB0      (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
-#define PB2_DIRB1      (PB2_TXDAT | PB2_TXEN | PB2_TXER)
-
-
-/* I/O Pin assignment for FCC3.  I don't yet know the best way to do this,
- * but there is little variation among the choices.
- */
-#define PB3_RXDV       0x00004000U
-#define PB3_RXER       0x00008000U
-#define PB3_TXER       0x00010000U
-#define PB3_TXEN       0x00020000U
-#define PB3_COL                0x00040000U
-#define PB3_CRS                0x00080000U
-#define PB3_TXDAT      0x0f000000U
-#define PB3_RXDAT      0x00f00000U
-#define PB3_PSORB0     (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
-               PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
-#define PB3_PSORB1     0
-#define PB3_DIRB0      (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
-#define PB3_DIRB1      (PB3_TXDAT | PB3_TXEN | PB3_TXER)
-
-#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128))
-#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
-#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1)
-
 #endif
index 7735336..325136e 100644 (file)
 #include <linux/device.h>
 #include <linux/serial_8250.h>
 #include <linux/fsl_devices.h>
+#include <linux/fs_enet_pd.h>
 #include <asm/mpc85xx.h>
 #include <asm/irq.h>
 #include <asm/ppc_sys.h>
+#include <asm/cpm2.h>
 
 /* We use offsets for IORESOURCE_MEM since we do not know at compile time
  * what CCSRBAR is, will get fixed up by mach_mpc85xx_fixup
@@ -82,6 +84,60 @@ static struct fsl_i2c_platform_data mpc85xx_fsl_i2c2_pdata = {
        .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
 };
 
+static struct fs_platform_info mpc85xx_fcc1_pdata = {
+       .fs_no          = fsid_fcc1,
+       .cp_page        = CPM_CR_FCC1_PAGE,
+       .cp_block       = CPM_CR_FCC1_SBLOCK,
+
+       .rx_ring        = 32,
+       .tx_ring        = 32,
+       .rx_copybreak   = 240,
+       .use_napi       = 0,
+       .napi_weight    = 17,
+
+       .clk_mask       = CMX1_CLK_MASK,
+       .clk_route      = CMX1_CLK_ROUTE,
+       .clk_trx        = (PC_F1RXCLK | PC_F1TXCLK),
+
+       .mem_offset     = FCC1_MEM_OFFSET,
+};
+
+static struct fs_platform_info mpc85xx_fcc2_pdata = {
+       .fs_no          = fsid_fcc2,
+       .cp_page        = CPM_CR_FCC2_PAGE,
+       .cp_block       = CPM_CR_FCC2_SBLOCK,
+
+       .rx_ring        = 32,
+       .tx_ring        = 32,
+       .rx_copybreak   = 240,
+       .use_napi       = 0,
+       .napi_weight    = 17,
+
+       .clk_mask       = CMX2_CLK_MASK,
+       .clk_route      = CMX2_CLK_ROUTE,
+       .clk_trx        = (PC_F2RXCLK | PC_F2TXCLK),
+
+       .mem_offset     = FCC2_MEM_OFFSET,
+};
+
+static struct fs_platform_info mpc85xx_fcc3_pdata = {
+       .fs_no          = fsid_fcc3,
+       .cp_page        = CPM_CR_FCC3_PAGE,
+       .cp_block       = CPM_CR_FCC3_SBLOCK,
+
+       .rx_ring        = 32,
+       .tx_ring        = 32,
+       .rx_copybreak   = 240,
+       .use_napi       = 0,
+       .napi_weight    = 17,
+
+       .clk_mask       = CMX3_CLK_MASK,
+       .clk_route      = CMX3_CLK_ROUTE,
+       .clk_trx        = (PC_F3RXCLK | PC_F3TXCLK),
+
+       .mem_offset     = FCC3_MEM_OFFSET,
+};
+
 static struct plat_serial8250_port serial_platform_data[] = {
        [0] = {
                .mapbase        = 0x4500,
@@ -318,18 +374,27 @@ struct platform_device ppc_sys_platform_devices[] = {
        [MPC85xx_CPM_FCC1] = {
                .name = "fsl-cpm-fcc",
                .id     = 1,
-               .num_resources   = 3,
+               .num_resources   = 4,
+               .dev.platform_data = &mpc85xx_fcc1_pdata,
                .resource = (struct resource[]) {
                        {
+                               .name   = "fcc_regs",
                                .start  = 0x91300,
                                .end    = 0x9131F,
                                .flags  = IORESOURCE_MEM,
                        },
                        {
+                               .name   = "fcc_regs_c",
                                .start  = 0x91380,
                                .end    = 0x9139F,
                                .flags  = IORESOURCE_MEM,
                        },
+                       {
+                               .name   = "fcc_pram",
+                               .start  = 0x88400,
+                               .end    = 0x884ff,
+                               .flags  = IORESOURCE_MEM,
+                       },
                        {
                                .start  = SIU_INT_FCC1,
                                .end    = SIU_INT_FCC1,
@@ -340,18 +405,27 @@ struct platform_device ppc_sys_platform_devices[] = {
        [MPC85xx_CPM_FCC2] = {
                .name = "fsl-cpm-fcc",
                .id     = 2,
-               .num_resources   = 3,
+               .num_resources   = 4,
+               .dev.platform_data = &mpc85xx_fcc2_pdata,
                .resource = (struct resource[]) {
                        {
+                               .name   = "fcc_regs",
                                .start  = 0x91320,
                                .end    = 0x9133F,
                                .flags  = IORESOURCE_MEM,
                        },
                        {
+                               .name   = "fcc_regs_c",
                                .start  = 0x913A0,
                                .end    = 0x913CF,
                                .flags  = IORESOURCE_MEM,
                        },
+                       {
+                               .name   = "fcc_pram",
+                               .start  = 0x88500,
+                               .end    = 0x885ff,
+                               .flags  = IORESOURCE_MEM,
+                       },
                        {
                                .start  = SIU_INT_FCC2,
                                .end    = SIU_INT_FCC2,
@@ -362,18 +436,27 @@ struct platform_device ppc_sys_platform_devices[] = {
        [MPC85xx_CPM_FCC3] = {
                .name = "fsl-cpm-fcc",
                .id     = 3,
-               .num_resources   = 3,
+               .num_resources   = 4,
+               .dev.platform_data = &mpc85xx_fcc3_pdata,
                .resource = (struct resource[]) {
                        {
+                               .name   = "fcc_regs",
                                .start  = 0x91340,
                                .end    = 0x9135F,
                                .flags  = IORESOURCE_MEM,
                        },
                        {
+                               .name   = "fcc_regs_c",
                                .start  = 0x913D0,
                                .end    = 0x913FF,
                                .flags  = IORESOURCE_MEM,
                        },
+                       {
+                               .name   = "fcc_pram",
+                               .start  = 0x88600,
+                               .end    = 0x886ff,
+                               .flags  = IORESOURCE_MEM,
+                       },
                        {
                                .start  = SIU_INT_FCC3,
                                .end    = SIU_INT_FCC3,
index 6f53638..cf5ab47 100644 (file)
@@ -218,6 +218,14 @@ struct platform_device ppc_sys_platform_devices[] = {
                        },
                },
        },
+
+        [MPC8xx_MDIO_FEC] = {
+                .name = "fsl-cpm-fec-mdio",
+                .id = 0,
+                .num_resources = 0,
+
+        },
+
 };
 
 static int __init mach_mpc8xx_fixup(struct platform_device *pdev)
index eee2132..18ba1d7 100644 (file)
@@ -22,7 +22,7 @@ struct ppc_sys_spec ppc_sys_specs[] = {
                .ppc_sys_name   = "MPC86X",
                .mask           = 0xFFFFFFFF,
                .value          = 0x00000000,
-               .num_devices    = 7,
+               .num_devices    = 8,
                .device_list    = (enum ppc_sys_devices[])
                {
                        MPC8xx_CPM_FEC1,
@@ -32,13 +32,14 @@ struct ppc_sys_spec ppc_sys_specs[] = {
                        MPC8xx_CPM_SCC4,
                        MPC8xx_CPM_SMC1,
                        MPC8xx_CPM_SMC2,
+                       MPC8xx_MDIO_FEC,
                },
        },
        {
                .ppc_sys_name   = "MPC885",
                .mask           = 0xFFFFFFFF,
                .value          = 0x00000000,
-               .num_devices    = 8,
+               .num_devices    = 9,
                .device_list    = (enum ppc_sys_devices[])
                {
                        MPC8xx_CPM_FEC1,
@@ -49,6 +50,7 @@ struct ppc_sys_spec ppc_sys_specs[] = {
                        MPC8xx_CPM_SCC4,
                        MPC8xx_CPM_SMC1,
                        MPC8xx_CPM_SMC2,
+                       MPC8xx_MDIO_FEC,
                },
        },
        {       /* default match */
index 8692d00..fefbc21 100644 (file)
@@ -369,6 +369,11 @@ struct platform_device ppc_sys_platform_devices[] = {
                        },
                },
        },
+       [MPC82xx_MDIO_BB] = {
+               .name = "fsl-bb-mdio",
+               .id = 0,
+               .num_resources = 0,
+       },
 };
 
 static int __init mach_mpc82xx_fixup(struct platform_device *pdev)
index fee8948..f52600c 100644 (file)
@@ -139,13 +139,14 @@ struct ppc_sys_spec ppc_sys_specs[] = {
                .ppc_sys_name   = "8272",
                .mask           = 0x0000ff00,
                .value          = 0x00000c00,
-               .num_devices    = 12,
+               .num_devices    = 13,
                .device_list = (enum ppc_sys_devices[])
                {
                        MPC82xx_CPM_FCC1, MPC82xx_CPM_FCC2, MPC82xx_CPM_SCC1,
                        MPC82xx_CPM_SCC2, MPC82xx_CPM_SCC3, MPC82xx_CPM_SCC4,
                        MPC82xx_CPM_SMC1, MPC82xx_CPM_SMC2, MPC82xx_CPM_SPI,
                        MPC82xx_CPM_I2C, MPC82xx_CPM_USB, MPC82xx_SEC1,
+                       MPC82xx_MDIO_BB,
                },
        },
        /* below is a list of the 8280 family of processors */
index 4532b17..aedfddf 100644 (file)
@@ -1003,7 +1003,8 @@ static int corkscrew_start_xmit(struct sk_buff *skb,
                /* Calculate the next Tx descriptor entry. */
                int entry = vp->cur_tx % TX_RING_SIZE;
                struct boom_tx_desc *prev_entry;
-               unsigned long flags, i;
+               unsigned long flags;
+               int i;
 
                if (vp->tx_full)        /* No room to transmit with */
                        return 1;
index 7e2ca95..257d3bc 100644 (file)
@@ -899,7 +899,7 @@ memory_squeeze:
 }
 
 
-static inline void i596_cleanup_cmd(struct net_device *dev, struct i596_private *lp)
+static void i596_cleanup_cmd(struct net_device *dev, struct i596_private *lp)
 {
        struct i596_cmd *ptr;
 
@@ -932,7 +932,8 @@ static inline void i596_cleanup_cmd(struct net_device *dev, struct i596_private
        lp->scb.cmd = I596_NULL;
 }
 
-static inline void i596_reset(struct net_device *dev, struct i596_private *lp, int ioaddr)
+static void i596_reset(struct net_device *dev, struct i596_private *lp,
+                       int ioaddr)
 {
        unsigned long flags;
 
@@ -1578,7 +1579,7 @@ static int debug = -1;
 module_param(debug, int, 0);
 MODULE_PARM_DESC(debug, "i82596 debug mask");
 
-int init_module(void)
+int __init init_module(void)
 {
        if (debug >= 0)
                i596_debug = debug;
@@ -1588,7 +1589,7 @@ int init_module(void)
        return 0;
 }
 
-void cleanup_module(void)
+void __exit cleanup_module(void)
 {
        unregister_netdev(dev_82596);
 #ifdef __mc68000__
index 3918990..30b3671 100644 (file)
@@ -1724,6 +1724,20 @@ config VIA_RHINE_MMIO
 
          If unsure, say Y.
 
+config VIA_RHINE_NAPI
+       bool "Use Rx Polling (NAPI)"
+       depends on VIA_RHINE
+       help
+         NAPI is a new driver API designed to reduce CPU and interrupt load
+         when the driver is receiving lots of packets from the card.
+
+         If your estimated Rx load is 10kpps or more, or if the card will be
+         deployed on potentially unfriendly networks (e.g. in a firewall),
+         then say Y here.
+
+         See <file:Documentation/networking/NAPI_HOWTO.txt> for more
+         information.
+
 config LAN_SAA9730
        bool "Philips SAA9730 Ethernet support (EXPERIMENTAL)"
        depends on NET_PCI && EXPERIMENTAL && MIPS
@@ -2219,6 +2233,33 @@ config GFAR_NAPI
        bool "NAPI Support"
        depends on GIANFAR
 
+config UCC_GETH
+       tristate "Freescale QE UCC GETH"
+       depends on QUICC_ENGINE && UCC_FAST
+       help
+         This driver supports the Gigabit Ethernet mode of QE UCC.
+         QE can be found on MPC836x CPUs.
+
+config UGETH_NAPI
+       bool "NAPI Support"
+       depends on UCC_GETH
+
+config UGETH_MAGIC_PACKET
+       bool "Magic Packet detection support"
+       depends on UCC_GETH
+
+config UGETH_FILTERING
+       bool "Mac address filtering support"
+       depends on UCC_GETH
+
+config UGETH_TX_ON_DEMOND
+       bool "Transmit on Demond support"
+       depends on UCC_GETH
+
+config UGETH_HAS_GIGA
+       bool
+       depends on UCC_GETH && MPC836x
+
 config MV643XX_ETH
        tristate "MV-643XX Ethernet support"
        depends on MOMENCO_OCELOT_C || MOMENCO_JAGUAR_ATX || MV64360 || MOMENCO_OCELOT_3 || PPC_MULTIPLATFORM
index c91e951..8427bf9 100644 (file)
@@ -18,6 +18,9 @@ gianfar_driver-objs := gianfar.o \
                gianfar_mii.o \
                gianfar_sysfs.o
 
+obj-$(CONFIG_UCC_GETH) += ucc_geth_driver.o
+ucc_geth_driver-objs := ucc_geth.o ucc_geth_phy.o
+
 #
 # link order important here
 #
index 7952dc6..0fbbcb7 100644 (file)
@@ -370,8 +370,7 @@ MODULE_PARM_DESC(mem, "Memory base address(es)");
 MODULE_DESCRIPTION("Ansel AC3200 EISA ethernet driver");
 MODULE_LICENSE("GPL");
 
-int
-init_module(void)
+int __init init_module(void)
 {
        struct net_device *dev;
        int this_dev, found = 0;
index 1d01ac0..ae7f828 100644 (file)
@@ -1030,7 +1030,7 @@ module_param(io, int, 0);
 module_param(irq, int, 0);
 module_param(board_type, int, 0);
 
-int init_module(void)
+int __init init_module(void)
 {
        if (io == 0)
                printk(KERN_WARNING "%s: You shouldn't autoprobe with insmod\n",
index 5d7929c..4ca061c 100644 (file)
@@ -901,7 +901,7 @@ MODULE_PARM_DESC(io, "AT1700/FMV18X I/O base address");
 MODULE_PARM_DESC(irq, "AT1700/FMV18X IRQ number");
 MODULE_PARM_DESC(net_debug, "AT1700/FMV18X debug level (0-6)");
 
-int init_module(void)
+int __init init_module(void)
 {
        if (io == 0)
                printk("at1700: You should not use auto-probing with insmod!\n");
index 47eecce..2dcca79 100644 (file)
@@ -1905,8 +1905,7 @@ MODULE_LICENSE("GPL");
 
 */
 
-int
-init_module(void)
+int __init init_module(void)
 {
        struct net_device *dev = alloc_etherdev(sizeof(struct net_local));
        struct net_local *lp;
index 1b758b7..3d76fa1 100644 (file)
@@ -339,6 +339,17 @@ static void dm9000_timeout(struct net_device *dev)
        spin_unlock_irqrestore(&db->lock,flags);
 }
 
+#ifdef CONFIG_NET_POLL_CONTROLLER
+/*
+ *Used by netconsole
+ */
+static void dm9000_poll_controller(struct net_device *dev)
+{
+       disable_irq(dev->irq);
+       dm9000_interrupt(dev->irq,dev,NULL);
+       enable_irq(dev->irq);
+}
+#endif
 
 /* dm9000_release_board
  *
@@ -538,6 +549,9 @@ dm9000_probe(struct platform_device *pdev)
        ndev->stop               = &dm9000_stop;
        ndev->get_stats          = &dm9000_get_stats;
        ndev->set_multicast_list = &dm9000_hash_table;
+#ifdef CONFIG_NET_POLL_CONTROLLER
+       ndev->poll_controller    = &dm9000_poll_controller;
+#endif
 
 #ifdef DM9000_PROGRAM_EEPROM
        program_eeprom(db);
index 583518a..b3b9191 100644 (file)
@@ -105,6 +105,33 @@ static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw,
                                                uint16_t duplex);
 static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
 
+static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw,
+                                          uint32_t segment);
+static int32_t e1000_get_software_flag(struct e1000_hw *hw);
+static int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
+static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw);
+static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
+static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset,
+                                     uint16_t words, uint16_t *data);
+static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index,
+                                   uint8_t* data);
+static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index,
+                                   uint16_t *data);
+static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr,
+                                  uint16_t *data);
+static void e1000_release_software_flag(struct e1000_hw *hw);
+static void e1000_release_software_semaphore(struct e1000_hw *hw);
+static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw,
+                                        uint32_t no_snoop);
+static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw,
+                                           uint32_t index, uint8_t byte);
+static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset,
+                                      uint16_t words, uint16_t *data);
+static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index,
+                                    uint8_t data);
+static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr,
+                                   uint16_t data);
+
 /* IGP cable length table */
 static const
 uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
@@ -3233,7 +3260,7 @@ e1000_shift_in_mdi_bits(struct e1000_hw *hw)
     return data;
 }
 
-int32_t
+static int32_t
 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
 {
     uint32_t swfw_sync = 0;
@@ -3277,7 +3304,7 @@ e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
     return E1000_SUCCESS;
 }
 
-void
+static void
 e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
 {
     uint32_t swfw_sync;
@@ -3575,7 +3602,7 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw,
     return E1000_SUCCESS;
 }
 
-int32_t
+static int32_t
 e1000_read_kmrn_reg(struct e1000_hw *hw,
                     uint32_t reg_addr,
                     uint16_t *data)
@@ -3608,7 +3635,7 @@ e1000_read_kmrn_reg(struct e1000_hw *hw,
     return E1000_SUCCESS;
 }
 
-int32_t
+static int32_t
 e1000_write_kmrn_reg(struct e1000_hw *hw,
                      uint32_t reg_addr,
                      uint16_t data)
@@ -3839,7 +3866,7 @@ e1000_phy_powerdown_workaround(struct e1000_hw *hw)
 *
 * hw - struct containing variables accessed by shared code
 ******************************************************************************/
-int32_t
+static int32_t
 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
 {
     int32_t ret_val;
@@ -4086,7 +4113,7 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
 * hw - Struct containing variables accessed by shared code
 * phy_info - PHY information structure
 ******************************************************************************/
-int32_t
+static int32_t
 e1000_phy_ife_get_info(struct e1000_hw *hw,
                        struct e1000_phy_info *phy_info)
 {
@@ -5643,6 +5670,7 @@ e1000_init_rx_addrs(struct e1000_hw *hw)
  * for the first 15 multicast addresses, and hashes the rest into the
  * multicast table.
  *****************************************************************************/
+#if 0
 void
 e1000_mc_addr_list_update(struct e1000_hw *hw,
                           uint8_t *mc_addr_list,
@@ -5719,6 +5747,7 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
     }
     DEBUGOUT("MC Update Complete\n");
 }
+#endif  /*  0  */
 
 /******************************************************************************
  * Hashes an address to determine its location in the multicast table
@@ -6587,6 +6616,7 @@ e1000_get_bus_info(struct e1000_hw *hw)
  * hw - Struct containing variables accessed by shared code
  * offset - offset to read from
  *****************************************************************************/
+#if 0
 uint32_t
 e1000_read_reg_io(struct e1000_hw *hw,
                   uint32_t offset)
@@ -6597,6 +6627,7 @@ e1000_read_reg_io(struct e1000_hw *hw,
     e1000_io_write(hw, io_addr, offset);
     return e1000_io_read(hw, io_data);
 }
+#endif  /*  0  */
 
 /******************************************************************************
  * Writes a value to one of the devices registers using port I/O (as opposed to
@@ -7909,6 +7940,7 @@ e1000_set_pci_express_master_disable(struct e1000_hw *hw)
  * returns: - none.
  *
  ***************************************************************************/
+#if 0
 void
 e1000_enable_pciex_master(struct e1000_hw *hw)
 {
@@ -7923,6 +7955,7 @@ e1000_enable_pciex_master(struct e1000_hw *hw)
     ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE;
     E1000_WRITE_REG(hw, CTRL, ctrl);
 }
+#endif  /*  0  */
 
 /*******************************************************************************
  *
@@ -8148,7 +8181,7 @@ e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
  *            E1000_SUCCESS at any other case.
  *
  ***************************************************************************/
-int32_t
+static int32_t
 e1000_get_software_semaphore(struct e1000_hw *hw)
 {
     int32_t timeout = hw->eeprom.word_size + 1;
@@ -8183,7 +8216,7 @@ e1000_get_software_semaphore(struct e1000_hw *hw)
  * hw: Struct containing variables accessed by shared code
  *
  ***************************************************************************/
-void
+static void
 e1000_release_software_semaphore(struct e1000_hw *hw)
 {
     uint32_t swsm;
@@ -8265,7 +8298,7 @@ e1000_arc_subsystem_valid(struct e1000_hw *hw)
  * returns: E1000_SUCCESS
  *
  *****************************************************************************/
-int32_t
+static int32_t
 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop)
 {
     uint32_t gcr_reg = 0;
@@ -8306,7 +8339,7 @@ e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop)
  * hw: Struct containing variables accessed by shared code
  *
  ***************************************************************************/
-int32_t
+static int32_t
 e1000_get_software_flag(struct e1000_hw *hw)
 {
     int32_t timeout = PHY_CFG_TIMEOUT;
@@ -8345,7 +8378,7 @@ e1000_get_software_flag(struct e1000_hw *hw)
  * hw: Struct containing variables accessed by shared code
  *
  ***************************************************************************/
-void
+static void
 e1000_release_software_flag(struct e1000_hw *hw)
 {
     uint32_t extcnf_ctrl;
@@ -8369,6 +8402,7 @@ e1000_release_software_flag(struct e1000_hw *hw)
  * hw: Struct containing variables accessed by shared code
  *
  ***************************************************************************/
+#if 0
 int32_t
 e1000_ife_disable_dynamic_power_down(struct e1000_hw *hw)
 {
@@ -8388,6 +8422,7 @@ e1000_ife_disable_dynamic_power_down(struct e1000_hw *hw)
 
     return ret_val;
 }
+#endif  /*  0  */
 
 /***************************************************************************
  *
@@ -8397,6 +8432,7 @@ e1000_ife_disable_dynamic_power_down(struct e1000_hw *hw)
  * hw: Struct containing variables accessed by shared code
  *
  ***************************************************************************/
+#if 0
 int32_t
 e1000_ife_enable_dynamic_power_down(struct e1000_hw *hw)
 {
@@ -8416,6 +8452,7 @@ e1000_ife_enable_dynamic_power_down(struct e1000_hw *hw)
 
     return ret_val;
 }
+#endif  /*  0  */
 
 /******************************************************************************
  * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
@@ -8426,7 +8463,7 @@ e1000_ife_enable_dynamic_power_down(struct e1000_hw *hw)
  * data - word read from the EEPROM
  * words - number of words to read
  *****************************************************************************/
-int32_t
+static int32_t
 e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
                        uint16_t *data)
 {
@@ -8482,7 +8519,7 @@ e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
  * words - number of words to write
  * data - words to write to the EEPROM
  *****************************************************************************/
-int32_t
+static int32_t
 e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
                         uint16_t *data)
 {
@@ -8529,7 +8566,7 @@ e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
  *
  * hw - The pointer to the hw structure
  ****************************************************************************/
-int32_t
+static int32_t
 e1000_ich8_cycle_init(struct e1000_hw *hw)
 {
     union ich8_hws_flash_status hsfsts;
@@ -8596,7 +8633,7 @@ e1000_ich8_cycle_init(struct e1000_hw *hw)
  *
  * hw - The pointer to the hw structure
  ****************************************************************************/
-int32_t
+static int32_t
 e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout)
 {
     union ich8_hws_flash_ctrl hsflctl;
@@ -8631,7 +8668,7 @@ e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout)
  * size - Size of data to read, 1=byte 2=word
  * data - Pointer to the word to store the value read.
  *****************************************************************************/
-int32_t
+static int32_t
 e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
                      uint32_t size, uint16_t* data)
 {
@@ -8710,7 +8747,7 @@ e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
  * size - Size of data to read, 1=byte 2=word
  * data - The byte(s) to write to the NVM.
  *****************************************************************************/
-int32_t
+static int32_t
 e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
                       uint16_t data)
 {
@@ -8785,7 +8822,7 @@ e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
  * index - The index of the byte to read.
  * data - Pointer to a byte to store the value read.
  *****************************************************************************/
-int32_t
+static int32_t
 e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data)
 {
     int32_t status = E1000_SUCCESS;
@@ -8808,7 +8845,7 @@ e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data)
  * index - The index of the byte to write.
  * byte - The byte to write to the NVM.
  *****************************************************************************/
-int32_t
+static int32_t
 e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte)
 {
     int32_t error = E1000_SUCCESS;
@@ -8839,7 +8876,7 @@ e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte)
  * index - The index of the byte to read.
  * data - The byte to write to the NVM.
  *****************************************************************************/
-int32_t
+static int32_t
 e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data)
 {
     int32_t status = E1000_SUCCESS;
@@ -8857,7 +8894,7 @@ e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data)
  * index - The starting byte index of the word to read.
  * data - Pointer to a word to store the value read.
  *****************************************************************************/
-int32_t
+static int32_t
 e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data)
 {
     int32_t status = E1000_SUCCESS;
@@ -8872,6 +8909,7 @@ e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data)
  * index - The starting byte index of the word to read.
  * data - The word to write to the NVM.
  *****************************************************************************/
+#if 0
 int32_t
 e1000_write_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t data)
 {
@@ -8879,6 +8917,7 @@ e1000_write_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t data)
     status = e1000_write_ich8_data(hw, index, 2, data);
     return status;
 }
+#endif  /*  0  */
 
 /******************************************************************************
  * Erases the bank specified. Each bank is a 4k block. Segments are 0 based.
@@ -8887,7 +8926,7 @@ e1000_write_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t data)
  * hw - pointer to e1000_hw structure
  * segment - 0 for first segment, 1 for second segment, etc.
  *****************************************************************************/
-int32_t
+static int32_t
 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t segment)
 {
     union ich8_hws_flash_status hsfsts;
@@ -8984,6 +9023,7 @@ e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t segment)
  * hw: Struct containing variables accessed by shared code
  *
  *****************************************************************************/
+#if 0
 int32_t
 e1000_duplex_reversal(struct e1000_hw *hw)
 {
@@ -9012,8 +9052,9 @@ e1000_duplex_reversal(struct e1000_hw *hw)
 
     return ret_val;
 }
+#endif  /*  0  */
 
-int32_t
+static int32_t
 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
                                       uint32_t cnf_base_addr, uint32_t cnf_size)
 {
@@ -9047,7 +9088,7 @@ e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
 }
 
 
-int32_t
+static int32_t
 e1000_init_lcd_from_nvm(struct e1000_hw *hw)
 {
     uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop;
index f9341e3..375b955 100644 (file)
@@ -323,13 +323,8 @@ int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t dat
 int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
 int32_t e1000_phy_reset(struct e1000_hw *hw);
 void e1000_phy_powerdown_workaround(struct e1000_hw *hw);
-int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
-int32_t e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size);
-int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw);
 int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
 int32_t e1000_validate_mdi_setting(struct e1000_hw *hw);
-int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data);
-int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
 
 /* EEPROM Functions */
 int32_t e1000_init_eeprom_params(struct e1000_hw *hw);
@@ -400,13 +395,8 @@ int32_t e1000_update_eeprom_checksum(struct e1000_hw *hw);
 int32_t e1000_write_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
 int32_t e1000_read_part_num(struct e1000_hw *hw, uint32_t * part_num);
 int32_t e1000_read_mac_addr(struct e1000_hw * hw);
-int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
-void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
-void e1000_release_software_flag(struct e1000_hw *hw);
-int32_t e1000_get_software_flag(struct e1000_hw *hw);
 
 /* Filters (multicast, vlan, receive) */
-void e1000_mc_addr_list_update(struct e1000_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count);
 uint32_t e1000_hash_mc_addr(struct e1000_hw *hw, uint8_t * mc_addr);
 void e1000_mta_set(struct e1000_hw *hw, uint32_t hash_value);
 void e1000_rar_set(struct e1000_hw *hw, uint8_t * mc_addr, uint32_t rar_index);
@@ -431,31 +421,9 @@ void e1000_pci_clear_mwi(struct e1000_hw *hw);
 void e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
 void e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
 /* Port I/O is only supported on 82544 and newer */
-uint32_t e1000_io_read(struct e1000_hw *hw, unsigned long port);
-uint32_t e1000_read_reg_io(struct e1000_hw *hw, uint32_t offset);
 void e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value);
-void e1000_enable_pciex_master(struct e1000_hw *hw);
 int32_t e1000_disable_pciex_master(struct e1000_hw *hw);
-int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
-void e1000_release_software_semaphore(struct e1000_hw *hw);
 int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
-int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop);
-
-int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index,
-                             uint8_t *data);
-int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index,
-                                     uint8_t byte);
-int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index,
-                              uint8_t byte);
-int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index,
-                             uint16_t *data);
-int32_t e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
-                             uint32_t size, uint16_t *data);
-int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset,
-                               uint16_t words, uint16_t *data);
-int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset,
-                                uint16_t words, uint16_t *data);
-int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t segment);
 
 
 #define E1000_READ_REG_IO(a, reg) \
index 627f224..726f43d 100644 (file)
@@ -4386,11 +4386,13 @@ e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
        pci_write_config_word(adapter->pdev, reg, *value);
 }
 
+#if 0
 uint32_t
 e1000_io_read(struct e1000_hw *hw, unsigned long port)
 {
        return inl(port);
 }
+#endif  /*  0  */
 
 void
 e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value)
index e5c5cd2..e4e733a 100644 (file)
@@ -425,8 +425,8 @@ MODULE_LICENSE("GPL");
 
 /* This is set up so that only a single autoprobe takes place per call.
 ISA device autoprobes on a running machine are not recommended. */
-int
-init_module(void)
+
+int __init init_module(void)
 {
        struct net_device *dev;
        int this_dev, found = 0;
index 20d3143..8dc61d6 100644 (file)
@@ -1807,8 +1807,7 @@ MODULE_PARM_DESC(irq, "EtherExpress Pro/10 IRQ number(s)");
 MODULE_PARM_DESC(mem, "EtherExpress Pro/10 Rx buffer size(es) in kB (3-29)");
 MODULE_PARM_DESC(autodetect, "EtherExpress Pro/10 force board(s) detection (0-1)");
 
-int
-init_module(void)
+int __init init_module(void)
 {
        struct net_device *dev;
        int i;
index 33291bc..0701c1d 100644 (file)
@@ -1698,7 +1698,7 @@ MODULE_LICENSE("GPL");
  * are specified, we verify and then use them.  If no parameters are given, we
  * autoprobe for one card only.
  */
-int init_module(void)
+int __init init_module(void)
 {
        struct net_device *dev;
        int this_dev, found = 0;
index 6b0ab1e..fd7b32a 100644 (file)
@@ -421,8 +421,7 @@ MODULE_PARM_DESC(mem, "memory base address(es)");
 MODULE_DESCRIPTION("Racal-Interlan ES3210 EISA ethernet driver");
 MODULE_LICENSE("GPL");
 
-int
-init_module(void)
+int __init init_module(void)
 {
        struct net_device *dev;
        int this_dev, found = 0;
index 4bf76f8..ca42efa 100644 (file)
@@ -1434,7 +1434,7 @@ MODULE_PARM_DESC(mediatype, "eth16i media type of interface(s) (bnc,tp,dix,auto,
 module_param(debug, int, 0);
 MODULE_PARM_DESC(debug, "eth16i debug level (0-6)");
 
-int init_module(void)
+int __init init_module(void)
 {
        int this_dev, found = 0;
        struct net_device *dev;
index 97d34fe..567e274 100644 (file)
@@ -92,7 +92,7 @@ static int full_duplex[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
 #include <asm/uaccess.h>
 
 /* These identify the driver base version and may not be removed. */
-static char version[] __devinitdata =
+static char version[] =
 KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE "\n";
 
 
index d6dd3f2..02d4dc1 100644 (file)
@@ -4,7 +4,7 @@
 
 obj-$(CONFIG_FS_ENET) += fs_enet.o
 
-obj-$(CONFIG_8xx) += mac-fec.o mac-scc.o
-obj-$(CONFIG_8260) += mac-fcc.o
+obj-$(CONFIG_8xx) += mac-fec.o mac-scc.o mii-fec.o
+obj-$(CONFIG_CPM2) += mac-fcc.o mii-bitbang.o
 
-fs_enet-objs := fs_enet-main.o fs_enet-mii.o mii-bitbang.o mii-fixed.o
+fs_enet-objs := fs_enet-main.o
diff --git a/drivers/net/fs_enet/fec.h b/drivers/net/fs_enet/fec.h
new file mode 100644 (file)
index 0000000..e980527
--- /dev/null
@@ -0,0 +1,42 @@
+#ifndef FS_ENET_FEC_H
+#define FS_ENET_FEC_H
+
+/* CRC polynomium used by the FEC for the multicast group filtering */
+#define FEC_CRC_POLY   0x04C11DB7
+
+#define FEC_MAX_MULTICAST_ADDRS        64
+
+/* Interrupt events/masks.
+*/
+#define FEC_ENET_HBERR 0x80000000U     /* Heartbeat error          */
+#define FEC_ENET_BABR  0x40000000U     /* Babbling receiver        */
+#define FEC_ENET_BABT  0x20000000U     /* Babbling transmitter     */
+#define FEC_ENET_GRA   0x10000000U     /* Graceful stop complete   */
+#define FEC_ENET_TXF   0x08000000U     /* Full frame transmitted   */
+#define FEC_ENET_TXB   0x04000000U     /* A buffer was transmitted */
+#define FEC_ENET_RXF   0x02000000U     /* Full frame received      */
+#define FEC_ENET_RXB   0x01000000U     /* A buffer was received    */
+#define FEC_ENET_MII   0x00800000U     /* MII interrupt            */
+#define FEC_ENET_EBERR 0x00400000U     /* SDMA bus error           */
+
+#define FEC_ECNTRL_PINMUX      0x00000004
+#define FEC_ECNTRL_ETHER_EN    0x00000002
+#define FEC_ECNTRL_RESET       0x00000001
+
+#define FEC_RCNTRL_BC_REJ      0x00000010
+#define FEC_RCNTRL_PROM                0x00000008
+#define FEC_RCNTRL_MII_MODE    0x00000004
+#define FEC_RCNTRL_DRT         0x00000002
+#define FEC_RCNTRL_LOOP                0x00000001
+
+#define FEC_TCNTRL_FDEN                0x00000004
+#define FEC_TCNTRL_HBC         0x00000002
+#define FEC_TCNTRL_GTS         0x00000001
+
+
+
+/*
+ * Delay to wait for FEC reset command to complete (in us)
+ */
+#define FEC_RESET_DELAY                50
+#endif
index f6abff5..df62506 100644 (file)
@@ -37,6 +37,7 @@
 #include <linux/bitops.h>
 #include <linux/fs.h>
 #include <linux/platform_device.h>
+#include <linux/phy.h>
 
 #include <linux/vmalloc.h>
 #include <asm/pgtable.h>
@@ -682,35 +683,6 @@ static void fs_free_irq(struct net_device *dev, int irq)
        (*fep->ops->post_free_irq)(dev, irq);
 }
 
-/**********************************************************************************/
-
-/* This interrupt occurs when the PHY detects a link change. */
-static irqreturn_t
-fs_mii_link_interrupt(int irq, void *dev_id, struct pt_regs *regs)
-{
-       struct net_device *dev = dev_id;
-       struct fs_enet_private *fep;
-       const struct fs_platform_info *fpi;
-
-       fep = netdev_priv(dev);
-       fpi = fep->fpi;
-
-       /*
-        * Acknowledge the interrupt if possible. If we have not
-        * found the PHY yet we can't process or acknowledge the
-        * interrupt now. Instead we ignore this interrupt for now,
-        * which we can do since it is edge triggered. It will be
-        * acknowledged later by fs_enet_open().
-        */
-       if (!fep->phy)
-               return IRQ_NONE;
-
-       fs_mii_ack_int(dev);
-       fs_mii_link_status_change_check(dev, 0);
-
-       return IRQ_HANDLED;
-}
-
 static void fs_timeout(struct net_device *dev)
 {
        struct fs_enet_private *fep = netdev_priv(dev);
@@ -722,10 +694,13 @@ static void fs_timeout(struct net_device *dev)
        spin_lock_irqsave(&fep->lock, flags);
 
        if (dev->flags & IFF_UP) {
+               phy_stop(fep->phydev);
                (*fep->ops->stop)(dev);
                (*fep->ops->restart)(dev);
+               phy_start(fep->phydev);
        }
 
+       phy_start(fep->phydev);
        wake = fep->tx_free && !(CBDR_SC(fep->cur_tx) & BD_ENET_TX_READY);
        spin_unlock_irqrestore(&fep->lock, flags);
 
@@ -733,35 +708,112 @@ static void fs_timeout(struct net_device *dev)
                netif_wake_queue(dev);
 }
 
+/*-----------------------------------------------------------------------------
+ *  generic link-change handler - should be sufficient for most cases
+ *-----------------------------------------------------------------------------*/
+static void generic_adjust_link(struct  net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       struct phy_device *phydev = fep->phydev;
+       int new_state = 0;
+
+       if (phydev->link) {
+
+               /* adjust to duplex mode */
+               if (phydev->duplex != fep->oldduplex){
+                       new_state = 1;
+                       fep->oldduplex = phydev->duplex;
+               }
+
+               if (phydev->speed != fep->oldspeed) {
+                       new_state = 1;
+                       fep->oldspeed = phydev->speed;
+               }
+
+               if (!fep->oldlink) {
+                       new_state = 1;
+                       fep->oldlink = 1;
+                       netif_schedule(dev);
+                       netif_carrier_on(dev);
+                       netif_start_queue(dev);
+               }
+
+               if (new_state)
+                       fep->ops->restart(dev);
+
+       } else if (fep->oldlink) {
+               new_state = 1;
+               fep->oldlink = 0;
+               fep->oldspeed = 0;
+               fep->oldduplex = -1;
+               netif_carrier_off(dev);
+               netif_stop_queue(dev);
+       }
+
+       if (new_state && netif_msg_link(fep))
+               phy_print_status(phydev);
+}
+
+
+static void fs_adjust_link(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       unsigned long flags;
+
+       spin_lock_irqsave(&fep->lock, flags);
+
+       if(fep->ops->adjust_link)
+               fep->ops->adjust_link(dev);
+       else
+               generic_adjust_link(dev);
+
+       spin_unlock_irqrestore(&fep->lock, flags);
+}
+
+static int fs_init_phy(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       struct phy_device *phydev;
+
+       fep->oldlink = 0;
+       fep->oldspeed = 0;
+       fep->oldduplex = -1;
+       if(fep->fpi->bus_id)
+               phydev = phy_connect(dev, fep->fpi->bus_id, &fs_adjust_link, 0);
+       else {
+               printk("No phy bus ID specified in BSP code\n");
+               return -EINVAL;
+       }
+       if (IS_ERR(phydev)) {
+               printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
+               return PTR_ERR(phydev);
+       }
+
+       fep->phydev = phydev;
+
+       return 0;
+}
+
+
 static int fs_enet_open(struct net_device *dev)
 {
        struct fs_enet_private *fep = netdev_priv(dev);
-       const struct fs_platform_info *fpi = fep->fpi;
        int r;
+       int err;
 
        /* Install our interrupt handler. */
        r = fs_request_irq(dev, fep->interrupt, "fs_enet-mac", fs_enet_interrupt);
        if (r != 0) {
                printk(KERN_ERR DRV_MODULE_NAME
-                      ": %s Could not allocate FEC IRQ!", dev->name);
+                      ": %s Could not allocate FS_ENET IRQ!", dev->name);
                return -EINVAL;
        }
 
-       /* Install our phy interrupt handler */
-       if (fpi->phy_irq != -1) {
-
-               r = fs_request_irq(dev, fpi->phy_irq, "fs_enet-phy", fs_mii_link_interrupt);
-               if (r != 0) {
-                       printk(KERN_ERR DRV_MODULE_NAME
-                              ": %s Could not allocate PHY IRQ!", dev->name);
-                       fs_free_irq(dev, fep->interrupt);
-                       return -EINVAL;
-               }
-       }
+       err = fs_init_phy(dev);
+       if(err)
+               return err;
 
-       fs_mii_startup(dev);
-       netif_carrier_off(dev);
-       fs_mii_link_status_change_check(dev, 1);
+       phy_start(fep->phydev);
 
        return 0;
 }
@@ -769,20 +821,19 @@ static int fs_enet_open(struct net_device *dev)
 static int fs_enet_close(struct net_device *dev)
 {
        struct fs_enet_private *fep = netdev_priv(dev);
-       const struct fs_platform_info *fpi = fep->fpi;
        unsigned long flags;
 
        netif_stop_queue(dev);
        netif_carrier_off(dev);
-       fs_mii_shutdown(dev);
+       phy_stop(fep->phydev);
 
        spin_lock_irqsave(&fep->lock, flags);
        (*fep->ops->stop)(dev);
        spin_unlock_irqrestore(&fep->lock, flags);
 
        /* release any irqs */
-       if (fpi->phy_irq != -1)
-               fs_free_irq(dev, fpi->phy_irq);
+       phy_disconnect(fep->phydev);
+       fep->phydev = NULL;
        fs_free_irq(dev, fep->interrupt);
 
        return 0;
@@ -830,33 +881,19 @@ static void fs_get_regs(struct net_device *dev, struct ethtool_regs *regs,
 static int fs_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 {
        struct fs_enet_private *fep = netdev_priv(dev);
-       unsigned long flags;
-       int rc;
-
-       spin_lock_irqsave(&fep->lock, flags);
-       rc = mii_ethtool_gset(&fep->mii_if, cmd);
-       spin_unlock_irqrestore(&fep->lock, flags);
-
-       return rc;
+       return phy_ethtool_gset(fep->phydev, cmd);
 }
 
 static int fs_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 {
        struct fs_enet_private *fep = netdev_priv(dev);
-       unsigned long flags;
-       int rc;
-
-       spin_lock_irqsave(&fep->lock, flags);
-       rc = mii_ethtool_sset(&fep->mii_if, cmd);
-       spin_unlock_irqrestore(&fep->lock, flags);
-
-       return rc;
+       phy_ethtool_sset(fep->phydev, cmd);
+       return 0;
 }
 
 static int fs_nway_reset(struct net_device *dev)
 {
-       struct fs_enet_private *fep = netdev_priv(dev);
-       return mii_nway_restart(&fep->mii_if);
+       return 0;
 }
 
 static u32 fs_get_msglevel(struct net_device *dev)
@@ -898,7 +935,7 @@ static int fs_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
                return -EINVAL;
 
        spin_lock_irqsave(&fep->lock, flags);
-       rc = generic_mii_ioctl(&fep->mii_if, mii, cmd, NULL);
+       rc = phy_mii_ioctl(fep->phydev, mii, cmd);
        spin_unlock_irqrestore(&fep->lock, flags);
        return rc;
 }
@@ -1030,12 +1067,6 @@ static struct net_device *fs_init_instance(struct device *dev,
        }
        registered = 1;
 
-       err = fs_mii_connect(ndev);
-       if (err != 0) {
-               printk(KERN_ERR DRV_MODULE_NAME
-                      ": %s fs_mii_connect failed.\n", ndev->name);
-               goto err;
-       }
 
        return ndev;
 
@@ -1073,8 +1104,6 @@ static int fs_cleanup_instance(struct net_device *ndev)
 
        fpi = fep->fpi;
 
-       fs_mii_disconnect(ndev);
-
        unregister_netdev(ndev);
 
        dma_free_coherent(fep->dev, (fpi->tx_ring + fpi->rx_ring) * sizeof(cbd_t),
@@ -1196,17 +1225,39 @@ static int __init fs_init(void)
        r = setup_immap();
        if (r != 0)
                return r;
-       r = driver_register(&fs_enet_fec_driver);
+
+#ifdef CONFIG_FS_ENET_HAS_FCC
+       /* let's insert mii stuff */
+       r = fs_enet_mdio_bb_init();
+
+       if (r != 0) {
+               printk(KERN_ERR DRV_MODULE_NAME
+                       "BB PHY init failed.\n");
+               return r;
+       }
+       r = driver_register(&fs_enet_fcc_driver);
        if (r != 0)
                goto err;
+#endif
 
-       r = driver_register(&fs_enet_fcc_driver);
+#ifdef CONFIG_FS_ENET_HAS_FEC
+       r =  fs_enet_mdio_fec_init();
+       if (r != 0) {
+               printk(KERN_ERR DRV_MODULE_NAME
+                       "FEC PHY init failed.\n");
+               return r;
+       }
+
+       r = driver_register(&fs_enet_fec_driver);
        if (r != 0)
                goto err;
+#endif
 
+#ifdef CONFIG_FS_ENET_HAS_SCC
        r = driver_register(&fs_enet_scc_driver);
        if (r != 0)
                goto err;
+#endif
 
        return 0;
 err:
diff --git a/drivers/net/fs_enet/fs_enet-mii.c b/drivers/net/fs_enet/fs_enet-mii.c
deleted file mode 100644 (file)
index b7e6e21..0000000
+++ /dev/null
@@ -1,505 +0,0 @@
-/*
- * Combined Ethernet driver for Motorola MPC8xx and MPC82xx.
- *
- * Copyright (c) 2003 Intracom S.A. 
- *  by Pantelis Antoniou <panto@intracom.gr>
- * 
- * 2005 (c) MontaVista Software, Inc. 
- * Vitaly Bordug <vbordug@ru.mvista.com>
- *
- * Heavily based on original FEC driver by Dan Malek <dan@embeddededge.com>
- * and modifications by Joakim Tjernlund <joakim.tjernlund@lumentis.se>
- *
- * This file is licensed under the terms of the GNU General Public License 
- * version 2. This program is licensed "as is" without any warranty of any 
- * kind, whether express or implied.
- */
-
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/string.h>
-#include <linux/ptrace.h>
-#include <linux/errno.h>
-#include <linux/ioport.h>
-#include <linux/slab.h>
-#include <linux/interrupt.h>
-#include <linux/pci.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/netdevice.h>
-#include <linux/etherdevice.h>
-#include <linux/skbuff.h>
-#include <linux/spinlock.h>
-#include <linux/mii.h>
-#include <linux/ethtool.h>
-#include <linux/bitops.h>
-
-#include <asm/pgtable.h>
-#include <asm/irq.h>
-#include <asm/uaccess.h>
-
-#include "fs_enet.h"
-
-/*************************************************/
-
-/*
- * Generic PHY support.
- * Should work for all PHYs, but link change is detected by polling
- */
-
-static void generic_timer_callback(unsigned long data)
-{
-       struct net_device *dev = (struct net_device *)data;
-       struct fs_enet_private *fep = netdev_priv(dev);
-
-       fep->phy_timer_list.expires = jiffies + HZ / 2;
-
-       add_timer(&fep->phy_timer_list);
-
-       fs_mii_link_status_change_check(dev, 0);
-}
-
-static void generic_startup(struct net_device *dev)
-{
-       struct fs_enet_private *fep = netdev_priv(dev);
-
-       fep->phy_timer_list.expires = jiffies + HZ / 2; /* every 500ms */
-       fep->phy_timer_list.data = (unsigned long)dev;
-       fep->phy_timer_list.function = generic_timer_callback;
-       add_timer(&fep->phy_timer_list);
-}
-
-static void generic_shutdown(struct net_device *dev)
-{
-       struct fs_enet_private *fep = netdev_priv(dev);
-
-       del_timer_sync(&fep->phy_timer_list);
-}
-
-/* ------------------------------------------------------------------------- */
-/* The Davicom DM9161 is used on the NETTA board                            */
-
-/* register definitions */
-
-#define MII_DM9161_ANAR                4       /* Aux. Config Register         */
-#define MII_DM9161_ACR         16      /* Aux. Config Register         */
-#define MII_DM9161_ACSR                17      /* Aux. Config/Status Register  */
-#define MII_DM9161_10TCSR      18      /* 10BaseT Config/Status Reg.   */
-#define MII_DM9161_INTR                21      /* Interrupt Register           */
-#define MII_DM9161_RECR                22      /* Receive Error Counter Reg.   */
-#define MII_DM9161_DISCR       23      /* Disconnect Counter Register  */
-
-static void dm9161_startup(struct net_device *dev)
-{
-       struct fs_enet_private *fep = netdev_priv(dev);
-
-       fs_mii_write(dev, fep->mii_if.phy_id, MII_DM9161_INTR, 0x0000);
-       /* Start autonegotiation */
-       fs_mii_write(dev, fep->mii_if.phy_id, MII_BMCR, 0x1200);
-
-       set_current_state(TASK_UNINTERRUPTIBLE);
-       schedule_timeout(HZ*8);
-}
-
-static void dm9161_ack_int(struct net_device *dev)
-{
-       struct fs_enet_private *fep = netdev_priv(dev);
-
-       fs_mii_read(dev, fep->mii_if.phy_id, MII_DM9161_INTR);
-}
-
-static void dm9161_shutdown(struct net_device *dev)
-{
-       struct fs_enet_private *fep = netdev_priv(dev);
-
-       fs_mii_write(dev, fep->mii_if.phy_id, MII_DM9161_INTR, 0x0f00);
-}
-
-/**********************************************************************************/
-
-static const struct phy_info phy_info[] = {
-       {
-               .id = 0x00181b88,
-               .name = "DM9161",
-               .startup = dm9161_startup,
-               .ack_int = dm9161_ack_int,
-               .shutdown = dm9161_shutdown,
-       }, {
-               .id = 0,
-               .name = "GENERIC",
-               .startup = generic_startup,
-               .shutdown = generic_shutdown,
-       },
-};
-
-/**********************************************************************************/
-
-static int phy_id_detect(struct net_device *dev)
-{
-       struct fs_enet_private *fep = netdev_priv(dev);
-       const struct fs_platform_info *fpi = fep->fpi;
-       struct fs_enet_mii_bus *bus = fep->mii_bus;
-       int i, r, start, end, phytype, physubtype;
-       const struct phy_info *phy;
-       int phy_hwid, phy_id;
-
-       phy_hwid = -1;
-       fep->phy = NULL;
-
-       /* auto-detect? */
-       if (fpi->phy_addr == -1) {
-               start = 1;
-               end = 32;
-       } else {                /* direct */
-               start = fpi->phy_addr;
-               end = start + 1;
-       }
-
-       for (phy_id = start; phy_id < end; phy_id++) {
-               /* skip already used phy addresses on this bus */ 
-               if (bus->usage_map & (1 << phy_id))
-                       continue;
-               r = fs_mii_read(dev, phy_id, MII_PHYSID1);
-               if (r == -1 || (phytype = (r & 0xffff)) == 0xffff)
-                       continue;
-               r = fs_mii_read(dev, phy_id, MII_PHYSID2);
-               if (r == -1 || (physubtype = (r & 0xffff)) == 0xffff)
-                       continue;
-               phy_hwid = (phytype << 16) | physubtype;
-               if (phy_hwid != -1)
-                       break;
-       }
-
-       if (phy_hwid == -1) {
-               printk(KERN_ERR DRV_MODULE_NAME
-                      ": %s No PHY detected! range=0x%02x-0x%02x\n",
-                       dev->name, start, end);
-               return -1;
-       }
-
-       for (i = 0, phy = phy_info; i < ARRAY_SIZE(phy_info); i++, phy++)
-               if (phy->id == (phy_hwid >> 4) || phy->id == 0)
-                       break;
-
-       if (i >= ARRAY_SIZE(phy_info)) {
-               printk(KERN_ERR DRV_MODULE_NAME
-                      ": %s PHY id 0x%08x is not supported!\n",
-                      dev->name, phy_hwid);
-               return -1;
-       }
-
-       fep->phy = phy;
-
-       /* mark this address as used */
-       bus->usage_map |= (1 << phy_id);
-
-       printk(KERN_INFO DRV_MODULE_NAME
-              ": %s Phy @ 0x%x, type %s (0x%08x)%s\n",
-              dev->name, phy_id, fep->phy->name, phy_hwid,
-              fpi->phy_addr == -1 ? " (auto-detected)" : "");
-
-       return phy_id;
-}
-
-void fs_mii_startup(struct net_device *dev)
-{
-       struct fs_enet_private *fep = netdev_priv(dev);
-
-       if (fep->phy->startup)
-               (*fep->phy->startup) (dev);
-}
-
-void fs_mii_shutdown(struct net_device *dev)
-{
-       struct fs_enet_private *fep = netdev_priv(dev);
-
-       if (fep->phy->shutdown)
-               (*fep->phy->shutdown) (dev);
-}
-
-void fs_mii_ack_int(struct net_device *dev)
-{
-       struct fs_enet_private *fep = netdev_priv(dev);
-
-       if (fep->phy->ack_int)
-               (*fep->phy->ack_int) (dev);
-}
-
-#define MII_LINK       0x0001
-#define MII_HALF       0x0002
-#define MII_FULL       0x0004
-#define MII_BASE4      0x0008
-#define MII_10M                0x0010
-#define MII_100M       0x0020
-#define MII_1G         0x0040
-#define MII_10G                0x0080
-
-/* return full mii info at one gulp, with a usable form */
-static unsigned int mii_full_status(struct mii_if_info *mii)
-{
-       unsigned int status;
-       int bmsr, adv, lpa, neg;
-       struct fs_enet_private* fep = netdev_priv(mii->dev);
-       
-       /* first, a dummy read, needed to latch some MII phys */
-       (void)mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR);
-       bmsr = mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR);
-
-       /* no link */
-       if ((bmsr & BMSR_LSTATUS) == 0)
-               return 0;
-
-       status = MII_LINK;
-       
-       /* Lets look what ANEG says if it's supported - otherwize we shall
-          take the right values from the platform info*/
-       if(!mii->force_media) {
-               /* autoneg not completed; don't bother */
-               if ((bmsr & BMSR_ANEGCOMPLETE) == 0)
-                       return 0;
-
-               adv = (*mii->mdio_read)(mii->dev, mii->phy_id, MII_ADVERTISE);
-               lpa = (*mii->mdio_read)(mii->dev, mii->phy_id, MII_LPA);
-
-               neg = lpa & adv;
-       } else {
-               neg = fep->fpi->bus_info->lpa;
-       }
-
-       if (neg & LPA_100FULL)
-               status |= MII_FULL | MII_100M;
-       else if (neg & LPA_100BASE4)
-               status |= MII_FULL | MII_BASE4 | MII_100M;
-       else if (neg & LPA_100HALF)
-               status |= MII_HALF | MII_100M;
-       else if (neg & LPA_10FULL)
-               status |= MII_FULL | MII_10M;
-       else
-               status |= MII_HALF | MII_10M;
-       
-       return status;
-}
-
-void fs_mii_link_status_change_check(struct net_device *dev, int init_media)
-{
-       struct fs_enet_private *fep = netdev_priv(dev);
-       struct mii_if_info *mii = &fep->mii_if;
-       unsigned int mii_status;
-       int ok_to_print, link, duplex, speed;
-       unsigned long flags;
-
-       ok_to_print = netif_msg_link(fep);
-
-       mii_status = mii_full_status(mii);
-
-       if (!init_media && mii_status == fep->last_mii_status)
-               return;
-
-       fep->last_mii_status = mii_status;
-
-       link = !!(mii_status & MII_LINK);
-       duplex = !!(mii_status & MII_FULL);
-       speed = (mii_status & MII_100M) ? 100 : 10;
-
-       if (link == 0) {
-               netif_carrier_off(mii->dev);
-               netif_stop_queue(dev);
-               if (!init_media) {
-                       spin_lock_irqsave(&fep->lock, flags);
-                       (*fep->ops->stop)(dev);
-                       spin_unlock_irqrestore(&fep->lock, flags);
-               }
-
-               if (ok_to_print)
-                       printk(KERN_INFO "%s: link down\n", mii->dev->name);
-
-       } else {
-
-               mii->full_duplex = duplex;
-
-               netif_carrier_on(mii->dev);
-
-               spin_lock_irqsave(&fep->lock, flags);
-               fep->duplex = duplex;
-               fep->speed = speed;
-               (*fep->ops->restart)(dev);
-               spin_unlock_irqrestore(&fep->lock, flags);
-
-               netif_start_queue(dev);
-
-               if (ok_to_print)
-                       printk(KERN_INFO "%s: link up, %dMbps, %s-duplex\n",
-                              dev->name, speed, duplex ? "full" : "half");
-       }
-}
-
-/**********************************************************************************/
-
-int fs_mii_read(struct net_device *dev, int phy_id, int location)
-{
-       struct fs_enet_private *fep = netdev_priv(dev);
-       struct fs_enet_mii_bus *bus = fep->mii_bus;
-
-       unsigned long flags;
-       int ret;
-
-       spin_lock_irqsave(&bus->mii_lock, flags);
-       ret = (*bus->mii_read)(bus, phy_id, location);
-       spin_unlock_irqrestore(&bus->mii_lock, flags);
-
-       return ret;
-}
-
-void fs_mii_write(struct net_device *dev, int phy_id, int location, int value)
-{
-       struct fs_enet_private *fep = netdev_priv(dev);
-       struct fs_enet_mii_bus *bus = fep->mii_bus;
-       unsigned long flags;
-
-       spin_lock_irqsave(&bus->mii_lock, flags);
-       (*bus->mii_write)(bus, phy_id, location, value);
-       spin_unlock_irqrestore(&bus->mii_lock, flags);
-}
-
-/*****************************************************************************/
-
-/* list of all registered mii buses */
-static LIST_HEAD(fs_mii_bus_list);
-
-static struct fs_enet_mii_bus *lookup_bus(int method, int id)
-{
-       struct list_head *ptr;
-       struct fs_enet_mii_bus *bus;
-
-       list_for_each(ptr, &fs_mii_bus_list) {
-               bus = list_entry(ptr, struct fs_enet_mii_bus, list);
-               if (bus->bus_info->method == method &&
-                       bus->bus_info->id == id)
-                       return bus;
-       }
-       return NULL;
-}
-
-static struct fs_enet_mii_bus *create_bus(const struct fs_mii_bus_info *bi)
-{
-       struct fs_enet_mii_bus *bus;
-       int ret = 0;
-
-       bus = kmalloc(sizeof(*bus), GFP_KERNEL);
-       if (bus == NULL) {
-               ret = -ENOMEM;
-               goto err;
-       }
-       memset(bus, 0, sizeof(*bus));
-       spin_lock_init(&bus->mii_lock);
-       bus->bus_info = bi;
-       bus->refs = 0;
-       bus->usage_map = 0;
-
-       /* perform initialization */
-       switch (bi->method) {
-
-               case fsmii_fixed:
-                       ret = fs_mii_fixed_init(bus);
-                       if (ret != 0)
-                               goto err;
-                       break;
-
-               case fsmii_bitbang:
-                       ret = fs_mii_bitbang_init(bus);
-                       if (ret != 0)
-                               goto err;
-                       break;
-#ifdef CONFIG_FS_ENET_HAS_FEC
-               case fsmii_fec:
-                       ret = fs_mii_fec_init(bus);
-                       if (ret != 0)
-                               goto err;
-                       break;
-#endif
-               default:
-                       ret = -EINVAL;
-                       goto err;
-       }
-
-       list_add(&bus->list, &fs_mii_bus_list);
-
-       return bus;
-
-err:
-       kfree(bus);
-       return ERR_PTR(ret);
-}
-
-static void destroy_bus(struct fs_enet_mii_bus *bus)
-{
-       /* remove from bus list */
-       list_del(&bus->list);
-
-       /* nothing more needed */
-       kfree(bus);
-}
-
-int fs_mii_connect(struct net_device *dev)
-{
-       struct fs_enet_private *fep = netdev_priv(dev);
-       const struct fs_platform_info *fpi = fep->fpi;
-       struct fs_enet_mii_bus *bus = NULL;
-
-       /* check method validity */
-       switch (fpi->bus_info->method) {
-               case fsmii_fixed:
-               case fsmii_bitbang:
-                       break;
-#ifdef CONFIG_FS_ENET_HAS_FEC
-               case fsmii_fec:
-                       break;
-#endif
-               default:
-                       printk(KERN_ERR DRV_MODULE_NAME
-                              ": %s Unknown MII bus method (%d)!\n",
-                              dev->name, fpi->bus_info->method);
-                       return -EINVAL; 
-       }
-
-       bus = lookup_bus(fpi->bus_info->method, fpi->bus_info->id);
-
-       /* if not found create new bus */
-       if (bus == NULL) {
-               bus = create_bus(fpi->bus_info);
-               if (IS_ERR(bus)) {
-                       printk(KERN_ERR DRV_MODULE_NAME
-                              ": %s MII bus creation failure!\n", dev->name);
-                       return PTR_ERR(bus);
-               }
-       }
-
-       bus->refs++;
-
-       fep->mii_bus = bus;
-
-       fep->mii_if.dev = dev;
-       fep->mii_if.phy_id_mask = 0x1f;
-       fep->mii_if.reg_num_mask = 0x1f;
-       fep->mii_if.mdio_read = fs_mii_read;
-       fep->mii_if.mdio_write = fs_mii_write;
-       fep->mii_if.force_media = fpi->bus_info->disable_aneg;
-       fep->mii_if.phy_id = phy_id_detect(dev);
-
-       return 0;
-}
-
-void fs_mii_disconnect(struct net_device *dev)
-{
-       struct fs_enet_private *fep = netdev_priv(dev);
-       struct fs_enet_mii_bus *bus = NULL;
-
-       bus = fep->mii_bus;
-       fep->mii_bus = NULL;
-
-       if (--bus->refs <= 0)
-               destroy_bus(bus);
-}
index e7ec96c..95022c0 100644 (file)
@@ -5,6 +5,7 @@
 #include <linux/netdevice.h>
 #include <linux/types.h>
 #include <linux/list.h>
+#include <linux/phy.h>
 
 #include <linux/fs_enet_pd.h>
 
 
 #ifdef CONFIG_CPM1
 #include <asm/commproc.h>
+
+struct fec_info {
+        fec_t*  fecp;
+       u32     mii_speed;
+};
 #endif
 
 #ifdef CONFIG_CPM2
 #include <asm/cpm2.h>
 #endif
 
+/* This is used to operate with pins.
+  Note that the actual port size may
+    be different; cpm(s) handle it OK  */
+struct bb_info {
+       u8 mdio_dat_msk;
+       u8 mdio_dir_msk;
+       u8 *mdio_dir;
+       u8 *mdio_dat;
+       u8 mdc_msk;
+       u8 *mdc_dat;
+       int delay;
+};
+
 /* hw driver ops */
 struct fs_ops {
        int (*setup_data)(struct net_device *dev);
@@ -25,6 +44,7 @@ struct fs_ops {
        void (*free_bd)(struct net_device *dev);
        void (*cleanup_data)(struct net_device *dev);
        void (*set_multicast_list)(struct net_device *dev);
+       void (*adjust_link)(struct net_device *dev);
        void (*restart)(struct net_device *dev);
        void (*stop)(struct net_device *dev);
        void (*pre_request_irq)(struct net_device *dev, int irq);
@@ -100,10 +120,6 @@ struct fs_enet_mii_bus {
        };
 };
 
-int fs_mii_bitbang_init(struct fs_enet_mii_bus *bus);
-int fs_mii_fixed_init(struct fs_enet_mii_bus *bus);
-int fs_mii_fec_init(struct fs_enet_mii_bus *bus);
-
 struct fs_enet_private {
        struct device *dev;     /* pointer back to the device (must be initialized first) */
        spinlock_t lock;        /* during all ops except TX pckt processing */
@@ -130,7 +146,8 @@ struct fs_enet_private {
        struct fs_enet_mii_bus *mii_bus;
        int interrupt;
 
-       int duplex, speed;      /* current settings */
+       struct phy_device *phydev;
+       int oldduplex, oldspeed, oldlink;       /* current settings */
 
        /* event masks */
        u32 ev_napi_rx;         /* mask of NAPI rx events */
@@ -168,15 +185,9 @@ struct fs_enet_private {
 };
 
 /***************************************************************************/
-
-int fs_mii_read(struct net_device *dev, int phy_id, int location);
-void fs_mii_write(struct net_device *dev, int phy_id, int location, int value);
-
-void fs_mii_startup(struct net_device *dev);
-void fs_mii_shutdown(struct net_device *dev);
-void fs_mii_ack_int(struct net_device *dev);
-
-void fs_mii_link_status_change_check(struct net_device *dev, int init_media);
+int fs_enet_mdio_bb_init(void);
+int fs_mii_fixed_init(struct fs_enet_mii_bus *bus);
+int fs_enet_mdio_fec_init(void);
 
 void fs_init_bds(struct net_device *dev);
 void fs_cleanup_bds(struct net_device *dev);
@@ -194,7 +205,6 @@ int fs_enet_platform_init(void);
 void fs_enet_platform_cleanup(void);
 
 /***************************************************************************/
-
 /* buffer descriptor access macros */
 
 /* access macros */
index 64e2098..1ff2597 100644 (file)
@@ -34,6 +34,7 @@
 #include <linux/bitops.h>
 #include <linux/fs.h>
 #include <linux/platform_device.h>
+#include <linux/phy.h>
 
 #include <asm/immap_cpm2.h>
 #include <asm/mpc8260.h>
@@ -122,22 +123,32 @@ static int do_pd_setup(struct fs_enet_private *fep)
 
        /* Attach the memory for the FCC Parameter RAM */
        r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fcc_pram");
-       fep->fcc.ep = (void *)r->start;
-
+       fep->fcc.ep = (void *)ioremap(r->start, r->end - r->start + 1);
        if (fep->fcc.ep == NULL)
                return -EINVAL;
 
        r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fcc_regs");
-       fep->fcc.fccp = (void *)r->start;
-
+       fep->fcc.fccp = (void *)ioremap(r->start, r->end - r->start + 1);
        if (fep->fcc.fccp == NULL)
                return -EINVAL;
 
-       fep->fcc.fcccp = (void *)fep->fpi->fcc_regs_c;
+       if (fep->fpi->fcc_regs_c) {
+
+               fep->fcc.fcccp = (void *)fep->fpi->fcc_regs_c;
+       } else {
+               r = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+                               "fcc_regs_c");
+               fep->fcc.fcccp = (void *)ioremap(r->start,
+                               r->end - r->start + 1);
+       }
 
        if (fep->fcc.fcccp == NULL)
                return -EINVAL;
 
+       fep->fcc.mem = (void *)fep->fpi->mem_offset;
+       if (fep->fcc.mem == NULL)
+               return -EINVAL;
+
        return 0;
 }
 
@@ -155,8 +166,6 @@ static int setup_data(struct net_device *dev)
        if ((unsigned int)fep->fcc.idx >= 3)    /* max 3 FCCs */
                return -EINVAL;
 
-       fep->fcc.mem = (void *)fpi->mem_offset;
-
        if (do_pd_setup(fep) != 0)
                return -EINVAL;
 
@@ -394,7 +403,7 @@ static void restart(struct net_device *dev)
 
        /* adjust to speed (for RMII mode) */
        if (fpi->use_rmii) {
-               if (fep->speed == 100)
+               if (fep->phydev->speed == 100)
                        C8(fcccp, fcc_gfemr, 0x20);
                else
                        S8(fcccp, fcc_gfemr, 0x20);
@@ -420,7 +429,7 @@ static void restart(struct net_device *dev)
                S32(fccp, fcc_fpsmr, FCC_PSMR_RMII);
 
        /* adjust to duplex mode */
-       if (fep->duplex)
+       if (fep->phydev->duplex)
                S32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB);
        else
                C32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB);
@@ -486,7 +495,10 @@ static void rx_bd_done(struct net_device *dev)
 
 static void tx_kickstart(struct net_device *dev)
 {
-       /* nothing */
+       struct fs_enet_private *fep = netdev_priv(dev);
+       fcc_t *fccp = fep->fcc.fccp;
+
+       S32(fccp, fcc_ftodr, 0x80);
 }
 
 static u32 get_int_events(struct net_device *dev)
index e095470..c2c5fd4 100644 (file)
@@ -46,6 +46,7 @@
 #endif
 
 #include "fs_enet.h"
+#include "fec.h"
 
 /*************************************************/
 
 /* clear bits */
 #define FC(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) & ~(_v))
 
-
-/* CRC polynomium used by the FEC for the multicast group filtering */
-#define FEC_CRC_POLY   0x04C11DB7
-
-#define FEC_MAX_MULTICAST_ADDRS        64
-
-/* Interrupt events/masks.
-*/
-#define FEC_ENET_HBERR 0x80000000U     /* Heartbeat error          */
-#define FEC_ENET_BABR  0x40000000U     /* Babbling receiver        */
-#define FEC_ENET_BABT  0x20000000U     /* Babbling transmitter     */
-#define FEC_ENET_GRA   0x10000000U     /* Graceful stop complete   */
-#define FEC_ENET_TXF   0x08000000U     /* Full frame transmitted   */
-#define FEC_ENET_TXB   0x04000000U     /* A buffer was transmitted */
-#define FEC_ENET_RXF   0x02000000U     /* Full frame received      */
-#define FEC_ENET_RXB   0x01000000U     /* A buffer was received    */
-#define FEC_ENET_MII   0x00800000U     /* MII interrupt            */
-#define FEC_ENET_EBERR 0x00400000U     /* SDMA bus error           */
-
-#define FEC_ECNTRL_PINMUX      0x00000004
-#define FEC_ECNTRL_ETHER_EN    0x00000002
-#define FEC_ECNTRL_RESET       0x00000001
-
-#define FEC_RCNTRL_BC_REJ      0x00000010
-#define FEC_RCNTRL_PROM                0x00000008
-#define FEC_RCNTRL_MII_MODE    0x00000004
-#define FEC_RCNTRL_DRT         0x00000002
-#define FEC_RCNTRL_LOOP                0x00000001
-
-#define FEC_TCNTRL_FDEN                0x00000004
-#define FEC_TCNTRL_HBC         0x00000002
-#define FEC_TCNTRL_GTS         0x00000001
-
-
-/* Make MII read/write commands for the FEC.
-*/
-#define mk_mii_read(REG)       (0x60020000 | ((REG & 0x1f) << 18))
-#define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
-#define mk_mii_end             0
-
-#define FEC_MII_LOOPS  10000
-
 /*
- * Delay to wait for FEC reset command to complete (in us) 
+ * Delay to wait for FEC reset command to complete (in us)
  */
 #define FEC_RESET_DELAY                50
 
@@ -303,13 +262,15 @@ static void restart(struct net_device *dev)
        int r;
        u32 addrhi, addrlo;
 
+       struct mii_bus* mii = fep->phydev->bus;
+       struct fec_info* fec_inf = mii->priv;
+
        r = whack_reset(fep->fec.fecp);
        if (r != 0)
                printk(KERN_ERR DRV_MODULE_NAME
                                ": %s FEC Reset FAILED!\n", dev->name);
-
        /*
-        * Set station address. 
+        * Set station address.
         */
        addrhi = ((u32) dev->dev_addr[0] << 24) |
                 ((u32) dev->dev_addr[1] << 16) |
@@ -350,12 +311,12 @@ static void restart(struct net_device *dev)
        FW(fecp, fun_code, 0x78000000);
 
        /*
-        * Set MII speed. 
+        * Set MII speed.
         */
-       FW(fecp, mii_speed, fep->mii_bus->fec.mii_speed);
+       FW(fecp, mii_speed, fec_inf->mii_speed);
 
        /*
-        * Clear any outstanding interrupt. 
+        * Clear any outstanding interrupt.
         */
        FW(fecp, ievent, 0xffc0);
        FW(fecp, ivec, (fep->interrupt / 2) << 29);
@@ -390,11 +351,12 @@ static void restart(struct net_device *dev)
        }
 #endif
 
+
        FW(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
        /*
-        * adjust to duplex mode 
+        * adjust to duplex mode
         */
-       if (fep->duplex) {
+       if (fep->phydev->duplex) {
                FC(fecp, r_cntrl, FEC_RCNTRL_DRT);
                FS(fecp, x_cntrl, FEC_TCNTRL_FDEN);     /* FD enable */
        } else {
@@ -418,9 +380,11 @@ static void restart(struct net_device *dev)
 static void stop(struct net_device *dev)
 {
        struct fs_enet_private *fep = netdev_priv(dev);
+       const struct fs_platform_info *fpi = fep->fpi;
        fec_t *fecp = fep->fec.fecp;
-       struct fs_enet_mii_bus *bus = fep->mii_bus;
-       const struct fs_mii_bus_info *bi = bus->bus_info;
+
+       struct fec_info* feci= fep->phydev->bus->priv;
+
        int i;
 
        if ((FR(fecp, ecntrl) & FEC_ECNTRL_ETHER_EN) == 0)
@@ -444,11 +408,11 @@ static void stop(struct net_device *dev)
        fs_cleanup_bds(dev);
 
        /* shut down FEC1? that's where the mii bus is */
-       if (fep->fec.idx == 0 && bus->refs > 1 && bi->method == fsmii_fec) {
+       if (fpi->has_phy) {
                FS(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
                FS(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
                FW(fecp, ievent, FEC_ENET_MII);
-               FW(fecp, mii_speed, bus->fec.mii_speed);
+               FW(fecp, mii_speed, feci->mii_speed);
        }
 }
 
@@ -583,73 +547,3 @@ const struct fs_ops fs_fec_ops = {
        .free_bd                = free_bd,
 };
 
-/***********************************************************************/
-
-static int mii_read(struct fs_enet_mii_bus *bus, int phy_id, int location)
-{
-       fec_t *fecp = bus->fec.fecp;
-       int i, ret = -1;
-
-       if ((FR(fecp, r_cntrl) & FEC_RCNTRL_MII_MODE) == 0)
-               BUG();
-
-       /* Add PHY address to register command.  */
-       FW(fecp, mii_data, (phy_id << 23) | mk_mii_read(location));
-
-       for (i = 0; i < FEC_MII_LOOPS; i++)
-               if ((FR(fecp, ievent) & FEC_ENET_MII) != 0)
-                       break;
-
-       if (i < FEC_MII_LOOPS) {
-               FW(fecp, ievent, FEC_ENET_MII);
-               ret = FR(fecp, mii_data) & 0xffff;
-       }
-
-       return ret;
-}
-
-static void mii_write(struct fs_enet_mii_bus *bus, int phy_id, int location, int value)
-{
-       fec_t *fecp = bus->fec.fecp;
-       int i;
-
-       /* this must never happen */
-       if ((FR(fecp, r_cntrl) & FEC_RCNTRL_MII_MODE) == 0)
-               BUG();
-
-       /* Add PHY address to register command.  */
-       FW(fecp, mii_data, (phy_id << 23) | mk_mii_write(location, value));
-
-       for (i = 0; i < FEC_MII_LOOPS; i++)
-               if ((FR(fecp, ievent) & FEC_ENET_MII) != 0)
-                       break;
-
-       if (i < FEC_MII_LOOPS)
-               FW(fecp, ievent, FEC_ENET_MII);
-}
-
-int fs_mii_fec_init(struct fs_enet_mii_bus *bus)
-{
-       bd_t *bd = (bd_t *)__res;
-       const struct fs_mii_bus_info *bi = bus->bus_info;
-       fec_t *fecp;
-
-       if (bi->id != 0)
-               return -1;
-
-       bus->fec.fecp = &((immap_t *)fs_enet_immap)->im_cpm.cp_fec;
-       bus->fec.mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2)
-                               & 0x3F) << 1;
-
-       fecp = bus->fec.fecp;
-
-       FS(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
-       FS(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
-       FW(fecp, ievent, FEC_ENET_MII);
-       FW(fecp, mii_speed, bus->fec.mii_speed);
-
-       bus->mii_read = mii_read;
-       bus->mii_write = mii_write;
-
-       return 0;
-}
index eaa24fa..95ec587 100644 (file)
@@ -369,7 +369,7 @@ static void restart(struct net_device *dev)
        W16(sccp, scc_psmr, SCC_PSMR_ENCRC | SCC_PSMR_NIB22);
 
        /* Set full duplex mode if needed */
-       if (fep->duplex)
+       if (fep->phydev->duplex)
                S16(sccp, scc_psmr, SCC_PSMR_LPB | SCC_PSMR_FDE);
 
        S32(sccp, scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
@@ -500,6 +500,8 @@ static void tx_restart(struct net_device *dev)
        scc_cr_cmd(fep, CPM_CR_RESTART_TX);
 }
 
+
+
 /*************************************************************************/
 
 const struct fs_ops fs_scc_ops = {
index 48f9cf8..0b9b8b5 100644 (file)
@@ -33,6 +33,7 @@
 #include <linux/mii.h>
 #include <linux/ethtool.h>
 #include <linux/bitops.h>
+#include <linux/platform_device.h>
 
 #include <asm/pgtable.h>
 #include <asm/irq.h>
 
 #include "fs_enet.h"
 
-#ifdef CONFIG_8xx
-static int bitbang_prep_bit(u8 **dirp, u8 **datp, u8 *mskp, int port, int bit)
+static int bitbang_prep_bit(u8 **datp, u8 *mskp,
+               struct fs_mii_bit *mii_bit)
 {
-       immap_t *im = (immap_t *)fs_enet_immap;
-       void *dir, *dat, *ppar;
+       void *dat;
        int adv;
        u8 msk;
 
-       switch (port) {
-               case fsiop_porta:
-                       dir = &im->im_ioport.iop_padir;
-                       dat = &im->im_ioport.iop_padat;
-                       ppar = &im->im_ioport.iop_papar;
-                       break;
-
-               case fsiop_portb:
-                       dir = &im->im_cpm.cp_pbdir;
-                       dat = &im->im_cpm.cp_pbdat;
-                       ppar = &im->im_cpm.cp_pbpar;
-                       break;
-
-               case fsiop_portc:
-                       dir = &im->im_ioport.iop_pcdir;
-                       dat = &im->im_ioport.iop_pcdat;
-                       ppar = &im->im_ioport.iop_pcpar;
-                       break;
-
-               case fsiop_portd:
-                       dir = &im->im_ioport.iop_pddir;
-                       dat = &im->im_ioport.iop_pddat;
-                       ppar = &im->im_ioport.iop_pdpar;
-                       break;
-
-               case fsiop_porte:
-                       dir = &im->im_cpm.cp_pedir;
-                       dat = &im->im_cpm.cp_pedat;
-                       ppar = &im->im_cpm.cp_pepar;
-                       break;
-
-               default:
-                       printk(KERN_ERR DRV_MODULE_NAME
-                              "Illegal port value %d!\n", port);
-                       return -EINVAL;
-       }
-
-       adv = bit >> 3;
-       dir = (char *)dir + adv;
-       dat = (char *)dat + adv;
-       ppar = (char *)ppar + adv;
-
-       msk = 1 << (7 - (bit & 7));
-       if ((in_8(ppar) & msk) != 0) {
-               printk(KERN_ERR DRV_MODULE_NAME
-                      "pin %d on port %d is not general purpose!\n", bit, port);
-               return -EINVAL;
-       }
-
-       *dirp = dir;
-       *datp = dat;
-       *mskp = msk;
-
-       return 0;
-}
-#endif
-
-#ifdef CONFIG_8260
-static int bitbang_prep_bit(u8 **dirp, u8 **datp, u8 *mskp, int port, int bit)
-{
-       iop_cpm2_t *io = &((cpm2_map_t *)fs_enet_immap)->im_ioport;
-       void *dir, *dat, *ppar;
-       int adv;
-       u8 msk;
-
-       switch (port) {
-               case fsiop_porta:
-                       dir = &io->iop_pdira;
-                       dat = &io->iop_pdata;
-                       ppar = &io->iop_ppara;
-                       break;
-
-               case fsiop_portb:
-                       dir = &io->iop_pdirb;
-                       dat = &io->iop_pdatb;
-                       ppar = &io->iop_pparb;
-                       break;
-
-               case fsiop_portc:
-                       dir = &io->iop_pdirc;
-                       dat = &io->iop_pdatc;
-                       ppar = &io->iop_pparc;
-                       break;
-
-               case fsiop_portd:
-                       dir = &io->iop_pdird;
-                       dat = &io->iop_pdatd;
-                       ppar = &io->iop_ppard;
-                       break;
-
-               default:
-                       printk(KERN_ERR DRV_MODULE_NAME
-                              "Illegal port value %d!\n", port);
-                       return -EINVAL;
-       }
+       dat = (void*) mii_bit->offset;
 
-       adv = bit >> 3;
-       dir = (char *)dir + adv;
+       adv = mii_bit->bit >> 3;
        dat = (char *)dat + adv;
-       ppar = (char *)ppar + adv;
 
-       msk = 1 << (7 - (bit & 7));
-       if ((in_8(ppar) & msk) != 0) {
-               printk(KERN_ERR DRV_MODULE_NAME
-                      "pin %d on port %d is not general purpose!\n", bit, port);
-               return -EINVAL;
-       }
+       msk = 1 << (7 - (mii_bit->bit & 7));
 
-       *dirp = dir;
        *datp = dat;
        *mskp = msk;
 
        return 0;
 }
-#endif
 
 static inline void bb_set(u8 *p, u8 m)
 {
@@ -179,44 +76,44 @@ static inline int bb_read(u8 *p, u8 m)
        return (in_8(p) & m) != 0;
 }
 
-static inline void mdio_active(struct fs_enet_mii_bus *bus)
+static inline void mdio_active(struct bb_info *bitbang)
 {
-       bb_set(bus->bitbang.mdio_dir, bus->bitbang.mdio_msk);
+       bb_set(bitbang->mdio_dir, bitbang->mdio_dir_msk);
 }
 
-static inline void mdio_tristate(struct fs_enet_mii_bus *bus)
+static inline void mdio_tristate(struct bb_info *bitbang )
 {
-       bb_clr(bus->bitbang.mdio_dir, bus->bitbang.mdio_msk);
+       bb_clr(bitbang->mdio_dir, bitbang->mdio_dir_msk);
 }
 
-static inline int mdio_read(struct fs_enet_mii_bus *bus)
+static inline int mdio_read(struct bb_info *bitbang )
 {
-       return bb_read(bus->bitbang.mdio_dat, bus->bitbang.mdio_msk);
+       return bb_read(bitbang->mdio_dat, bitbang->mdio_dat_msk);
 }
 
-static inline void mdio(struct fs_enet_mii_bus *bus, int what)
+static inline void mdio(struct bb_info *bitbang , int what)
 {
        if (what)
-               bb_set(bus->bitbang.mdio_dat, bus->bitbang.mdio_msk);
+               bb_set(bitbang->mdio_dat, bitbang->mdio_dat_msk);
        else
-               bb_clr(bus->bitbang.mdio_dat, bus->bitbang.mdio_msk);
+               bb_clr(bitbang->mdio_dat, bitbang->mdio_dat_msk);
 }
 
-static inline void mdc(struct fs_enet_mii_bus *bus, int what)
+static inline void mdc(struct bb_info *bitbang , int what)
 {
        if (what)
-               bb_set(bus->bitbang.mdc_dat, bus->bitbang.mdc_msk);
+               bb_set(bitbang->mdc_dat, bitbang->mdc_msk);
        else
-               bb_clr(bus->bitbang.mdc_dat, bus->bitbang.mdc_msk);
+               bb_clr(bitbang->mdc_dat, bitbang->mdc_msk);
 }
 
-static inline void mii_delay(struct fs_enet_mii_bus *bus)
+static inline void mii_delay(struct bb_info *bitbang )
 {
-       udelay(bus->bus_info->i.bitbang.delay);
+       udelay(bitbang->delay);
 }
 
 /* Utility to send the preamble, address, and register (common to read and write). */
-static void bitbang_pre(struct fs_enet_mii_bus *bus, int read, u8 addr, u8 reg)
+static void bitbang_pre(struct bb_info *bitbang , int read, u8 addr, u8 reg)
 {
        int j;
 
@@ -228,177 +125,284 @@ static void bitbang_pre(struct fs_enet_mii_bus *bus, int read, u8 addr, u8 reg)
         * but it is safer and will be much more robust.
         */
 
-       mdio_active(bus);
-       mdio(bus, 1);
+       mdio_active(bitbang);
+       mdio(bitbang, 1);
        for (j = 0; j < 32; j++) {
-               mdc(bus, 0);
-               mii_delay(bus);
-               mdc(bus, 1);
-               mii_delay(bus);
+               mdc(bitbang, 0);
+               mii_delay(bitbang);
+               mdc(bitbang, 1);
+               mii_delay(bitbang);
        }
 
        /* send the start bit (01) and the read opcode (10) or write (10) */
-       mdc(bus, 0);
-       mdio(bus, 0);
-       mii_delay(bus);
-       mdc(bus, 1);
-       mii_delay(bus);
-       mdc(bus, 0);
-       mdio(bus, 1);
-       mii_delay(bus);
-       mdc(bus, 1);
-       mii_delay(bus);
-       mdc(bus, 0);
-       mdio(bus, read);
-       mii_delay(bus);
-       mdc(bus, 1);
-       mii_delay(bus);
-       mdc(bus, 0);
-       mdio(bus, !read);
-       mii_delay(bus);
-       mdc(bus, 1);
-       mii_delay(bus);
+       mdc(bitbang, 0);
+       mdio(bitbang, 0);
+       mii_delay(bitbang);
+       mdc(bitbang, 1);
+       mii_delay(bitbang);
+       mdc(bitbang, 0);
+       mdio(bitbang, 1);
+       mii_delay(bitbang);
+       mdc(bitbang, 1);
+       mii_delay(bitbang);
+       mdc(bitbang, 0);
+       mdio(bitbang, read);
+       mii_delay(bitbang);
+       mdc(bitbang, 1);
+       mii_delay(bitbang);
+       mdc(bitbang, 0);
+       mdio(bitbang, !read);
+       mii_delay(bitbang);
+       mdc(bitbang, 1);
+       mii_delay(bitbang);
 
        /* send the PHY address */
        for (j = 0; j < 5; j++) {
-               mdc(bus, 0);
-               mdio(bus, (addr & 0x10) != 0);
-               mii_delay(bus);
-               mdc(bus, 1);
-               mii_delay(bus);
+               mdc(bitbang, 0);
+               mdio(bitbang, (addr & 0x10) != 0);
+               mii_delay(bitbang);
+               mdc(bitbang, 1);
+               mii_delay(bitbang);
                addr <<= 1;
        }
 
        /* send the register address */
        for (j = 0; j < 5; j++) {
-               mdc(bus, 0);
-               mdio(bus, (reg & 0x10) != 0);
-               mii_delay(bus);
-               mdc(bus, 1);
-               mii_delay(bus);
+               mdc(bitbang, 0);
+               mdio(bitbang, (reg & 0x10) != 0);
+               mii_delay(bitbang);
+               mdc(bitbang, 1);
+               mii_delay(bitbang);
                reg <<= 1;
        }
 }
 
-static int mii_read(struct fs_enet_mii_bus *bus, int phy_id, int location)
+static int fs_enet_mii_bb_read(struct mii_bus *bus , int phy_id, int location)
 {
        u16 rdreg;
        int ret, j;
        u8 addr = phy_id & 0xff;
        u8 reg = location & 0xff;
+       struct bb_info* bitbang = bus->priv;
 
-       bitbang_pre(bus, 1, addr, reg);
+       bitbang_pre(bitbang, 1, addr, reg);
 
        /* tri-state our MDIO I/O pin so we can read */
-       mdc(bus, 0);
-       mdio_tristate(bus);
-       mii_delay(bus);
-       mdc(bus, 1);
-       mii_delay(bus);
+       mdc(bitbang, 0);
+       mdio_tristate(bitbang);
+       mii_delay(bitbang);
+       mdc(bitbang, 1);
+       mii_delay(bitbang);
 
        /* check the turnaround bit: the PHY should be driving it to zero */
-       if (mdio_read(bus) != 0) {
+       if (mdio_read(bitbang) != 0) {
                /* PHY didn't drive TA low */
                for (j = 0; j < 32; j++) {
-                       mdc(bus, 0);
-                       mii_delay(bus);
-                       mdc(bus, 1);
-                       mii_delay(bus);
+                       mdc(bitbang, 0);
+                       mii_delay(bitbang);
+                       mdc(bitbang, 1);
+                       mii_delay(bitbang);
                }
                ret = -1;
                goto out;
        }
 
-       mdc(bus, 0);
-       mii_delay(bus);
+       mdc(bitbang, 0);
+       mii_delay(bitbang);
 
        /* read 16 bits of register data, MSB first */
        rdreg = 0;
        for (j = 0; j < 16; j++) {
-               mdc(bus, 1);
-               mii_delay(bus);
+               mdc(bitbang, 1);
+               mii_delay(bitbang);
                rdreg <<= 1;
-               rdreg |= mdio_read(bus);
-               mdc(bus, 0);
-               mii_delay(bus);
+               rdreg |= mdio_read(bitbang);
+               mdc(bitbang, 0);
+               mii_delay(bitbang);
        }
 
-       mdc(bus, 1);
-       mii_delay(bus);
-       mdc(bus, 0);
-       mii_delay(bus);
-       mdc(bus, 1);
-       mii_delay(bus);
+       mdc(bitbang, 1);
+       mii_delay(bitbang);
+       mdc(bitbang, 0);
+       mii_delay(bitbang);
+       mdc(bitbang, 1);
+       mii_delay(bitbang);
 
        ret = rdreg;
 out:
        return ret;
 }
 
-static void mii_write(struct fs_enet_mii_bus *bus, int phy_id, int location, int val)
+static int fs_enet_mii_bb_write(struct mii_bus *bus, int phy_id, int location, u16 val)
 {
        int j;
+       struct bb_info* bitbang = bus->priv;
+
        u8 addr = phy_id & 0xff;
        u8 reg = location & 0xff;
        u16 value = val & 0xffff;
 
-       bitbang_pre(bus, 0, addr, reg);
+       bitbang_pre(bitbang, 0, addr, reg);
 
        /* send the turnaround (10) */
-       mdc(bus, 0);
-       mdio(bus, 1);
-       mii_delay(bus);
-       mdc(bus, 1);
-       mii_delay(bus);
-       mdc(bus, 0);
-       mdio(bus, 0);
-       mii_delay(bus);
-       mdc(bus, 1);
-       mii_delay(bus);
+       mdc(bitbang, 0);
+       mdio(bitbang, 1);
+       mii_delay(bitbang);
+       mdc(bitbang, 1);
+       mii_delay(bitbang);
+       mdc(bitbang, 0);
+       mdio(bitbang, 0);
+       mii_delay(bitbang);
+       mdc(bitbang, 1);
+       mii_delay(bitbang);
 
        /* write 16 bits of register data, MSB first */
        for (j = 0; j < 16; j++) {
-               mdc(bus, 0);
-               mdio(bus, (value & 0x8000) != 0);
-               mii_delay(bus);
-               mdc(bus, 1);
-               mii_delay(bus);
+               mdc(bitbang, 0);
+               mdio(bitbang, (value & 0x8000) != 0);
+               mii_delay(bitbang);
+               mdc(bitbang, 1);
+               mii_delay(bitbang);
                value <<= 1;
        }
 
        /*
         * Tri-state the MDIO line.
         */
-       mdio_tristate(bus);
-       mdc(bus, 0);
-       mii_delay(bus);
-       mdc(bus, 1);
-       mii_delay(bus);
+       mdio_tristate(bitbang);
+       mdc(bitbang, 0);
+       mii_delay(bitbang);
+       mdc(bitbang, 1);
+       mii_delay(bitbang);
+       return 0;
 }
 
-int fs_mii_bitbang_init(struct fs_enet_mii_bus *bus)
+static int fs_enet_mii_bb_reset(struct mii_bus *bus)
+{
+       /*nothing here - dunno how to reset it*/
+       return 0;
+}
+
+static int fs_mii_bitbang_init(struct bb_info *bitbang, struct fs_mii_bb_platform_info* fmpi)
 {
-       const struct fs_mii_bus_info *bi = bus->bus_info;
        int r;
 
-       r = bitbang_prep_bit(&bus->bitbang.mdio_dir,
-                        &bus->bitbang.mdio_dat,
-                        &bus->bitbang.mdio_msk,
-                        bi->i.bitbang.mdio_port,
-                        bi->i.bitbang.mdio_bit);
+       bitbang->delay = fmpi->delay;
+
+       r = bitbang_prep_bit(&bitbang->mdio_dir,
+                        &bitbang->mdio_dir_msk,
+                        &fmpi->mdio_dir);
        if (r != 0)
                return r;
 
-       r = bitbang_prep_bit(&bus->bitbang.mdc_dir,
-                        &bus->bitbang.mdc_dat,
-                        &bus->bitbang.mdc_msk,
-                        bi->i.bitbang.mdc_port,
-                        bi->i.bitbang.mdc_bit);
+       r = bitbang_prep_bit(&bitbang->mdio_dat,
+                        &bitbang->mdio_dat_msk,
+                        &fmpi->mdio_dat);
        if (r != 0)
                return r;
 
-       bus->mii_read = mii_read;
-       bus->mii_write = mii_write;
+       r = bitbang_prep_bit(&bitbang->mdc_dat,
+                        &bitbang->mdc_msk,
+                        &fmpi->mdc_dat);
+       if (r != 0)
+               return r;
 
        return 0;
 }
+
+
+static int __devinit fs_enet_mdio_probe(struct device *dev)
+{
+       struct platform_device *pdev = to_platform_device(dev);
+       struct fs_mii_bb_platform_info *pdata;
+       struct mii_bus *new_bus;
+       struct bb_info *bitbang;
+       int err = 0;
+
+       if (NULL == dev)
+               return -EINVAL;
+
+       new_bus = kzalloc(sizeof(struct mii_bus), GFP_KERNEL);
+
+       if (NULL == new_bus)
+               return -ENOMEM;
+
+       bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
+
+       if (NULL == bitbang)
+               return -ENOMEM;
+
+       new_bus->name = "BB MII Bus",
+       new_bus->read = &fs_enet_mii_bb_read,
+       new_bus->write = &fs_enet_mii_bb_write,
+       new_bus->reset = &fs_enet_mii_bb_reset,
+       new_bus->id = pdev->id;
+
+       new_bus->phy_mask = ~0x9;
+       pdata = (struct fs_mii_bb_platform_info *)pdev->dev.platform_data;
+
+       if (NULL == pdata) {
+               printk(KERN_ERR "gfar mdio %d: Missing platform data!\n", pdev->id);
+               return -ENODEV;
+       }
+
+       /*set up workspace*/
+       fs_mii_bitbang_init(bitbang, pdata);
+
+       new_bus->priv = bitbang;
+
+       new_bus->irq = pdata->irq;
+
+       new_bus->dev = dev;
+       dev_set_drvdata(dev, new_bus);
+
+       err = mdiobus_register(new_bus);
+
+       if (0 != err) {
+               printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
+                               new_bus->name);
+               goto bus_register_fail;
+       }
+
+       return 0;
+
+bus_register_fail:
+       kfree(bitbang);
+       kfree(new_bus);
+
+       return err;
+}
+
+
+static int fs_enet_mdio_remove(struct device *dev)
+{
+       struct mii_bus *bus = dev_get_drvdata(dev);
+
+       mdiobus_unregister(bus);
+
+       dev_set_drvdata(dev, NULL);
+
+       iounmap((void *) (&bus->priv));
+       bus->priv = NULL;
+       kfree(bus);
+
+       return 0;
+}
+
+static struct device_driver fs_enet_bb_mdio_driver = {
+       .name = "fsl-bb-mdio",
+       .bus = &platform_bus_type,
+       .probe = fs_enet_mdio_probe,
+       .remove = fs_enet_mdio_remove,
+};
+
+int fs_enet_mdio_bb_init(void)
+{
+       return driver_register(&fs_enet_bb_mdio_driver);
+}
+
+void fs_enet_mdio_bb_exit(void)
+{
+       driver_unregister(&fs_enet_bb_mdio_driver);
+}
+
diff --git a/drivers/net/fs_enet/mii-fec.c b/drivers/net/fs_enet/mii-fec.c
new file mode 100644 (file)
index 0000000..1328e10
--- /dev/null
@@ -0,0 +1,243 @@
+/*
+ * Combined Ethernet driver for Motorola MPC8xx and MPC82xx.
+ *
+ * Copyright (c) 2003 Intracom S.A.
+ *  by Pantelis Antoniou <panto@intracom.gr>
+ *
+ * 2005 (c) MontaVista Software, Inc.
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/string.h>
+#include <linux/ptrace.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/spinlock.h>
+#include <linux/mii.h>
+#include <linux/ethtool.h>
+#include <linux/bitops.h>
+#include <linux/platform_device.h>
+
+#include <asm/pgtable.h>
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+
+#include "fs_enet.h"
+#include "fec.h"
+
+/* Make MII read/write commands for the FEC.
+*/
+#define mk_mii_read(REG)       (0x60020000 | ((REG & 0x1f) << 18))
+#define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
+#define mk_mii_end             0
+
+#define FEC_MII_LOOPS  10000
+
+static int match_has_phy (struct device *dev, void* data)
+{
+       struct platform_device* pdev = container_of(dev, struct platform_device, dev);
+       struct fs_platform_info* fpi;
+       if(strcmp(pdev->name, (char*)data))
+       {
+           return 0;
+       }
+
+       fpi = pdev->dev.platform_data;
+       if((fpi)&&(fpi->has_phy))
+               return 1;
+       return 0;
+}
+
+static int fs_mii_fec_init(struct fec_info* fec, struct fs_mii_fec_platform_info *fmpi)
+{
+       struct resource *r;
+       fec_t *fecp;
+       char* name = "fsl-cpm-fec";
+
+       /* we need fec in order to be useful */
+       struct platform_device *fec_pdev =
+               container_of(bus_find_device(&platform_bus_type, NULL, name, match_has_phy),
+                               struct platform_device, dev);
+
+       if(fec_pdev == NULL) {
+               printk(KERN_ERR"Unable to find PHY for %s", name);
+               return -ENODEV;
+       }
+
+       r = platform_get_resource_byname(fec_pdev, IORESOURCE_MEM, "regs");
+
+       fec->fecp = fecp = (fec_t*)ioremap(r->start,sizeof(fec_t));
+       fec->mii_speed = fmpi->mii_speed;
+
+       setbits32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE);     /* MII enable */
+       setbits32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
+       out_be32(&fecp->fec_ievent, FEC_ENET_MII);
+       out_be32(&fecp->fec_mii_speed, fec->mii_speed);
+
+       return 0;
+}
+
+static int fs_enet_fec_mii_read(struct mii_bus *bus , int phy_id, int location)
+{
+       struct fec_info* fec = bus->priv;
+       fec_t *fecp = fec->fecp;
+       int i, ret = -1;
+
+       if ((in_be32(&fecp->fec_r_cntrl) & FEC_RCNTRL_MII_MODE) == 0)
+               BUG();
+
+       /* Add PHY address to register command.  */
+       out_be32(&fecp->fec_mii_data, (phy_id << 23) | mk_mii_read(location));
+
+       for (i = 0; i < FEC_MII_LOOPS; i++)
+               if ((in_be32(&fecp->fec_ievent) & FEC_ENET_MII) != 0)
+                       break;
+
+       if (i < FEC_MII_LOOPS) {
+               out_be32(&fecp->fec_ievent, FEC_ENET_MII);
+               ret = in_be32(&fecp->fec_mii_data) & 0xffff;
+       }
+
+       return ret;
+
+}
+
+static int fs_enet_fec_mii_write(struct mii_bus *bus, int phy_id, int location, u16 val)
+{
+       struct fec_info* fec = bus->priv;
+       fec_t *fecp = fec->fecp;
+       int i;
+
+       /* this must never happen */
+       if ((in_be32(&fecp->fec_r_cntrl) & FEC_RCNTRL_MII_MODE) == 0)
+               BUG();
+
+       /* Add PHY address to register command.  */
+       out_be32(&fecp->fec_mii_data, (phy_id << 23) | mk_mii_write(location, val));
+
+       for (i = 0; i < FEC_MII_LOOPS; i++)
+               if ((in_be32(&fecp->fec_ievent) & FEC_ENET_MII) != 0)
+                       break;
+
+       if (i < FEC_MII_LOOPS)
+               out_be32(&fecp->fec_ievent, FEC_ENET_MII);
+
+       return 0;
+
+}
+
+static int fs_enet_fec_mii_reset(struct mii_bus *bus)
+{
+       /* nothing here - for now */
+       return 0;
+}
+
+static int __devinit fs_enet_fec_mdio_probe(struct device *dev)
+{
+       struct platform_device *pdev = to_platform_device(dev);
+       struct fs_mii_fec_platform_info *pdata;
+       struct mii_bus *new_bus;
+       struct fec_info *fec;
+       int err = 0;
+       if (NULL == dev)
+               return -EINVAL;
+       new_bus = kzalloc(sizeof(struct mii_bus), GFP_KERNEL);
+
+       if (NULL == new_bus)
+               return -ENOMEM;
+
+       fec = kzalloc(sizeof(struct fec_info), GFP_KERNEL);
+
+       if (NULL == fec)
+               return -ENOMEM;
+
+       new_bus->name = "FEC MII Bus",
+       new_bus->read = &fs_enet_fec_mii_read,
+       new_bus->write = &fs_enet_fec_mii_write,
+       new_bus->reset = &fs_enet_fec_mii_reset,
+       new_bus->id = pdev->id;
+
+       pdata = (struct fs_mii_fec_platform_info *)pdev->dev.platform_data;
+
+       if (NULL == pdata) {
+               printk(KERN_ERR "fs_enet FEC mdio %d: Missing platform data!\n", pdev->id);
+               return -ENODEV;
+       }
+
+       /*set up workspace*/
+
+       fs_mii_fec_init(fec, pdata);
+       new_bus->priv = fec;
+
+       new_bus->irq = pdata->irq;
+
+       new_bus->dev = dev;
+       dev_set_drvdata(dev, new_bus);
+
+       err = mdiobus_register(new_bus);
+
+       if (0 != err) {
+               printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
+                               new_bus->name);
+               goto bus_register_fail;
+       }
+
+       return 0;
+
+bus_register_fail:
+       kfree(new_bus);
+
+       return err;
+}
+
+
+static int fs_enet_fec_mdio_remove(struct device *dev)
+{
+       struct mii_bus *bus = dev_get_drvdata(dev);
+
+       mdiobus_unregister(bus);
+
+       dev_set_drvdata(dev, NULL);
+       kfree(bus->priv);
+
+       bus->priv = NULL;
+       kfree(bus);
+
+       return 0;
+}
+
+static struct device_driver fs_enet_fec_mdio_driver = {
+       .name = "fsl-cpm-fec-mdio",
+       .bus = &platform_bus_type,
+       .probe = fs_enet_fec_mdio_probe,
+       .remove = fs_enet_fec_mdio_remove,
+};
+
+int fs_enet_mdio_fec_init(void)
+{
+       return driver_register(&fs_enet_fec_mdio_driver);
+}
+
+void fs_enet_mdio_fec_exit(void)
+{
+       driver_unregister(&fs_enet_fec_mdio_driver);
+}
+
diff --git a/drivers/net/fs_enet/mii-fixed.c b/drivers/net/fs_enet/mii-fixed.c
deleted file mode 100644 (file)
index ae4a9c3..0000000
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Combined Ethernet driver for Motorola MPC8xx and MPC82xx.
- *
- * Copyright (c) 2003 Intracom S.A. 
- *  by Pantelis Antoniou <panto@intracom.gr>
- * 
- * 2005 (c) MontaVista Software, Inc. 
- * Vitaly Bordug <vbordug@ru.mvista.com>
- *
- * This file is licensed under the terms of the GNU General Public License 
- * version 2. This program is licensed "as is" without any warranty of any 
- * kind, whether express or implied.
- */
-
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/string.h>
-#include <linux/ptrace.h>
-#include <linux/errno.h>
-#include <linux/ioport.h>
-#include <linux/slab.h>
-#include <linux/interrupt.h>
-#include <linux/pci.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/netdevice.h>
-#include <linux/etherdevice.h>
-#include <linux/skbuff.h>
-#include <linux/spinlock.h>
-#include <linux/mii.h>
-#include <linux/ethtool.h>
-#include <linux/bitops.h>
-
-#include <asm/pgtable.h>
-#include <asm/irq.h>
-#include <asm/uaccess.h>
-
-#include "fs_enet.h"
-
-static const u16 mii_regs[7] = {
-       0x3100,
-       0x786d,
-       0x0fff,
-       0x0fff,
-       0x01e1,
-       0x45e1,
-       0x0003,
-};
-
-static int mii_read(struct fs_enet_mii_bus *bus, int phy_id, int location)
-{
-       int ret = 0;
-
-       if ((unsigned int)location >= ARRAY_SIZE(mii_regs))
-               return -1;
-
-       if (location != 5)
-               ret = mii_regs[location];
-       else
-               ret = bus->fixed.lpa;
-
-       return ret;
-}
-
-static void mii_write(struct fs_enet_mii_bus *bus, int phy_id, int location, int val)
-{
-       /* do nothing */
-}
-
-int fs_mii_fixed_init(struct fs_enet_mii_bus *bus)
-{
-       const struct fs_mii_bus_info *bi = bus->bus_info;
-
-       bus->fixed.lpa = 0x45e1;        /* default 100Mb, full duplex */
-
-       /* if speed is fixed at 10Mb, remove 100Mb modes */
-       if (bi->i.fixed.speed == 10)
-               bus->fixed.lpa &= ~LPA_100;
-
-       /* if duplex is half, remove full duplex modes */
-       if (bi->i.fixed.duplex == 0)
-               bus->fixed.lpa &= ~LPA_DUPLEX;
-
-       bus->mii_read = mii_read;
-       bus->mii_write = mii_write;
-
-       return 0;
-}
index c1c3452..5b4dbfe 100644 (file)
@@ -326,7 +326,7 @@ MODULE_PARM_DESC(dma, "LANCE/PCnet ISA DMA channel (ignored for some devices)");
 MODULE_PARM_DESC(irq, "LANCE/PCnet IRQ number (ignored for some devices)");
 MODULE_PARM_DESC(lance_debug, "LANCE/PCnet debug level (0-7)");
 
-int init_module(void)
+int __init init_module(void)
 {
        struct net_device *dev;
        int this_dev, found = 0;
index 646e89f..c0ec7f6 100644 (file)
@@ -406,7 +406,7 @@ MODULE_PARM_DESC(mem, "memory base address(es)");
 MODULE_DESCRIPTION("Mylex LNE390A/B EISA Ethernet driver");
 MODULE_LICENSE("GPL");
 
-int init_module(void)
+int __init init_module(void)
 {
        struct net_device *dev;
        int this_dev, found = 0;
index fa854c8..4d52ecf 100644 (file)
@@ -1323,7 +1323,7 @@ MODULE_PARM_DESC(irq, "NI5210 IRQ number,required");
 MODULE_PARM_DESC(memstart, "NI5210 memory base address,required");
 MODULE_PARM_DESC(memend, "NI5210 memory end address,required");
 
-int init_module(void)
+int __init init_module(void)
 {
        if(io <= 0x0 || !memend || !memstart || irq < 2) {
                printk("ni52: Autoprobing not allowed for modules.\nni52: Set symbols 'io' 'irq' 'memstart' and 'memend'\n");
index bb42ff2..810cc57 100644 (file)
@@ -1253,7 +1253,7 @@ MODULE_PARM_DESC(irq, "ni6510 IRQ number (ignored for some cards)");
 MODULE_PARM_DESC(io, "ni6510 I/O base address");
 MODULE_PARM_DESC(dma, "ni6510 ISA DMA channel (ignored for some cards)");
 
-int init_module(void)
+int __init init_module(void)
 {
        dev_ni65 = ni65_probe(-1);
        return IS_ERR(dev_ni65) ? PTR_ERR(dev_ni65) : 0;
index 9bae77c..4122bb4 100644 (file)
@@ -345,6 +345,7 @@ typedef struct local_info_t {
     void __iomem *dingo_ccr; /* only used for CEM56 cards */
     unsigned last_ptr_value; /* last packets transmitted value */
     const char *manf_str;
+    struct work_struct tx_timeout_task;
 } local_info_t;
 
 /****************
@@ -352,6 +353,7 @@ typedef struct local_info_t {
  */
 static int do_start_xmit(struct sk_buff *skb, struct net_device *dev);
 static void do_tx_timeout(struct net_device *dev);
+static void xirc2ps_tx_timeout_task(void *data);
 static struct net_device_stats *do_get_stats(struct net_device *dev);
 static void set_addresses(struct net_device *dev);
 static void set_multicast_list(struct net_device *dev);
@@ -589,6 +591,7 @@ xirc2ps_probe(struct pcmcia_device *link)
 #ifdef HAVE_TX_TIMEOUT
     dev->tx_timeout = do_tx_timeout;
     dev->watchdog_timeo = TX_TIMEOUT;
+    INIT_WORK(&local->tx_timeout_task, xirc2ps_tx_timeout_task, dev);
 #endif
 
     return xirc2ps_config(link);
@@ -1341,17 +1344,24 @@ xirc2ps_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 /*====================================================================*/
 
 static void
-do_tx_timeout(struct net_device *dev)
+xirc2ps_tx_timeout_task(void *data)
 {
-    local_info_t *lp = netdev_priv(dev);
-    printk(KERN_NOTICE "%s: transmit timed out\n", dev->name);
-    lp->stats.tx_errors++;
+    struct net_device *dev = data;
     /* reset the card */
     do_reset(dev,1);
     dev->trans_start = jiffies;
     netif_wake_queue(dev);
 }
 
+static void
+do_tx_timeout(struct net_device *dev)
+{
+    local_info_t *lp = netdev_priv(dev);
+    lp->stats.tx_errors++;
+    printk(KERN_NOTICE "%s: transmit timed out\n", dev->name);
+    schedule_work(&lp->tx_timeout_task);
+}
+
 static int
 do_start_xmit(struct sk_buff *skb, struct net_device *dev)
 {
index 4daafe3..d50bcb8 100644 (file)
@@ -202,6 +202,8 @@ static int homepna[MAX_UNITS];
 #define CSR15          15
 #define PCNET32_MC_FILTER      8
 
+#define PCNET32_79C970A        0x2621
+
 /* The PCNET32 Rx and Tx ring descriptors. */
 struct pcnet32_rx_head {
        u32     base;
@@ -289,6 +291,7 @@ struct pcnet32_private {
 
        /* each bit indicates an available PHY */
        u32                     phymask;
+       unsigned short          chip_version;   /* which variant this is */
 };
 
 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
@@ -724,9 +727,11 @@ static u32 pcnet32_get_link(struct net_device *dev)
        spin_lock_irqsave(&lp->lock, flags);
        if (lp->mii) {
                r = mii_link_ok(&lp->mii_if);
-       } else {
+       } else if (lp->chip_version >= PCNET32_79C970A) {
                ulong ioaddr = dev->base_addr;  /* card base I/O address */
                r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
+       } else {        /* can not detect link on really old chips */
+               r = 1;
        }
        spin_unlock_irqrestore(&lp->lock, flags);
 
@@ -1091,6 +1096,10 @@ static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
        ulong ioaddr = dev->base_addr;
        int ticks;
 
+       /* really old chips have to be stopped. */
+       if (lp->chip_version < PCNET32_79C970A)
+               return 0;
+
        /* set SUSPEND (SPND) - CSR5 bit 0 */
        csr5 = a->read_csr(ioaddr, CSR5);
        a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
@@ -1529,6 +1538,7 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
        lp->mii_if.reg_num_mask = 0x1f;
        lp->dxsuflo = dxsuflo;
        lp->mii = mii;
+       lp->chip_version = chip_version;
        lp->msg_enable = pcnet32_debug;
        if ((cards_found >= MAX_UNITS)
            || (options[cards_found] > sizeof(options_mapping)))
@@ -1839,10 +1849,7 @@ static int pcnet32_open(struct net_device *dev)
                                val |= 2;
                } else if (lp->options & PCNET32_PORT_ASEL) {
                        /* workaround of xSeries250, turn on for 79C975 only */
-                       i = ((lp->a.read_csr(ioaddr, 88) |
-                             (lp->a.
-                              read_csr(ioaddr, 89) << 16)) >> 12) & 0xffff;
-                       if (i == 0x2627)
+                       if (lp->chip_version == 0x2627)
                                val |= 3;
                }
                lp->a.write_bcr(ioaddr, 9, val);
@@ -1986,9 +1993,11 @@ static int pcnet32_open(struct net_device *dev)
 
        netif_start_queue(dev);
 
-       /* Print the link status and start the watchdog */
-       pcnet32_check_media(dev, 1);
-       mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
+       if (lp->chip_version >= PCNET32_79C970A) {
+               /* Print the link status and start the watchdog */
+               pcnet32_check_media(dev, 1);
+               mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
+       }
 
        i = 0;
        while (i++ < 100)
index 2ba6d3a..b79ec0d 100644 (file)
@@ -56,5 +56,22 @@ config SMSC_PHY
        ---help---
          Currently supports the LAN83C185 PHY
 
+config FIXED_PHY
+       tristate "Drivers for PHY emulation on fixed speed/link"
+       depends on PHYLIB
+       ---help---
+         Adds the driver to PHY layer to cover the boards that do not have any PHY bound,
+         but with the ability to manipulate with speed/link in software. The relavant MII
+         speed/duplex parameters could be effectively handled in user-specified  fuction.
+         Currently tested with mpc866ads.
+
+config FIXED_MII_10_FDX
+       bool "Emulation for 10M Fdx fixed PHY behavior"
+       depends on FIXED_PHY
+
+config FIXED_MII_100_FDX
+       bool "Emulation for 100M Fdx fixed PHY behavior"
+       depends on FIXED_PHY
+
 endmenu
 
index a00e619..320f832 100644 (file)
@@ -10,3 +10,4 @@ obj-$(CONFIG_LXT_PHY)         += lxt.o
 obj-$(CONFIG_QSEMI_PHY)                += qsemi.o
 obj-$(CONFIG_SMSC_PHY)         += smsc.o
 obj-$(CONFIG_VITESSE_PHY)      += vitesse.o
+obj-$(CONFIG_FIXED_PHY)                += fixed.o
diff --git a/drivers/net/phy/fixed.c b/drivers/net/phy/fixed.c
new file mode 100644 (file)
index 0000000..341036d
--- /dev/null
@@ -0,0 +1,358 @@
+/*
+ * drivers/net/phy/fixed.c
+ *
+ * Driver for fixed PHYs, when transceiver is able to operate in one fixed mode.
+ *
+ * Author: Vitaly Bordug
+ *
+ * Copyright (c) 2006 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/string.h>
+#include <linux/errno.h>
+#include <linux/unistd.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/spinlock.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/mii.h>
+#include <linux/ethtool.h>
+#include <linux/phy.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+
+#define MII_REGS_NUM   7
+
+/*
+    The idea is to emulate normal phy behavior by responding with
+    pre-defined values to mii BMCR read, so that read_status hook could
+    take all the needed info.
+*/
+
+struct fixed_phy_status {
+       u8      link;
+       u16     speed;
+       u8      duplex;
+};
+
+/*-----------------------------------------------------------------------------
+ *  Private information hoder for mii_bus
+ *-----------------------------------------------------------------------------*/
+struct fixed_info {
+       u16 *regs;
+       u8 regs_num;
+       struct fixed_phy_status phy_status;
+       struct phy_device *phydev; /* pointer to the container */
+       /* link & speed cb */
+       int(*link_update)(struct net_device*, struct fixed_phy_status*);
+
+};
+
+/*-----------------------------------------------------------------------------
+ *  If something weird is required to be done with link/speed,
+ * network driver is able to assign a function to implement this.
+ * May be useful for PHY's that need to be software-driven.
+ *-----------------------------------------------------------------------------*/
+int fixed_mdio_set_link_update(struct phy_device* phydev,
+               int(*link_update)(struct net_device*, struct fixed_phy_status*))
+{
+       struct fixed_info *fixed;
+
+       if(link_update == NULL)
+               return -EINVAL;
+
+       if(phydev) {
+               if(phydev->bus) {
+                       fixed = phydev->bus->priv;
+                       fixed->link_update = link_update;
+                       return 0;
+               }
+       }
+       return -EINVAL;
+}
+EXPORT_SYMBOL(fixed_mdio_set_link_update);
+
+/*-----------------------------------------------------------------------------
+ *  This is used for updating internal mii regs from the status
+ *-----------------------------------------------------------------------------*/
+static int fixed_mdio_update_regs(struct fixed_info *fixed)
+{
+       u16 *regs = fixed->regs;
+       u16 bmsr = 0;
+       u16 bmcr = 0;
+
+       if(!regs) {
+               printk(KERN_ERR "%s: regs not set up", __FUNCTION__);
+               return -EINVAL;
+       }
+
+       if(fixed->phy_status.link)
+               bmsr |= BMSR_LSTATUS;
+
+       if(fixed->phy_status.duplex) {
+               bmcr |= BMCR_FULLDPLX;
+
+               switch ( fixed->phy_status.speed ) {
+               case 100:
+                       bmsr |= BMSR_100FULL;
+                       bmcr |= BMCR_SPEED100;
+               break;
+
+               case 10:
+                       bmsr |= BMSR_10FULL;
+               break;
+               }
+       } else {
+               switch ( fixed->phy_status.speed ) {
+               case 100:
+                       bmsr |= BMSR_100HALF;
+                       bmcr |= BMCR_SPEED100;
+               break;
+
+               case 10:
+                       bmsr |= BMSR_100HALF;
+               break;
+               }
+       }
+
+       regs[MII_BMCR] =  bmcr;
+       regs[MII_BMSR] =  bmsr | 0x800; /*we are always capable of 10 hdx*/
+
+       return 0;
+}
+
+static int fixed_mii_read(struct mii_bus *bus, int phy_id, int location)
+{
+       struct fixed_info *fixed = bus->priv;
+
+       /* if user has registered link update callback, use it */
+       if(fixed->phydev)
+               if(fixed->phydev->attached_dev) {
+                       if(fixed->link_update) {
+                               fixed->link_update(fixed->phydev->attached_dev,
+                                               &fixed->phy_status);
+                               fixed_mdio_update_regs(fixed);
+                       }
+       }
+
+       if ((unsigned int)location >= fixed->regs_num)
+               return -1;
+       return fixed->regs[location];
+}
+
+static int fixed_mii_write(struct mii_bus *bus, int phy_id, int location, u16 val)
+{
+       /* do nothing for now*/
+       return 0;
+}
+
+static int fixed_mii_reset(struct mii_bus *bus)
+{
+       /*nothing here - no way/need to reset it*/
+       return 0;
+}
+
+static int fixed_config_aneg(struct phy_device *phydev)
+{
+       /* :TODO:03/13/2006 09:45:37 PM::
+        The full autoneg funcionality can be emulated,
+        but no need to have anything here for now
+        */
+       return 0;
+}
+
+/*-----------------------------------------------------------------------------
+ * the manual bind will do the magic - with phy_id_mask == 0
+ * match will never return true...
+ *-----------------------------------------------------------------------------*/
+static struct phy_driver fixed_mdio_driver = {
+       .name           = "Fixed PHY",
+       .features       = PHY_BASIC_FEATURES,
+       .config_aneg    = fixed_config_aneg,
+       .read_status    = genphy_read_status,
+       .driver         = { .owner = THIS_MODULE,},
+};
+
+/*-----------------------------------------------------------------------------
+ *  This func is used to create all the necessary stuff, bind
+ * the fixed phy driver and register all it on the mdio_bus_type.
+ * speed is either 10 or 100, duplex is boolean.
+ * number is used to create multiple fixed PHYs, so that several devices can
+ * utilize them simultaneously.
+ *-----------------------------------------------------------------------------*/
+static int fixed_mdio_register_device(int number, int speed, int duplex)
+{
+       struct mii_bus *new_bus;
+       struct fixed_info *fixed;
+       struct phy_device *phydev;
+       int err = 0;
+
+       struct device* dev = kzalloc(sizeof(struct device), GFP_KERNEL);
+
+       if (NULL == dev)
+               return -ENOMEM;
+
+       new_bus = kzalloc(sizeof(struct mii_bus), GFP_KERNEL);
+
+       if (NULL == new_bus) {
+               kfree(dev);
+               return -ENOMEM;
+       }
+       fixed = kzalloc(sizeof(struct fixed_info), GFP_KERNEL);
+
+       if (NULL == fixed) {
+               kfree(dev);
+               kfree(new_bus);
+               return -ENOMEM;
+       }
+
+       fixed->regs = kzalloc(MII_REGS_NUM*sizeof(int), GFP_KERNEL);
+       fixed->regs_num = MII_REGS_NUM;
+       fixed->phy_status.speed = speed;
+       fixed->phy_status.duplex = duplex;
+       fixed->phy_status.link = 1;
+
+       new_bus->name = "Fixed MII Bus",
+       new_bus->read = &fixed_mii_read,
+       new_bus->write = &fixed_mii_write,
+       new_bus->reset = &fixed_mii_reset,
+
+       /*set up workspace*/
+       fixed_mdio_update_regs(fixed);
+       new_bus->priv = fixed;
+
+       new_bus->dev = dev;
+       dev_set_drvdata(dev, new_bus);
+
+       /* create phy_device and register it on the mdio bus */
+       phydev = phy_device_create(new_bus, 0, 0);
+
+       /*
+        Put the phydev pointer into the fixed pack so that bus read/write code could
+        be able to access for instance attached netdev. Well it doesn't have to do
+        so, only in case of utilizing user-specified link-update...
+        */
+       fixed->phydev = phydev;
+
+       if(NULL == phydev) {
+               err = -ENOMEM;
+               goto device_create_fail;
+       }
+
+       phydev->irq = -1;
+       phydev->dev.bus = &mdio_bus_type;
+
+       if(number)
+               snprintf(phydev->dev.bus_id, BUS_ID_SIZE,
+                               "fixed_%d@%d:%d", number, speed, duplex);
+       else
+               snprintf(phydev->dev.bus_id, BUS_ID_SIZE,
+                               "fixed@%d:%d", speed, duplex);
+       phydev->bus = new_bus;
+
+       err = device_register(&phydev->dev);
+       if(err) {
+               printk(KERN_ERR "Phy %s failed to register\n",
+                               phydev->dev.bus_id);
+               goto bus_register_fail;
+       }
+
+       /*
+          the mdio bus has phy_id match... In order not to do it
+          artificially, we are binding the driver here by hand;
+          it will be the same for all the fixed phys anyway.
+        */
+       down_write(&phydev->dev.bus->subsys.rwsem);
+
+       phydev->dev.driver = &fixed_mdio_driver.driver;
+
+       err = phydev->dev.driver->probe(&phydev->dev);
+       if(err < 0) {
+               printk(KERN_ERR "Phy %s: problems with fixed driver\n",phydev->dev.bus_id);
+               up_write(&phydev->dev.bus->subsys.rwsem);
+               goto probe_fail;
+       }
+
+       device_bind_driver(&phydev->dev);
+       up_write(&phydev->dev.bus->subsys.rwsem);
+
+       return 0;
+
+probe_fail:
+       device_unregister(&phydev->dev);
+bus_register_fail:
+       kfree(phydev);
+device_create_fail:
+       kfree(dev);
+       kfree(new_bus);
+       kfree(fixed);
+
+       return err;
+}
+
+
+MODULE_DESCRIPTION("Fixed PHY device & driver for PAL");
+MODULE_AUTHOR("Vitaly Bordug");
+MODULE_LICENSE("GPL");
+
+static int __init fixed_init(void)
+{
+       int ret;
+       int duplex = 0;
+
+       /* register on the bus... Not expected to be matched with anything there... */
+       phy_driver_register(&fixed_mdio_driver);
+
+       /* So let the fun begin...
+          We will create several mdio devices here, and will bound the upper
+          driver to them.
+
+          Then the external software can lookup the phy bus by searching
+          fixed@speed:duplex, e.g. fixed@100:1, to be connected to the
+          virtual 100M Fdx phy.
+
+          In case several virtual PHYs required, the bus_id will be in form
+          fixed_<num>@<speed>:<duplex>, which make it able even to define
+          driver-specific link control callback, if for instance PHY is completely
+          SW-driven.
+
+       */
+
+#ifdef CONFIG_FIXED_MII_DUPLEX
+       duplex = 1;
+#endif
+
+#ifdef CONFIG_FIXED_MII_100_FDX
+       fixed_mdio_register_device(0, 100, 1);
+#endif
+
+#ifdef CONFIX_FIXED_MII_10_FDX
+       fixed_mdio_register_device(0, 10, 1);
+#endif
+       return 0;
+}
+
+static void __exit fixed_exit(void)
+{
+       phy_driver_unregister(&fixed_mdio_driver);
+       /* :WARNING:02/18/2006 04:32:40 AM:: Cleanup all the created stuff */
+}
+
+module_init(fixed_init);
+module_exit(fixed_exit);
index 1dde390..cf6660c 100644 (file)
@@ -159,6 +159,7 @@ struct bus_type mdio_bus_type = {
        .suspend        = mdio_bus_suspend,
        .resume         = mdio_bus_resume,
 };
+EXPORT_SYMBOL(mdio_bus_type);
 
 int __init mdio_bus_init(void)
 {
index 1bc1e03..2d1ecfd 100644 (file)
@@ -45,6 +45,35 @@ static struct phy_driver genphy_driver;
 extern int mdio_bus_init(void);
 extern void mdio_bus_exit(void);
 
+struct phy_device* phy_device_create(struct mii_bus *bus, int addr, int phy_id)
+{
+       struct phy_device *dev;
+       /* We allocate the device, and initialize the
+        * default values */
+       dev = kcalloc(1, sizeof(*dev), GFP_KERNEL);
+
+       if (NULL == dev)
+               return (struct phy_device*) PTR_ERR((void*)-ENOMEM);
+
+       dev->speed = 0;
+       dev->duplex = -1;
+       dev->pause = dev->asym_pause = 0;
+       dev->link = 1;
+
+       dev->autoneg = AUTONEG_ENABLE;
+
+       dev->addr = addr;
+       dev->phy_id = phy_id;
+       dev->bus = bus;
+
+       dev->state = PHY_DOWN;
+
+       spin_lock_init(&dev->lock);
+
+       return dev;
+}
+EXPORT_SYMBOL(phy_device_create);
+
 /* get_phy_device
  *
  * description: Reads the ID registers of the PHY at addr on the
@@ -78,27 +107,7 @@ struct phy_device * get_phy_device(struct mii_bus *bus, int addr)
        if (0xffffffff == phy_id)
                return NULL;
 
-       /* Otherwise, we allocate the device, and initialize the
-        * default values */
-       dev = kcalloc(1, sizeof(*dev), GFP_KERNEL);
-
-       if (NULL == dev)
-               return ERR_PTR(-ENOMEM);
-
-       dev->speed = 0;
-       dev->duplex = -1;
-       dev->pause = dev->asym_pause = 0;
-       dev->link = 1;
-
-       dev->autoneg = AUTONEG_ENABLE;
-
-       dev->addr = addr;
-       dev->phy_id = phy_id;
-       dev->bus = bus;
-
-       dev->state = PHY_DOWN;
-
-       spin_lock_init(&dev->lock);
+       dev = phy_device_create(bus, addr, phy_id);
 
        return dev;
 }
index 132ed32..e72e0e0 100644 (file)
@@ -71,6 +71,7 @@
 #include <asm/uaccess.h>
 #include <asm/io.h>
 #include <asm/div64.h>
+#include <asm/irq.h>
 
 /* local include */
 #include "s2io.h"
index efd0f23..01392bc 100644 (file)
@@ -742,7 +742,7 @@ module_param(irq, int, 0);
 MODULE_PARM_DESC(io, "SEEQ 8005 I/O base address");
 MODULE_PARM_DESC(irq, "SEEQ 8005 IRQ number");
 
-int init_module(void)
+int __init init_module(void)
 {
        dev_seeq = seeq8005_probe(-1);
        if (IS_ERR(dev_seeq))
index 7de9a07..ad878df 100644 (file)
@@ -2211,6 +2211,7 @@ static int skge_up(struct net_device *dev)
        skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
        skge_led(skge, LED_MODE_ON);
 
+       netif_poll_enable(dev);
        return 0;
 
  free_rx_ring:
@@ -2279,6 +2280,7 @@ static int skge_down(struct net_device *dev)
 
        skge_led(skge, LED_MODE_OFF);
 
+       netif_poll_disable(dev);
        skge_tx_clean(skge);
        skge_rx_clean(skge);
 
index de91609..933e87f 100644 (file)
@@ -233,6 +233,8 @@ static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
                        if (hw->ports > 1)
                                reg1 |= PCI_Y2_PHY2_COMA;
                }
+               sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
+               udelay(100);
 
                if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
                        sky2_pci_write32(hw, PCI_DEV_REG3, 0);
@@ -242,9 +244,6 @@ static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
                        sky2_pci_write32(hw, PCI_DEV_REG5, 0);
                }
 
-               sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
-               udelay(100);
-
                break;
 
        case PCI_D3hot:
index d37bd86..0b15290 100644 (file)
@@ -1092,6 +1092,7 @@ static irqreturn_t smc911x_interrupt(int irq, void *dev_id, struct pt_regs *regs
        /* Spurious interrupt check */
        if ((SMC_GET_IRQ_CFG() & (INT_CFG_IRQ_INT_ | INT_CFG_IRQ_EN_)) !=
                (INT_CFG_IRQ_INT_ | INT_CFG_IRQ_EN_)) {
+               spin_unlock_irqrestore(&lp->lock, flags);
                return IRQ_NONE;
        }
 
index 3d8dcb6..cf62373 100644 (file)
@@ -321,12 +321,12 @@ static void smc_reset(struct net_device *dev)
        DBG(2, "%s: %s\n", dev->name, __FUNCTION__);
 
        /* Disable all interrupts, block TX tasklet */
-       spin_lock(&lp->lock);
+       spin_lock_irq(&lp->lock);
        SMC_SELECT_BANK(2);
        SMC_SET_INT_MASK(0);
        pending_skb = lp->pending_tx_skb;
        lp->pending_tx_skb = NULL;
-       spin_unlock(&lp->lock);
+       spin_unlock_irq(&lp->lock);
 
        /* free any pending tx skb */
        if (pending_skb) {
@@ -448,12 +448,12 @@ static void smc_shutdown(struct net_device *dev)
        DBG(2, "%s: %s\n", CARDNAME, __FUNCTION__);
 
        /* no more interrupts for me */
-       spin_lock(&lp->lock);
+       spin_lock_irq(&lp->lock);
        SMC_SELECT_BANK(2);
        SMC_SET_INT_MASK(0);
        pending_skb = lp->pending_tx_skb;
        lp->pending_tx_skb = NULL;
-       spin_unlock(&lp->lock);
+       spin_unlock_irq(&lp->lock);
        if (pending_skb)
                dev_kfree_skb(pending_skb);
 
index 4ec4b4d..7aa7fba 100644 (file)
 #define SMC_CAN_USE_32BIT      0
 #define SMC_IO_SHIFT           0
 #define SMC_NOWAIT             1
-#define SMC_USE_PXA_DMA                1
 
-#define SMC_inb(a, r)          readb((a) + (r))
 #define SMC_inw(a, r)          readw((a) + (r))
-#define SMC_inl(a, r)          readl((a) + (r))
-#define SMC_outb(v, a, r)      writeb(v, (a) + (r))
 #define SMC_outw(v, a, r)      writew(v, (a) + (r))
-#define SMC_outl(v, a, r)      writel(v, (a) + (r))
 #define SMC_insw(a, r, p, l)   readsw((a) + (r), p, l)
 #define SMC_outsw(a, r, p, l)  writesw((a) + (r), p, l)
 
@@ -189,16 +184,10 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg)
 #define SMC_IO_SHIFT           0
 #define SMC_NOWAIT             1
 
-#define SMC_inb(a, r)          readb((a) + (r))
-#define SMC_outb(v, a, r)      writeb(v, (a) + (r))
 #define SMC_inw(a, r)          readw((a) + (r))
 #define SMC_outw(v, a, r)      writew(v, (a) + (r))
 #define SMC_insw(a, r, p, l)   readsw((a) + (r), p, l)
 #define SMC_outsw(a, r, p, l)  writesw((a) + (r), p, l)
-#define SMC_inl(a, r)          readl((a) + (r))
-#define SMC_outl(v, a, r)      writel(v, (a) + (r))
-#define SMC_insl(a, r, p, l)   readsl((a) + (r), p, l)
-#define SMC_outsl(a, r, p, l)  writesl((a) + (r), p, l)
 
 #include <asm/mach-types.h>
 #include <asm/arch/cpu.h>
@@ -372,6 +361,24 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r,
 
 #define SMC_IRQ_FLAGS          (0)
 
+#elif  defined(CONFIG_ARCH_VERSATILE)
+
+#define SMC_CAN_USE_8BIT       1
+#define SMC_CAN_USE_16BIT      1
+#define SMC_CAN_USE_32BIT      1
+#define SMC_NOWAIT             1
+
+#define SMC_inb(a, r)          readb((a) + (r))
+#define SMC_inw(a, r)          readw((a) + (r))
+#define SMC_inl(a, r)          readl((a) + (r))
+#define SMC_outb(v, a, r)      writeb(v, (a) + (r))
+#define SMC_outw(v, a, r)      writew(v, (a) + (r))
+#define SMC_outl(v, a, r)      writel(v, (a) + (r))
+#define SMC_insl(a, r, p, l)   readsl((a) + (r), p, l)
+#define SMC_outsl(a, r, p, l)  writesl((a) + (r), p, l)
+
+#define SMC_IRQ_FLAGS          (0)
+
 #else
 
 #define SMC_CAN_USE_8BIT       1
index 647f62e..8890721 100644 (file)
@@ -1611,13 +1611,12 @@ spider_net_open(struct net_device *netdev)
        int result;
 
        result = -ENOMEM;
-       if (spider_net_init_chain(card, &card->tx_chain,
-                       card->descr,
-                       PCI_DMA_TODEVICE, tx_descriptors))
+       if (spider_net_init_chain(card, &card->tx_chain, card->descr,
+                       PCI_DMA_TODEVICE, card->tx_desc))
                goto alloc_tx_failed;
        if (spider_net_init_chain(card, &card->rx_chain,
-                       card->descr + tx_descriptors,
-                       PCI_DMA_FROMDEVICE, rx_descriptors))
+                       card->descr + card->rx_desc,
+                       PCI_DMA_FROMDEVICE, card->rx_desc))
                goto alloc_rx_failed;
 
        /* allocate rx skbs */
@@ -2005,6 +2004,9 @@ spider_net_setup_netdev(struct spider_net_card *card)
 
        card->options.rx_csum = SPIDER_NET_RX_CSUM_DEFAULT;
 
+       card->tx_desc = tx_descriptors;
+       card->rx_desc = rx_descriptors;
+
        spider_net_setup_netdev_ops(netdev);
 
        netdev->features = NETIF_F_HW_CSUM | NETIF_F_LLTX;
index f6dcf18..30407cd 100644 (file)
@@ -440,6 +440,9 @@ struct spider_net_card {
        /* for ethtool */
        int msg_enable;
 
+       int rx_desc;
+       int tx_desc;
+
        struct spider_net_descr descr[0];
 };
 
index a5bb0b7..0220922 100644 (file)
@@ -130,6 +130,18 @@ spider_net_ethtool_set_tx_csum(struct net_device *netdev, uint32_t data)
         return 0;
 }
 
+static void
+spider_net_ethtool_get_ringparam(struct net_device *netdev,
+                                struct ethtool_ringparam *ering)
+{
+       struct spider_net_card *card = netdev->priv;
+
+       ering->tx_max_pending = SPIDER_NET_TX_DESCRIPTORS_MAX;
+       ering->tx_pending = card->tx_desc;
+       ering->rx_max_pending = SPIDER_NET_RX_DESCRIPTORS_MAX;
+       ering->rx_pending = card->rx_desc;
+}
+
 struct ethtool_ops spider_net_ethtool_ops = {
        .get_settings           = spider_net_ethtool_get_settings,
        .get_drvinfo            = spider_net_ethtool_get_drvinfo,
@@ -141,5 +153,6 @@ struct ethtool_ops spider_net_ethtool_ops = {
        .set_rx_csum            = spider_net_ethtool_set_rx_csum,
        .get_tx_csum            = spider_net_ethtool_get_tx_csum,
        .set_tx_csum            = spider_net_ethtool_set_tx_csum,
+       .get_ringparam          = spider_net_ethtool_get_ringparam,
 };
 
index ac17377..698568e 100644 (file)
@@ -107,7 +107,7 @@ static char *media[MAX_UNITS];
 #endif
 
 /* These identify the driver base version and may not be removed. */
-static char version[] __devinitdata =
+static char version[] =
 KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE "  Written by Donald Becker\n"
 KERN_INFO "  http://www.scyld.com/network/sundance.html\n";
 
index 9f49156..4470025 100644 (file)
@@ -140,7 +140,7 @@ in the event that chatty debug messages are desired - jjs 12/30/98 */
 
 /* version and credits */
 #ifndef PCMCIA
-static char version[] __initdata =
+static char version[] __devinitdata =
     "\nibmtr.c: v1.3.57   8/ 7/94 Peter De Schrijver and Mark Swanson\n"
     "         v2.1.125 10/20/98 Paul Norton    <pnorton@ieee.org>\n"
     "         v2.2.0   12/30/98 Joel Sloan     <jjs@c-me.com>\n"
@@ -216,7 +216,7 @@ static int __devinitdata turbo_irq[IBMTR_MAX_ADAPTERS] = {0};
 static int __devinitdata turbo_searched = 0;
 
 #ifndef PCMCIA
-static __u32 ibmtr_mem_base __initdata = 0xd0000;
+static __u32 ibmtr_mem_base __devinitdata = 0xd0000;
 #endif
 
 static void __devinit PrtChanID(char *pcid, short stride)
index cd2e025..85a7f79 100644 (file)
@@ -5666,7 +5666,7 @@ module_param_array(io, int, NULL, 0);
 module_param_array(irq, int, NULL, 0);
 module_param(ringspeed, int, 0);
 
-static struct net_device *setup_card(int n)
+static struct net_device * __init setup_card(int n)
 {
        struct net_device *dev = alloc_trdev(sizeof(struct net_local));
        int err;
@@ -5696,9 +5696,8 @@ out:
        free_netdev(dev);
        return ERR_PTR(err);
 }
-                       
 
-int init_module(void)
+int __init init_module(void)
 {
         int i, found = 0;
        struct net_device *dev;
index 7f41481..eba9083 100644 (file)
@@ -138,7 +138,7 @@ static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
 #include <asm/irq.h>
 
 /* These identify the driver base version and may not be removed. */
-static char version[] __devinitdata =
+static char version[] =
 KERN_INFO DRV_NAME ".c:v" DRV_VERSION " (2.4 port) " DRV_RELDATE "  Donald Becker <becker@scyld.com>\n"
 KERN_INFO "  http://www.scyld.com/network/drivers.html\n";
 
index f874e4f..cf43390 100644 (file)
@@ -1264,8 +1264,7 @@ static void investigate_write_descriptor(struct net_device *dev, struct xircom_p
 
 static int __init xircom_init(void)
 {
-       pci_register_driver(&xircom_ops);
-       return 0;
+       return pci_register_driver(&xircom_ops);
 }
 
 static void __exit xircom_exit(void)
diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c
new file mode 100644 (file)
index 0000000..47f49ef
--- /dev/null
@@ -0,0 +1,4278 @@
+/*
+ * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
+ *
+ * Author: Shlomi Gridish <gridish@freescale.com>
+ *
+ * Description:
+ * QE UCC Gigabit Ethernet Driver
+ *
+ * Changelog:
+ * Jul 6, 2006 Li Yang <LeoLi@freescale.com>
+ * - Rearrange code and style fixes
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/slab.h>
+#include <linux/stddef.h>
+#include <linux/interrupt.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/spinlock.h>
+#include <linux/mm.h>
+#include <linux/ethtool.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/fsl_devices.h>
+#include <linux/ethtool.h>
+#include <linux/platform_device.h>
+#include <linux/mii.h>
+
+#include <asm/uaccess.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+#include <asm/immap_qe.h>
+#include <asm/qe.h>
+#include <asm/ucc.h>
+#include <asm/ucc_fast.h>
+
+#include "ucc_geth.h"
+#include "ucc_geth_phy.h"
+
+#undef DEBUG
+
+#define DRV_DESC "QE UCC Gigabit Ethernet Controller version:June 20, 2006"
+#define DRV_NAME "ucc_geth"
+
+#define ugeth_printk(level, format, arg...)  \
+        printk(level format "\n", ## arg)
+
+#define ugeth_dbg(format, arg...)            \
+        ugeth_printk(KERN_DEBUG , format , ## arg)
+#define ugeth_err(format, arg...)            \
+        ugeth_printk(KERN_ERR , format , ## arg)
+#define ugeth_info(format, arg...)           \
+        ugeth_printk(KERN_INFO , format , ## arg)
+#define ugeth_warn(format, arg...)           \
+        ugeth_printk(KERN_WARNING , format , ## arg)
+
+#ifdef UGETH_VERBOSE_DEBUG
+#define ugeth_vdbg ugeth_dbg
+#else
+#define ugeth_vdbg(fmt, args...) do { } while (0)
+#endif                         /* UGETH_VERBOSE_DEBUG */
+
+static DEFINE_SPINLOCK(ugeth_lock);
+
+static ucc_geth_info_t ugeth_primary_info = {
+       .uf_info = {
+                   .bd_mem_part = MEM_PART_SYSTEM,
+                   .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
+                   .max_rx_buf_length = 1536,
+/* FIXME: should be changed in run time for 1G and 100M */
+#ifdef CONFIG_UGETH_HAS_GIGA
+                   .urfs = UCC_GETH_URFS_GIGA_INIT,
+                   .urfet = UCC_GETH_URFET_GIGA_INIT,
+                   .urfset = UCC_GETH_URFSET_GIGA_INIT,
+                   .utfs = UCC_GETH_UTFS_GIGA_INIT,
+                   .utfet = UCC_GETH_UTFET_GIGA_INIT,
+                   .utftt = UCC_GETH_UTFTT_GIGA_INIT,
+#else
+                   .urfs = UCC_GETH_URFS_INIT,
+                   .urfet = UCC_GETH_URFET_INIT,
+                   .urfset = UCC_GETH_URFSET_INIT,
+                   .utfs = UCC_GETH_UTFS_INIT,
+                   .utfet = UCC_GETH_UTFET_INIT,
+                   .utftt = UCC_GETH_UTFTT_INIT,
+#endif
+                   .ufpt = 256,
+                   .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
+                   .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
+                   .tenc = UCC_FAST_TX_ENCODING_NRZ,
+                   .renc = UCC_FAST_RX_ENCODING_NRZ,
+                   .tcrc = UCC_FAST_16_BIT_CRC,
+                   .synl = UCC_FAST_SYNC_LEN_NOT_USED,
+                   },
+       .numQueuesTx = 1,
+       .numQueuesRx = 1,
+       .extendedFilteringChainPointer = ((uint32_t) NULL),
+       .typeorlen = 3072 /*1536 */ ,
+       .nonBackToBackIfgPart1 = 0x40,
+       .nonBackToBackIfgPart2 = 0x60,
+       .miminumInterFrameGapEnforcement = 0x50,
+       .backToBackInterFrameGap = 0x60,
+       .mblinterval = 128,
+       .nortsrbytetime = 5,
+       .fracsiz = 1,
+       .strictpriorityq = 0xff,
+       .altBebTruncation = 0xa,
+       .excessDefer = 1,
+       .maxRetransmission = 0xf,
+       .collisionWindow = 0x37,
+       .receiveFlowControl = 1,
+       .maxGroupAddrInHash = 4,
+       .maxIndAddrInHash = 4,
+       .prel = 7,
+       .maxFrameLength = 1518,
+       .minFrameLength = 64,
+       .maxD1Length = 1520,
+       .maxD2Length = 1520,
+       .vlantype = 0x8100,
+       .ecamptr = ((uint32_t) NULL),
+       .eventRegMask = UCCE_OTHER,
+       .pausePeriod = 0xf000,
+       .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
+       .bdRingLenTx = {
+                       TX_BD_RING_LEN,
+                       TX_BD_RING_LEN,
+                       TX_BD_RING_LEN,
+                       TX_BD_RING_LEN,
+                       TX_BD_RING_LEN,
+                       TX_BD_RING_LEN,
+                       TX_BD_RING_LEN,
+                       TX_BD_RING_LEN},
+
+       .bdRingLenRx = {
+                       RX_BD_RING_LEN,
+                       RX_BD_RING_LEN,
+                       RX_BD_RING_LEN,
+                       RX_BD_RING_LEN,
+                       RX_BD_RING_LEN,
+                       RX_BD_RING_LEN,
+                       RX_BD_RING_LEN,
+                       RX_BD_RING_LEN},
+
+       .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
+       .largestexternallookupkeysize =
+           QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
+       .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_NONE,
+       .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
+       .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
+       .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
+       .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
+       .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
+       .numThreadsTx = UCC_GETH_NUM_OF_THREADS_4,
+       .numThreadsRx = UCC_GETH_NUM_OF_THREADS_4,
+       .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+       .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+};
+
+static ucc_geth_info_t ugeth_info[8];
+
+#ifdef DEBUG
+static void mem_disp(u8 *addr, int size)
+{
+       u8 *i;
+       int size16Aling = (size >> 4) << 4;
+       int size4Aling = (size >> 2) << 2;
+       int notAlign = 0;
+       if (size % 16)
+               notAlign = 1;
+
+       for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
+               printk("0x%08x: %08x %08x %08x %08x\r\n",
+                      (u32) i,
+                      *((u32 *) (i)),
+                      *((u32 *) (i + 4)),
+                      *((u32 *) (i + 8)), *((u32 *) (i + 12)));
+       if (notAlign == 1)
+               printk("0x%08x: ", (u32) i);
+       for (; (u32) i < (u32) addr + size4Aling; i += 4)
+               printk("%08x ", *((u32 *) (i)));
+       for (; (u32) i < (u32) addr + size; i++)
+               printk("%02x", *((u8 *) (i)));
+       if (notAlign == 1)
+               printk("\r\n");
+}
+#endif /* DEBUG */
+
+#ifdef CONFIG_UGETH_FILTERING
+static void enqueue(struct list_head *node, struct list_head *lh)
+{
+       unsigned long flags;
+
+       spin_lock_irqsave(ugeth_lock, flags);
+       list_add_tail(node, lh);
+       spin_unlock_irqrestore(ugeth_lock, flags);
+}
+#endif /* CONFIG_UGETH_FILTERING */
+
+static struct list_head *dequeue(struct list_head *lh)
+{
+       unsigned long flags;
+
+       spin_lock_irqsave(ugeth_lock, flags);
+       if (!list_empty(lh)) {
+               struct list_head *node = lh->next;
+               list_del(node);
+               spin_unlock_irqrestore(ugeth_lock, flags);
+               return node;
+       } else {
+               spin_unlock_irqrestore(ugeth_lock, flags);
+               return NULL;
+       }
+}
+
+static int get_interface_details(enet_interface_e enet_interface,
+                                enet_speed_e *speed,
+                                int *r10m,
+                                int *rmm,
+                                int *rpm,
+                                int *tbi, int *limited_to_full_duplex)
+{
+       /* Analyze enet_interface according to Interface Mode
+       Configuration table */
+       switch (enet_interface) {
+       case ENET_10_MII:
+               *speed = ENET_SPEED_10BT;
+               break;
+       case ENET_10_RMII:
+               *speed = ENET_SPEED_10BT;
+               *r10m = 1;
+               *rmm = 1;
+               break;
+       case ENET_10_RGMII:
+               *speed = ENET_SPEED_10BT;
+               *rpm = 1;
+               *r10m = 1;
+               *limited_to_full_duplex = 1;
+               break;
+       case ENET_100_MII:
+               *speed = ENET_SPEED_100BT;
+               break;
+       case ENET_100_RMII:
+               *speed = ENET_SPEED_100BT;
+               *rmm = 1;
+               break;
+       case ENET_100_RGMII:
+               *speed = ENET_SPEED_100BT;
+               *rpm = 1;
+               *limited_to_full_duplex = 1;
+               break;
+       case ENET_1000_GMII:
+               *speed = ENET_SPEED_1000BT;
+               *limited_to_full_duplex = 1;
+               break;
+       case ENET_1000_RGMII:
+               *speed = ENET_SPEED_1000BT;
+               *rpm = 1;
+               *limited_to_full_duplex = 1;
+               break;
+       case ENET_1000_TBI:
+               *speed = ENET_SPEED_1000BT;
+               *tbi = 1;
+               *limited_to_full_duplex = 1;
+               break;
+       case ENET_1000_RTBI:
+               *speed = ENET_SPEED_1000BT;
+               *rpm = 1;
+               *tbi = 1;
+               *limited_to_full_duplex = 1;
+               break;
+       default:
+               return -EINVAL;
+               break;
+       }
+
+       return 0;
+}
+
+static struct sk_buff *get_new_skb(ucc_geth_private_t *ugeth, u8 *bd)
+{
+       struct sk_buff *skb = NULL;
+
+       skb = dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length +
+                                 UCC_GETH_RX_DATA_BUF_ALIGNMENT);
+
+       if (skb == NULL)
+               return NULL;
+
+       /* We need the data buffer to be aligned properly.  We will reserve
+        * as many bytes as needed to align the data properly
+        */
+       skb_reserve(skb,
+                   UCC_GETH_RX_DATA_BUF_ALIGNMENT -
+                   (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
+                                             1)));
+
+       skb->dev = ugeth->dev;
+
+       BD_BUFFER_SET(bd,
+                     dma_map_single(NULL,
+                                    skb->data,
+                                    ugeth->ug_info->uf_info.max_rx_buf_length +
+                                    UCC_GETH_RX_DATA_BUF_ALIGNMENT,
+                                    DMA_FROM_DEVICE));
+
+       BD_STATUS_AND_LENGTH_SET(bd,
+                                (R_E | R_I |
+                                 (BD_STATUS_AND_LENGTH(bd) & R_W)));
+
+       return skb;
+}
+
+static int rx_bd_buffer_set(ucc_geth_private_t *ugeth, u8 rxQ)
+{
+       u8 *bd;
+       u32 bd_status;
+       struct sk_buff *skb;
+       int i;
+
+       bd = ugeth->p_rx_bd_ring[rxQ];
+       i = 0;
+
+       do {
+               bd_status = BD_STATUS_AND_LENGTH(bd);
+               skb = get_new_skb(ugeth, bd);
+
+               if (!skb)       /* If can not allocate data buffer,
+                               abort. Cleanup will be elsewhere */
+                       return -ENOMEM;
+
+               ugeth->rx_skbuff[rxQ][i] = skb;
+
+               /* advance the BD pointer */
+               bd += UCC_GETH_SIZE_OF_BD;
+               i++;
+       } while (!(bd_status & R_W));
+
+       return 0;
+}
+
+static int fill_init_enet_entries(ucc_geth_private_t *ugeth,
+                                 volatile u32 *p_start,
+                                 u8 num_entries,
+                                 u32 thread_size,
+                                 u32 thread_alignment,
+                                 qe_risc_allocation_e risc,
+                                 int skip_page_for_first_entry)
+{
+       u32 init_enet_offset;
+       u8 i;
+       int snum;
+
+       for (i = 0; i < num_entries; i++) {
+               if ((snum = qe_get_snum()) < 0) {
+                       ugeth_err("fill_init_enet_entries: Can not get SNUM.");
+                       return snum;
+               }
+               if ((i == 0) && skip_page_for_first_entry)
+               /* First entry of Rx does not have page */
+                       init_enet_offset = 0;
+               else {
+                       init_enet_offset =
+                           qe_muram_alloc(thread_size, thread_alignment);
+                       if (IS_MURAM_ERR(init_enet_offset)) {
+                               ugeth_err
+               ("fill_init_enet_entries: Can not allocate DPRAM memory.");
+                               qe_put_snum((u8) snum);
+                               return -ENOMEM;
+                       }
+               }
+               *(p_start++) =
+                   ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
+                   | risc;
+       }
+
+       return 0;
+}
+
+static int return_init_enet_entries(ucc_geth_private_t *ugeth,
+                                   volatile u32 *p_start,
+                                   u8 num_entries,
+                                   qe_risc_allocation_e risc,
+                                   int skip_page_for_first_entry)
+{
+       u32 init_enet_offset;
+       u8 i;
+       int snum;
+
+       for (i = 0; i < num_entries; i++) {
+               /* Check that this entry was actually valid --
+               needed in case failed in allocations */
+               if ((*p_start & ENET_INIT_PARAM_RISC_MASK) == risc) {
+                       snum =
+                           (u32) (*p_start & ENET_INIT_PARAM_SNUM_MASK) >>
+                           ENET_INIT_PARAM_SNUM_SHIFT;
+                       qe_put_snum((u8) snum);
+                       if (!((i == 0) && skip_page_for_first_entry)) {
+                       /* First entry of Rx does not have page */
+                               init_enet_offset =
+                                   (in_be32(p_start) &
+                                    ENET_INIT_PARAM_PTR_MASK);
+                               qe_muram_free(init_enet_offset);
+                       }
+                       *(p_start++) = 0;       /* Just for cosmetics */
+               }
+       }
+
+       return 0;
+}
+
+#ifdef DEBUG
+static int dump_init_enet_entries(ucc_geth_private_t *ugeth,
+                                 volatile u32 *p_start,
+                                 u8 num_entries,
+                                 u32 thread_size,
+                                 qe_risc_allocation_e risc,
+                                 int skip_page_for_first_entry)
+{
+       u32 init_enet_offset;
+       u8 i;
+       int snum;
+
+       for (i = 0; i < num_entries; i++) {
+               /* Check that this entry was actually valid --
+               needed in case failed in allocations */
+               if ((*p_start & ENET_INIT_PARAM_RISC_MASK) == risc) {
+                       snum =
+                           (u32) (*p_start & ENET_INIT_PARAM_SNUM_MASK) >>
+                           ENET_INIT_PARAM_SNUM_SHIFT;
+                       qe_put_snum((u8) snum);
+                       if (!((i == 0) && skip_page_for_first_entry)) {
+                       /* First entry of Rx does not have page */
+                               init_enet_offset =
+                                   (in_be32(p_start) &
+                                    ENET_INIT_PARAM_PTR_MASK);
+                               ugeth_info("Init enet entry %d:", i);
+                               ugeth_info("Base address: 0x%08x",
+                                          (u32)
+                                          qe_muram_addr(init_enet_offset));
+                               mem_disp(qe_muram_addr(init_enet_offset),
+                                        thread_size);
+                       }
+                       p_start++;
+               }
+       }
+
+       return 0;
+}
+#endif
+
+#ifdef CONFIG_UGETH_FILTERING
+static enet_addr_container_t *get_enet_addr_container(void)
+{
+       enet_addr_container_t *enet_addr_cont;
+
+       /* allocate memory */
+       enet_addr_cont = kmalloc(sizeof(enet_addr_container_t), GFP_KERNEL);
+       if (!enet_addr_cont) {
+               ugeth_err("%s: No memory for enet_addr_container_t object.",
+                         __FUNCTION__);
+               return NULL;
+       }
+
+       return enet_addr_cont;
+}
+#endif /* CONFIG_UGETH_FILTERING */
+
+static void put_enet_addr_container(enet_addr_container_t *enet_addr_cont)
+{
+       kfree(enet_addr_cont);
+}
+
+#ifdef CONFIG_UGETH_FILTERING
+static int hw_add_addr_in_paddr(ucc_geth_private_t *ugeth,
+                               enet_addr_t *p_enet_addr, u8 paddr_num)
+{
+       ucc_geth_82xx_address_filtering_pram_t *p_82xx_addr_filt;
+
+       if (!(paddr_num < NUM_OF_PADDRS)) {
+               ugeth_warn("%s: Illagel paddr_num.", __FUNCTION__);
+               return -EINVAL;
+       }
+
+       p_82xx_addr_filt =
+           (ucc_geth_82xx_address_filtering_pram_t *) ugeth->p_rx_glbl_pram->
+           addressfiltering;
+
+       /* Ethernet frames are defined in Little Endian mode,    */
+       /* therefore to insert the address we reverse the bytes. */
+       out_be16(&p_82xx_addr_filt->paddr[paddr_num].h,
+                (u16) (((u16) (((u16) ((*p_enet_addr)[5])) << 8)) |
+                       (u16) (*p_enet_addr)[4]));
+       out_be16(&p_82xx_addr_filt->paddr[paddr_num].m,
+                (u16) (((u16) (((u16) ((*p_enet_addr)[3])) << 8)) |
+                       (u16) (*p_enet_addr)[2]));
+       out_be16(&p_82xx_addr_filt->paddr[paddr_num].l,
+                (u16) (((u16) (((u16) ((*p_enet_addr)[1])) << 8)) |
+                       (u16) (*p_enet_addr)[0]));
+
+       return 0;
+}
+#endif /* CONFIG_UGETH_FILTERING */
+
+static int hw_clear_addr_in_paddr(ucc_geth_private_t *ugeth, u8 paddr_num)
+{
+       ucc_geth_82xx_address_filtering_pram_t *p_82xx_addr_filt;
+
+       if (!(paddr_num < NUM_OF_PADDRS)) {
+               ugeth_warn("%s: Illagel paddr_num.", __FUNCTION__);
+               return -EINVAL;
+       }
+
+       p_82xx_addr_filt =
+           (ucc_geth_82xx_address_filtering_pram_t *) ugeth->p_rx_glbl_pram->
+           addressfiltering;
+
+       /* Writing address ff.ff.ff.ff.ff.ff disables address
+       recognition for this register */
+       out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
+       out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
+       out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
+
+       return 0;
+}
+
+static void hw_add_addr_in_hash(ucc_geth_private_t *ugeth,
+                               enet_addr_t *p_enet_addr)
+{
+       ucc_geth_82xx_address_filtering_pram_t *p_82xx_addr_filt;
+       u32 cecr_subblock;
+
+       p_82xx_addr_filt =
+           (ucc_geth_82xx_address_filtering_pram_t *) ugeth->p_rx_glbl_pram->
+           addressfiltering;
+
+       cecr_subblock =
+           ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
+
+       /* Ethernet frames are defined in Little Endian mode,
+       therefor to insert */
+       /* the address to the hash (Big Endian mode), we reverse the bytes.*/
+       out_be16(&p_82xx_addr_filt->taddr.h,
+                (u16) (((u16) (((u16) ((*p_enet_addr)[5])) << 8)) |
+                       (u16) (*p_enet_addr)[4]));
+       out_be16(&p_82xx_addr_filt->taddr.m,
+                (u16) (((u16) (((u16) ((*p_enet_addr)[3])) << 8)) |
+                       (u16) (*p_enet_addr)[2]));
+       out_be16(&p_82xx_addr_filt->taddr.l,
+                (u16) (((u16) (((u16) ((*p_enet_addr)[1])) << 8)) |
+                       (u16) (*p_enet_addr)[0]));
+
+       qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
+                    (u8) QE_CR_PROTOCOL_ETHERNET, 0);
+}
+
+#ifdef CONFIG_UGETH_MAGIC_PACKET
+static void magic_packet_detection_enable(ucc_geth_private_t *ugeth)
+{
+       ucc_fast_private_t *uccf;
+       ucc_geth_t *ug_regs;
+       u32 maccfg2, uccm;
+
+       uccf = ugeth->uccf;
+       ug_regs = ugeth->ug_regs;
+
+       /* Enable interrupts for magic packet detection */
+       uccm = in_be32(uccf->p_uccm);
+       uccm |= UCCE_MPD;
+       out_be32(uccf->p_uccm, uccm);
+
+       /* Enable magic packet detection */
+       maccfg2 = in_be32(&ug_regs->maccfg2);
+       maccfg2 |= MACCFG2_MPE;
+       out_be32(&ug_regs->maccfg2, maccfg2);
+}
+
+static void magic_packet_detection_disable(ucc_geth_private_t *ugeth)
+{
+       ucc_fast_private_t *uccf;
+       ucc_geth_t *ug_regs;
+       u32 maccfg2, uccm;
+
+       uccf = ugeth->uccf;
+       ug_regs = ugeth->ug_regs;
+
+       /* Disable interrupts for magic packet detection */
+       uccm = in_be32(uccf->p_uccm);
+       uccm &= ~UCCE_MPD;
+       out_be32(uccf->p_uccm, uccm);
+
+       /* Disable magic packet detection */
+       maccfg2 = in_be32(&ug_regs->maccfg2);
+       maccfg2 &= ~MACCFG2_MPE;
+       out_be32(&ug_regs->maccfg2, maccfg2);
+}
+#endif /* MAGIC_PACKET */
+
+static inline int compare_addr(enet_addr_t *addr1, enet_addr_t *addr2)
+{
+       return memcmp(addr1, addr2, ENET_NUM_OCTETS_PER_ADDRESS);
+}
+
+#ifdef DEBUG
+static void get_statistics(ucc_geth_private_t *ugeth,
+                          ucc_geth_tx_firmware_statistics_t *
+                          tx_firmware_statistics,
+                          ucc_geth_rx_firmware_statistics_t *
+                          rx_firmware_statistics,
+                          ucc_geth_hardware_statistics_t *hardware_statistics)
+{
+       ucc_fast_t *uf_regs;
+       ucc_geth_t *ug_regs;
+       ucc_geth_tx_firmware_statistics_pram_t *p_tx_fw_statistics_pram;
+       ucc_geth_rx_firmware_statistics_pram_t *p_rx_fw_statistics_pram;
+
+       ug_regs = ugeth->ug_regs;
+       uf_regs = (ucc_fast_t *) ug_regs;
+       p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
+       p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
+
+       /* Tx firmware only if user handed pointer and driver actually
+       gathers Tx firmware statistics */
+       if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
+               tx_firmware_statistics->sicoltx =
+                   in_be32(&p_tx_fw_statistics_pram->sicoltx);
+               tx_firmware_statistics->mulcoltx =
+                   in_be32(&p_tx_fw_statistics_pram->mulcoltx);
+               tx_firmware_statistics->latecoltxfr =
+                   in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
+               tx_firmware_statistics->frabortduecol =
+                   in_be32(&p_tx_fw_statistics_pram->frabortduecol);
+               tx_firmware_statistics->frlostinmactxer =
+                   in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
+               tx_firmware_statistics->carriersenseertx =
+                   in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
+               tx_firmware_statistics->frtxok =
+                   in_be32(&p_tx_fw_statistics_pram->frtxok);
+               tx_firmware_statistics->txfrexcessivedefer =
+                   in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
+               tx_firmware_statistics->txpkts256 =
+                   in_be32(&p_tx_fw_statistics_pram->txpkts256);
+               tx_firmware_statistics->txpkts512 =
+                   in_be32(&p_tx_fw_statistics_pram->txpkts512);
+               tx_firmware_statistics->txpkts1024 =
+                   in_be32(&p_tx_fw_statistics_pram->txpkts1024);
+               tx_firmware_statistics->txpktsjumbo =
+                   in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
+       }
+
+       /* Rx firmware only if user handed pointer and driver actually
+        * gathers Rx firmware statistics */
+       if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
+               int i;
+               rx_firmware_statistics->frrxfcser =
+                   in_be32(&p_rx_fw_statistics_pram->frrxfcser);
+               rx_firmware_statistics->fraligner =
+                   in_be32(&p_rx_fw_statistics_pram->fraligner);
+               rx_firmware_statistics->inrangelenrxer =
+                   in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
+               rx_firmware_statistics->outrangelenrxer =
+                   in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
+               rx_firmware_statistics->frtoolong =
+                   in_be32(&p_rx_fw_statistics_pram->frtoolong);
+               rx_firmware_statistics->runt =
+                   in_be32(&p_rx_fw_statistics_pram->runt);
+               rx_firmware_statistics->verylongevent =
+                   in_be32(&p_rx_fw_statistics_pram->verylongevent);
+               rx_firmware_statistics->symbolerror =
+                   in_be32(&p_rx_fw_statistics_pram->symbolerror);
+               rx_firmware_statistics->dropbsy =
+                   in_be32(&p_rx_fw_statistics_pram->dropbsy);
+               for (i = 0; i < 0x8; i++)
+                       rx_firmware_statistics->res0[i] =
+                           p_rx_fw_statistics_pram->res0[i];
+               rx_firmware_statistics->mismatchdrop =
+                   in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
+               rx_firmware_statistics->underpkts =
+                   in_be32(&p_rx_fw_statistics_pram->underpkts);
+               rx_firmware_statistics->pkts256 =
+                   in_be32(&p_rx_fw_statistics_pram->pkts256);
+               rx_firmware_statistics->pkts512 =
+                   in_be32(&p_rx_fw_statistics_pram->pkts512);
+               rx_firmware_statistics->pkts1024 =
+                   in_be32(&p_rx_fw_statistics_pram->pkts1024);
+               rx_firmware_statistics->pktsjumbo =
+                   in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
+               rx_firmware_statistics->frlossinmacer =
+                   in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
+               rx_firmware_statistics->pausefr =
+                   in_be32(&p_rx_fw_statistics_pram->pausefr);
+               for (i = 0; i < 0x4; i++)
+                       rx_firmware_statistics->res1[i] =
+                           p_rx_fw_statistics_pram->res1[i];
+               rx_firmware_statistics->removevlan =
+                   in_be32(&p_rx_fw_statistics_pram->removevlan);
+               rx_firmware_statistics->replacevlan =
+                   in_be32(&p_rx_fw_statistics_pram->replacevlan);
+               rx_firmware_statistics->insertvlan =
+                   in_be32(&p_rx_fw_statistics_pram->insertvlan);
+       }
+
+       /* Hardware only if user handed pointer and driver actually
+       gathers hardware statistics */
+       if (hardware_statistics && (in_be32(&uf_regs->upsmr) & UPSMR_HSE)) {
+               hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
+               hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
+               hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
+               hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
+               hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
+               hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
+               hardware_statistics->txok = in_be32(&ug_regs->txok);
+               hardware_statistics->txcf = in_be16(&ug_regs->txcf);
+               hardware_statistics->tmca = in_be32(&ug_regs->tmca);
+               hardware_statistics->tbca = in_be32(&ug_regs->tbca);
+               hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
+               hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
+               hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
+               hardware_statistics->rmca = in_be32(&ug_regs->rmca);
+               hardware_statistics->rbca = in_be32(&ug_regs->rbca);
+       }
+}
+
+static void dump_bds(ucc_geth_private_t *ugeth)
+{
+       int i;
+       int length;
+
+       for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
+               if (ugeth->p_tx_bd_ring[i]) {
+                       length =
+                           (ugeth->ug_info->bdRingLenTx[i] *
+                            UCC_GETH_SIZE_OF_BD);
+                       ugeth_info("TX BDs[%d]", i);
+                       mem_disp(ugeth->p_tx_bd_ring[i], length);
+               }
+       }
+       for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
+               if (ugeth->p_rx_bd_ring[i]) {
+                       length =
+                           (ugeth->ug_info->bdRingLenRx[i] *
+                            UCC_GETH_SIZE_OF_BD);
+                       ugeth_info("RX BDs[%d]", i);
+                       mem_disp(ugeth->p_rx_bd_ring[i], length);
+               }
+       }
+}
+
+static void dump_regs(ucc_geth_private_t *ugeth)
+{
+       int i;
+
+       ugeth_info("UCC%d Geth registers:", ugeth->ug_info->uf_info.ucc_num);
+       ugeth_info("Base address: 0x%08x", (u32) ugeth->ug_regs);
+
+       ugeth_info("maccfg1    : addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->maccfg1,
+                  in_be32(&ugeth->ug_regs->maccfg1));
+       ugeth_info("maccfg2    : addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->maccfg2,
+                  in_be32(&ugeth->ug_regs->maccfg2));
+       ugeth_info("ipgifg     : addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->ipgifg,
+                  in_be32(&ugeth->ug_regs->ipgifg));
+       ugeth_info("hafdup     : addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->hafdup,
+                  in_be32(&ugeth->ug_regs->hafdup));
+       ugeth_info("miimcfg    : addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->miimng.miimcfg,
+                  in_be32(&ugeth->ug_regs->miimng.miimcfg));
+       ugeth_info("miimcom    : addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->miimng.miimcom,
+                  in_be32(&ugeth->ug_regs->miimng.miimcom));
+       ugeth_info("miimadd    : addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->miimng.miimadd,
+                  in_be32(&ugeth->ug_regs->miimng.miimadd));
+       ugeth_info("miimcon    : addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->miimng.miimcon,
+                  in_be32(&ugeth->ug_regs->miimng.miimcon));
+       ugeth_info("miimstat   : addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->miimng.miimstat,
+                  in_be32(&ugeth->ug_regs->miimng.miimstat));
+       ugeth_info("miimmind   : addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->miimng.miimind,
+                  in_be32(&ugeth->ug_regs->miimng.miimind));
+       ugeth_info("ifctl      : addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->ifctl,
+                  in_be32(&ugeth->ug_regs->ifctl));
+       ugeth_info("ifstat     : addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->ifstat,
+                  in_be32(&ugeth->ug_regs->ifstat));
+       ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->macstnaddr1,
+                  in_be32(&ugeth->ug_regs->macstnaddr1));
+       ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->macstnaddr2,
+                  in_be32(&ugeth->ug_regs->macstnaddr2));
+       ugeth_info("uempr      : addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->uempr,
+                  in_be32(&ugeth->ug_regs->uempr));
+       ugeth_info("utbipar    : addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->utbipar,
+                  in_be32(&ugeth->ug_regs->utbipar));
+       ugeth_info("uescr      : addr - 0x%08x, val - 0x%04x",
+                  (u32) & ugeth->ug_regs->uescr,
+                  in_be16(&ugeth->ug_regs->uescr));
+       ugeth_info("tx64       : addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->tx64,
+                  in_be32(&ugeth->ug_regs->tx64));
+       ugeth_info("tx127      : addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->tx127,
+                  in_be32(&ugeth->ug_regs->tx127));
+       ugeth_info("tx255      : addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->tx255,
+                  in_be32(&ugeth->ug_regs->tx255));
+       ugeth_info("rx64       : addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->rx64,
+                  in_be32(&ugeth->ug_regs->rx64));
+       ugeth_info("rx127      : addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->rx127,
+                  in_be32(&ugeth->ug_regs->rx127));
+       ugeth_info("rx255      : addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->rx255,
+                  in_be32(&ugeth->ug_regs->rx255));
+       ugeth_info("txok       : addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->txok,
+                  in_be32(&ugeth->ug_regs->txok));
+       ugeth_info("txcf       : addr - 0x%08x, val - 0x%04x",
+                  (u32) & ugeth->ug_regs->txcf,
+                  in_be16(&ugeth->ug_regs->txcf));
+       ugeth_info("tmca       : addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->tmca,
+                  in_be32(&ugeth->ug_regs->tmca));
+       ugeth_info("tbca       : addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->tbca,
+                  in_be32(&ugeth->ug_regs->tbca));
+       ugeth_info("rxfok      : addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->rxfok,
+                  in_be32(&ugeth->ug_regs->rxfok));
+       ugeth_info("rxbok      : addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->rxbok,
+                  in_be32(&ugeth->ug_regs->rxbok));
+       ugeth_info("rbyt       : addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->rbyt,
+                  in_be32(&ugeth->ug_regs->rbyt));
+       ugeth_info("rmca       : addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->rmca,
+                  in_be32(&ugeth->ug_regs->rmca));
+       ugeth_info("rbca       : addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->rbca,
+                  in_be32(&ugeth->ug_regs->rbca));
+       ugeth_info("scar       : addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->scar,
+                  in_be32(&ugeth->ug_regs->scar));
+       ugeth_info("scam       : addr - 0x%08x, val - 0x%08x",
+                  (u32) & ugeth->ug_regs->scam,
+                  in_be32(&ugeth->ug_regs->scam));
+
+       if (ugeth->p_thread_data_tx) {
+               int numThreadsTxNumerical;
+               switch (ugeth->ug_info->numThreadsTx) {
+               case UCC_GETH_NUM_OF_THREADS_1:
+                       numThreadsTxNumerical = 1;
+                       break;
+               case UCC_GETH_NUM_OF_THREADS_2:
+                       numThreadsTxNumerical = 2;
+                       break;
+               case UCC_GETH_NUM_OF_THREADS_4:
+                       numThreadsTxNumerical = 4;
+                       break;
+               case UCC_GETH_NUM_OF_THREADS_6:
+                       numThreadsTxNumerical = 6;
+                       break;
+               case UCC_GETH_NUM_OF_THREADS_8:
+                       numThreadsTxNumerical = 8;
+                       break;
+               default:
+                       numThreadsTxNumerical = 0;
+                       break;
+               }
+
+               ugeth_info("Thread data TXs:");
+               ugeth_info("Base address: 0x%08x",
+                          (u32) ugeth->p_thread_data_tx);
+               for (i = 0; i < numThreadsTxNumerical; i++) {
+                       ugeth_info("Thread data TX[%d]:", i);
+                       ugeth_info("Base address: 0x%08x",
+                                  (u32) & ugeth->p_thread_data_tx[i]);
+                       mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
+                                sizeof(ucc_geth_thread_data_tx_t));
+               }
+       }
+       if (ugeth->p_thread_data_rx) {
+               int numThreadsRxNumerical;
+               switch (ugeth->ug_info->numThreadsRx) {
+               case UCC_GETH_NUM_OF_THREADS_1:
+                       numThreadsRxNumerical = 1;
+                       break;
+               case UCC_GETH_NUM_OF_THREADS_2:
+                       numThreadsRxNumerical = 2;
+                       break;
+               case UCC_GETH_NUM_OF_THREADS_4:
+                       numThreadsRxNumerical = 4;
+                       break;
+               case UCC_GETH_NUM_OF_THREADS_6:
+                       numThreadsRxNumerical = 6;
+                       break;
+               case UCC_GETH_NUM_OF_THREADS_8:
+                       numThreadsRxNumerical = 8;
+                       break;
+               default:
+                       numThreadsRxNumerical = 0;
+                       break;
+               }
+
+               ugeth_info("Thread data RX:");
+               ugeth_info("Base address: 0x%08x",
+                          (u32) ugeth->p_thread_data_rx);
+               for (i = 0; i < numThreadsRxNumerical; i++) {
+                       ugeth_info("Thread data RX[%d]:", i);
+                       ugeth_info("Base address: 0x%08x",
+                                  (u32) & ugeth->p_thread_data_rx[i]);
+                       mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
+                                sizeof(ucc_geth_thread_data_rx_t));
+               }
+       }
+       if (ugeth->p_exf_glbl_param) {
+               ugeth_info("EXF global param:");
+               ugeth_info("Base address: 0x%08x",
+                          (u32) ugeth->p_exf_glbl_param);
+               mem_disp((u8 *) ugeth->p_exf_glbl_param,
+                        sizeof(*ugeth->p_exf_glbl_param));
+       }
+       if (ugeth->p_tx_glbl_pram) {
+               ugeth_info("TX global param:");
+               ugeth_info("Base address: 0x%08x", (u32) ugeth->p_tx_glbl_pram);
+               ugeth_info("temoder      : addr - 0x%08x, val - 0x%04x",
+                          (u32) & ugeth->p_tx_glbl_pram->temoder,
+                          in_be16(&ugeth->p_tx_glbl_pram->temoder));
+               ugeth_info("sqptr        : addr - 0x%08x, val - 0x%08x",
+                          (u32) & ugeth->p_tx_glbl_pram->sqptr,
+                          in_be32(&ugeth->p_tx_glbl_pram->sqptr));
+               ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x",
+                          (u32) & ugeth->p_tx_glbl_pram->schedulerbasepointer,
+                          in_be32(&ugeth->p_tx_glbl_pram->
+                                  schedulerbasepointer));
+               ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x",
+                          (u32) & ugeth->p_tx_glbl_pram->txrmonbaseptr,
+                          in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
+               ugeth_info("tstate       : addr - 0x%08x, val - 0x%08x",
+                          (u32) & ugeth->p_tx_glbl_pram->tstate,
+                          in_be32(&ugeth->p_tx_glbl_pram->tstate));
+               ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x",
+                          (u32) & ugeth->p_tx_glbl_pram->iphoffset[0],
+                          ugeth->p_tx_glbl_pram->iphoffset[0]);
+               ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x",
+                          (u32) & ugeth->p_tx_glbl_pram->iphoffset[1],
+                          ugeth->p_tx_glbl_pram->iphoffset[1]);
+               ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x",
+                          (u32) & ugeth->p_tx_glbl_pram->iphoffset[2],
+                          ugeth->p_tx_glbl_pram->iphoffset[2]);
+               ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x",
+                          (u32) & ugeth->p_tx_glbl_pram->iphoffset[3],
+                          ugeth->p_tx_glbl_pram->iphoffset[3]);
+               ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x",
+                          (u32) & ugeth->p_tx_glbl_pram->iphoffset[4],
+                          ugeth->p_tx_glbl_pram->iphoffset[4]);
+               ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x",
+                          (u32) & ugeth->p_tx_glbl_pram->iphoffset[5],
+                          ugeth->p_tx_glbl_pram->iphoffset[5]);
+               ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x",
+                          (u32) & ugeth->p_tx_glbl_pram->iphoffset[6],
+                          ugeth->p_tx_glbl_pram->iphoffset[6]);
+               ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x",
+                          (u32) & ugeth->p_tx_glbl_pram->iphoffset[7],
+                          ugeth->p_tx_glbl_pram->iphoffset[7]);
+               ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x",
+                          (u32) & ugeth->p_tx_glbl_pram->vtagtable[0],
+                          in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
+               ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x",
+                          (u32) & ugeth->p_tx_glbl_pram->vtagtable[1],
+                          in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
+               ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x",
+                          (u32) & ugeth->p_tx_glbl_pram->vtagtable[2],
+                          in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
+               ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x",
+                          (u32) & ugeth->p_tx_glbl_pram->vtagtable[3],
+                          in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
+               ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x",
+                          (u32) & ugeth->p_tx_glbl_pram->vtagtable[4],
+                          in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
+               ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x",
+                          (u32) & ugeth->p_tx_glbl_pram->vtagtable[5],
+                          in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
+               ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x",
+                          (u32) & ugeth->p_tx_glbl_pram->vtagtable[6],
+                          in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
+               ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x",
+                          (u32) & ugeth->p_tx_glbl_pram->vtagtable[7],
+                          in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
+               ugeth_info("tqptr        : addr - 0x%08x, val - 0x%08x",
+                          (u32) & ugeth->p_tx_glbl_pram->tqptr,
+                          in_be32(&ugeth->p_tx_glbl_pram->tqptr));
+       }
+       if (ugeth->p_rx_glbl_pram) {
+               ugeth_info("RX global param:");
+               ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_glbl_pram);
+               ugeth_info("remoder         : addr - 0x%08x, val - 0x%08x",
+                          (u32) & ugeth->p_rx_glbl_pram->remoder,
+                          in_be32(&ugeth->p_rx_glbl_pram->remoder));
+               ugeth_info("rqptr           : addr - 0x%08x, val - 0x%08x",
+                          (u32) & ugeth->p_rx_glbl_pram->rqptr,
+                          in_be32(&ugeth->p_rx_glbl_pram->rqptr));
+               ugeth_info("typeorlen       : addr - 0x%08x, val - 0x%04x",
+                          (u32) & ugeth->p_rx_glbl_pram->typeorlen,
+                          in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
+               ugeth_info("rxgstpack       : addr - 0x%08x, val - 0x%02x",
+                          (u32) & ugeth->p_rx_glbl_pram->rxgstpack,
+                          ugeth->p_rx_glbl_pram->rxgstpack);
+               ugeth_info("rxrmonbaseptr   : addr - 0x%08x, val - 0x%08x",
+                          (u32) & ugeth->p_rx_glbl_pram->rxrmonbaseptr,
+                          in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
+               ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x",
+                          (u32) & ugeth->p_rx_glbl_pram->intcoalescingptr,
+                          in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
+               ugeth_info("rstate          : addr - 0x%08x, val - 0x%02x",
+                          (u32) & ugeth->p_rx_glbl_pram->rstate,
+                          ugeth->p_rx_glbl_pram->rstate);
+               ugeth_info("mrblr           : addr - 0x%08x, val - 0x%04x",
+                          (u32) & ugeth->p_rx_glbl_pram->mrblr,
+                          in_be16(&ugeth->p_rx_glbl_pram->mrblr));
+               ugeth_info("rbdqptr         : addr - 0x%08x, val - 0x%08x",
+                          (u32) & ugeth->p_rx_glbl_pram->rbdqptr,
+                          in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
+               ugeth_info("mflr            : addr - 0x%08x, val - 0x%04x",
+                          (u32) & ugeth->p_rx_glbl_pram->mflr,
+                          in_be16(&ugeth->p_rx_glbl_pram->mflr));
+               ugeth_info("minflr          : addr - 0x%08x, val - 0x%04x",
+                          (u32) & ugeth->p_rx_glbl_pram->minflr,
+                          in_be16(&ugeth->p_rx_glbl_pram->minflr));
+               ugeth_info("maxd1           : addr - 0x%08x, val - 0x%04x",
+                          (u32) & ugeth->p_rx_glbl_pram->maxd1,
+                          in_be16(&ugeth->p_rx_glbl_pram->maxd1));
+               ugeth_info("maxd2           : addr - 0x%08x, val - 0x%04x",
+                          (u32) & ugeth->p_rx_glbl_pram->maxd2,
+                          in_be16(&ugeth->p_rx_glbl_pram->maxd2));
+               ugeth_info("ecamptr         : addr - 0x%08x, val - 0x%08x",
+                          (u32) & ugeth->p_rx_glbl_pram->ecamptr,
+                          in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
+               ugeth_info("l2qt            : addr - 0x%08x, val - 0x%08x",
+                          (u32) & ugeth->p_rx_glbl_pram->l2qt,
+                          in_be32(&ugeth->p_rx_glbl_pram->l2qt));
+               ugeth_info("l3qt[0]         : addr - 0x%08x, val - 0x%08x",
+                          (u32) & ugeth->p_rx_glbl_pram->l3qt[0],
+                          in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
+               ugeth_info("l3qt[1]         : addr - 0x%08x, val - 0x%08x",
+                          (u32) & ugeth->p_rx_glbl_pram->l3qt[1],
+                          in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
+               ugeth_info("l3qt[2]         : addr - 0x%08x, val - 0x%08x",
+                          (u32) & ugeth->p_rx_glbl_pram->l3qt[2],
+                          in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
+               ugeth_info("l3qt[3]         : addr - 0x%08x, val - 0x%08x",
+                          (u32) & ugeth->p_rx_glbl_pram->l3qt[3],
+                          in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
+               ugeth_info("l3qt[4]         : addr - 0x%08x, val - 0x%08x",
+                          (u32) & ugeth->p_rx_glbl_pram->l3qt[4],
+                          in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
+               ugeth_info("l3qt[5]         : addr - 0x%08x, val - 0x%08x",
+                          (u32) & ugeth->p_rx_glbl_pram->l3qt[5],
+                          in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
+               ugeth_info("l3qt[6]         : addr - 0x%08x, val - 0x%08x",
+                          (u32) & ugeth->p_rx_glbl_pram->l3qt[6],
+                          in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
+               ugeth_info("l3qt[7]         : addr - 0x%08x, val - 0x%08x",
+                          (u32) & ugeth->p_rx_glbl_pram->l3qt[7],
+                          in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
+               ugeth_info("vlantype        : addr - 0x%08x, val - 0x%04x",
+                          (u32) & ugeth->p_rx_glbl_pram->vlantype,
+                          in_be16(&ugeth->p_rx_glbl_pram->vlantype));
+               ugeth_info("vlantci         : addr - 0x%08x, val - 0x%04x",
+                          (u32) & ugeth->p_rx_glbl_pram->vlantci,
+                          in_be16(&ugeth->p_rx_glbl_pram->vlantci));
+               for (i = 0; i < 64; i++)
+                       ugeth_info
+                   ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x",
+                            i,
+                            (u32) & ugeth->p_rx_glbl_pram->addressfiltering[i],
+                            ugeth->p_rx_glbl_pram->addressfiltering[i]);
+               ugeth_info("exfGlobalParam  : addr - 0x%08x, val - 0x%08x",
+                          (u32) & ugeth->p_rx_glbl_pram->exfGlobalParam,
+                          in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
+       }
+       if (ugeth->p_send_q_mem_reg) {
+               ugeth_info("Send Q memory registers:");
+               ugeth_info("Base address: 0x%08x",
+                          (u32) ugeth->p_send_q_mem_reg);
+               for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
+                       ugeth_info("SQQD[%d]:", i);
+                       ugeth_info("Base address: 0x%08x",
+                                  (u32) & ugeth->p_send_q_mem_reg->sqqd[i]);
+                       mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
+                                sizeof(ucc_geth_send_queue_qd_t));
+               }
+       }
+       if (ugeth->p_scheduler) {
+               ugeth_info("Scheduler:");
+               ugeth_info("Base address: 0x%08x", (u32) ugeth->p_scheduler);
+               mem_disp((u8 *) ugeth->p_scheduler,
+                        sizeof(*ugeth->p_scheduler));
+       }
+       if (ugeth->p_tx_fw_statistics_pram) {
+               ugeth_info("TX FW statistics pram:");
+               ugeth_info("Base address: 0x%08x",
+                          (u32) ugeth->p_tx_fw_statistics_pram);
+               mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
+                        sizeof(*ugeth->p_tx_fw_statistics_pram));
+       }
+       if (ugeth->p_rx_fw_statistics_pram) {
+               ugeth_info("RX FW statistics pram:");
+               ugeth_info("Base address: 0x%08x",
+                          (u32) ugeth->p_rx_fw_statistics_pram);
+               mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
+                        sizeof(*ugeth->p_rx_fw_statistics_pram));
+       }
+       if (ugeth->p_rx_irq_coalescing_tbl) {
+               ugeth_info("RX IRQ coalescing tables:");
+               ugeth_info("Base address: 0x%08x",
+                          (u32) ugeth->p_rx_irq_coalescing_tbl);
+               for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
+                       ugeth_info("RX IRQ coalescing table entry[%d]:", i);
+                       ugeth_info("Base address: 0x%08x",
+                                  (u32) & ugeth->p_rx_irq_coalescing_tbl->
+                                  coalescingentry[i]);
+                       ugeth_info
+               ("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x",
+                            (u32) & ugeth->p_rx_irq_coalescing_tbl->
+                            coalescingentry[i].interruptcoalescingmaxvalue,
+                            in_be32(&ugeth->p_rx_irq_coalescing_tbl->
+                                    coalescingentry[i].
+                                    interruptcoalescingmaxvalue));
+                       ugeth_info
+               ("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x",
+                            (u32) & ugeth->p_rx_irq_coalescing_tbl->
+                            coalescingentry[i].interruptcoalescingcounter,
+                            in_be32(&ugeth->p_rx_irq_coalescing_tbl->
+                                    coalescingentry[i].
+                                    interruptcoalescingcounter));
+               }
+       }
+       if (ugeth->p_rx_bd_qs_tbl) {
+               ugeth_info("RX BD QS tables:");
+               ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_bd_qs_tbl);
+               for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
+                       ugeth_info("RX BD QS table[%d]:", i);
+                       ugeth_info("Base address: 0x%08x",
+                                  (u32) & ugeth->p_rx_bd_qs_tbl[i]);
+                       ugeth_info
+                           ("bdbaseptr        : addr - 0x%08x, val - 0x%08x",
+                            (u32) & ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
+                            in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
+                       ugeth_info
+                           ("bdptr            : addr - 0x%08x, val - 0x%08x",
+                            (u32) & ugeth->p_rx_bd_qs_tbl[i].bdptr,
+                            in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
+                       ugeth_info
+                           ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x",
+                            (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
+                            in_be32(&ugeth->p_rx_bd_qs_tbl[i].
+                                    externalbdbaseptr));
+                       ugeth_info
+                           ("externalbdptr    : addr - 0x%08x, val - 0x%08x",
+                            (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
+                            in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
+                       ugeth_info("ucode RX Prefetched BDs:");
+                       ugeth_info("Base address: 0x%08x",
+                                  (u32)
+                                  qe_muram_addr(in_be32
+                                                (&ugeth->p_rx_bd_qs_tbl[i].
+                                                 bdbaseptr)));
+                       mem_disp((u8 *)
+                                qe_muram_addr(in_be32
+                                              (&ugeth->p_rx_bd_qs_tbl[i].
+                                               bdbaseptr)),
+                                sizeof(ucc_geth_rx_prefetched_bds_t));
+               }
+       }
+       if (ugeth->p_init_enet_param_shadow) {
+               int size;
+               ugeth_info("Init enet param shadow:");
+               ugeth_info("Base address: 0x%08x",
+                          (u32) ugeth->p_init_enet_param_shadow);
+               mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
+                        sizeof(*ugeth->p_init_enet_param_shadow));
+
+               size = sizeof(ucc_geth_thread_rx_pram_t);
+               if (ugeth->ug_info->rxExtendedFiltering) {
+                       size +=
+                           THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
+                       if (ugeth->ug_info->largestexternallookupkeysize ==
+                           QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
+                               size +=
+                       THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
+                       if (ugeth->ug_info->largestexternallookupkeysize ==
+                           QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
+                               size +=
+                       THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
+               }
+
+               dump_init_enet_entries(ugeth,
+                                      &(ugeth->p_init_enet_param_shadow->
+                                        txthread[0]),
+                                      ENET_INIT_PARAM_MAX_ENTRIES_TX,
+                                      sizeof(ucc_geth_thread_tx_pram_t),
+                                      ugeth->ug_info->riscTx, 0);
+               dump_init_enet_entries(ugeth,
+                                      &(ugeth->p_init_enet_param_shadow->
+                                        rxthread[0]),
+                                      ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
+                                      ugeth->ug_info->riscRx, 1);
+       }
+}
+#endif /* DEBUG */
+
+static void init_default_reg_vals(volatile u32 *upsmr_register,
+                                 volatile u32 *maccfg1_register,
+                                 volatile u32 *maccfg2_register)
+{
+       out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
+       out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
+       out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
+}
+
+static int init_half_duplex_params(int alt_beb,
+                                  int back_pressure_no_backoff,
+                                  int no_backoff,
+                                  int excess_defer,
+                                  u8 alt_beb_truncation,
+                                  u8 max_retransmissions,
+                                  u8 collision_window,
+                                  volatile u32 *hafdup_register)
+{
+       u32 value = 0;
+
+       if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
+           (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
+           (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
+               return -EINVAL;
+
+       value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
+
+       if (alt_beb)
+               value |= HALFDUP_ALT_BEB;
+       if (back_pressure_no_backoff)
+               value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
+       if (no_backoff)
+               value |= HALFDUP_NO_BACKOFF;
+       if (excess_defer)
+               value |= HALFDUP_EXCESSIVE_DEFER;
+
+       value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
+
+       value |= collision_window;
+
+       out_be32(hafdup_register, value);
+       return 0;
+}
+
+static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
+                                      u8 non_btb_ipg,
+                                      u8 min_ifg,
+                                      u8 btb_ipg,
+                                      volatile u32 *ipgifg_register)
+{
+       u32 value = 0;
+
+       /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
+       IPG part 2 */
+       if (non_btb_cs_ipg > non_btb_ipg)
+               return -EINVAL;
+
+       if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
+           (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
+           /*(min_ifg        > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
+           (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
+               return -EINVAL;
+
+       value |=
+           ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
+            IPGIFG_NBTB_CS_IPG_MASK);
+       value |=
+           ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
+            IPGIFG_NBTB_IPG_MASK);
+       value |=
+           ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
+            IPGIFG_MIN_IFG_MASK);
+       value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
+
+       out_be32(ipgifg_register, value);
+       return 0;
+}
+
+static int init_flow_control_params(u32 automatic_flow_control_mode,
+                                   int rx_flow_control_enable,
+                                   int tx_flow_control_enable,
+                                   u16 pause_period,
+                                   u16 extension_field,
+                                   volatile u32 *upsmr_register,
+                                   volatile u32 *uempr_register,
+                                   volatile u32 *maccfg1_register)
+{
+       u32 value = 0;
+
+       /* Set UEMPR register */
+       value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
+       value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
+       out_be32(uempr_register, value);
+
+       /* Set UPSMR register */
+       value = in_be32(upsmr_register);
+       value |= automatic_flow_control_mode;
+       out_be32(upsmr_register, value);
+
+       value = in_be32(maccfg1_register);
+       if (rx_flow_control_enable)
+               value |= MACCFG1_FLOW_RX;
+       if (tx_flow_control_enable)
+               value |= MACCFG1_FLOW_TX;
+       out_be32(maccfg1_register, value);
+
+       return 0;
+}
+
+static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
+                                            int auto_zero_hardware_statistics,
+                                            volatile u32 *upsmr_register,
+                                            volatile u16 *uescr_register)
+{
+       u32 upsmr_value = 0;
+       u16 uescr_value = 0;
+       /* Enable hardware statistics gathering if requested */
+       if (enable_hardware_statistics) {
+               upsmr_value = in_be32(upsmr_register);
+               upsmr_value |= UPSMR_HSE;
+               out_be32(upsmr_register, upsmr_value);
+       }
+
+       /* Clear hardware statistics counters */
+       uescr_value = in_be16(uescr_register);
+       uescr_value |= UESCR_CLRCNT;
+       /* Automatically zero hardware statistics counters on read,
+       if requested */
+       if (auto_zero_hardware_statistics)
+               uescr_value |= UESCR_AUTOZ;
+       out_be16(uescr_register, uescr_value);
+
+       return 0;
+}
+
+static int init_firmware_statistics_gathering_mode(int
+               enable_tx_firmware_statistics,
+               int enable_rx_firmware_statistics,
+               volatile u32 *tx_rmon_base_ptr,
+               u32 tx_firmware_statistics_structure_address,
+               volatile u32 *rx_rmon_base_ptr,
+               u32 rx_firmware_statistics_structure_address,
+               volatile u16 *temoder_register,
+               volatile u32 *remoder_register)
+{
+       /* Note: this function does not check if */
+       /* the parameters it receives are NULL   */
+       u16 temoder_value;
+       u32 remoder_value;
+
+       if (enable_tx_firmware_statistics) {
+               out_be32(tx_rmon_base_ptr,
+                        tx_firmware_statistics_structure_address);
+               temoder_value = in_be16(temoder_register);
+               temoder_value |= TEMODER_TX_RMON_STATISTICS_ENABLE;
+               out_be16(temoder_register, temoder_value);
+       }
+
+       if (enable_rx_firmware_statistics) {
+               out_be32(rx_rmon_base_ptr,
+                        rx_firmware_statistics_structure_address);
+               remoder_value = in_be32(remoder_register);
+               remoder_value |= REMODER_RX_RMON_STATISTICS_ENABLE;
+               out_be32(remoder_register, remoder_value);
+       }
+
+       return 0;
+}
+
+static int init_mac_station_addr_regs(u8 address_byte_0,
+                                     u8 address_byte_1,
+                                     u8 address_byte_2,
+                                     u8 address_byte_3,
+                                     u8 address_byte_4,
+                                     u8 address_byte_5,
+                                     volatile u32 *macstnaddr1_register,
+                                     volatile u32 *macstnaddr2_register)
+{
+       u32 value = 0;
+
+       /* Example: for a station address of 0x12345678ABCD, */
+       /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
+
+       /* MACSTNADDR1 Register: */
+
+       /* 0                      7   8                      15  */
+       /* station address byte 5     station address byte 4     */
+       /* 16                     23  24                     31  */
+       /* station address byte 3     station address byte 2     */
+       value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
+       value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
+       value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
+       value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
+
+       out_be32(macstnaddr1_register, value);
+
+       /* MACSTNADDR2 Register: */
+
+       /* 0                      7   8                      15  */
+       /* station address byte 1     station address byte 0     */
+       /* 16                     23  24                     31  */
+       /*         reserved                   reserved           */
+       value = 0;
+       value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
+       value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
+
+       out_be32(macstnaddr2_register, value);
+
+       return 0;
+}
+
+static int init_mac_duplex_mode(int full_duplex,
+                               int limited_to_full_duplex,
+                               volatile u32 *maccfg2_register)
+{
+       u32 value = 0;
+
+       /* some interfaces must work in full duplex mode */
+       if ((full_duplex == 0) && (limited_to_full_duplex == 1))
+               return -EINVAL;
+
+       value = in_be32(maccfg2_register);
+
+       if (full_duplex)
+               value |= MACCFG2_FDX;
+       else
+               value &= ~MACCFG2_FDX;
+
+       out_be32(maccfg2_register, value);
+       return 0;
+}
+
+static int init_check_frame_length_mode(int length_check,
+                                       volatile u32 *maccfg2_register)
+{
+       u32 value = 0;
+
+       value = in_be32(maccfg2_register);
+
+       if (length_check)
+               value |= MACCFG2_LC;
+       else
+               value &= ~MACCFG2_LC;
+
+       out_be32(maccfg2_register, value);
+       return 0;
+}
+
+static int init_preamble_length(u8 preamble_length,
+                               volatile u32 *maccfg2_register)
+{
+       u32 value = 0;
+
+       if ((preamble_length < 3) || (preamble_length > 7))
+               return -EINVAL;
+
+       value = in_be32(maccfg2_register);
+       value &= ~MACCFG2_PREL_MASK;
+       value |= (preamble_length << MACCFG2_PREL_SHIFT);
+       out_be32(maccfg2_register, value);
+       return 0;
+}
+
+static int init_mii_management_configuration(int reset_mgmt,
+                                            int preamble_supress,
+                                            volatile u32 *miimcfg_register,
+                                            volatile u32 *miimind_register)
+{
+       unsigned int timeout = PHY_INIT_TIMEOUT;
+       u32 value = 0;
+
+       value = in_be32(miimcfg_register);
+       if (reset_mgmt) {
+               value |= MIIMCFG_RESET_MANAGEMENT;
+               out_be32(miimcfg_register, value);
+       }
+
+       value = 0;
+
+       if (preamble_supress)
+               value |= MIIMCFG_NO_PREAMBLE;
+
+       value |= UCC_GETH_MIIMCFG_MNGMNT_CLC_DIV_INIT;
+       out_be32(miimcfg_register, value);
+
+       /* Wait until the bus is free */
+       while ((in_be32(miimind_register) & MIIMIND_BUSY) && timeout--)
+               cpu_relax();
+
+       if (timeout <= 0) {
+               ugeth_err("%s: The MII Bus is stuck!", __FUNCTION__);
+               return -ETIMEDOUT;
+       }
+
+       return 0;
+}
+
+static int init_rx_parameters(int reject_broadcast,
+                             int receive_short_frames,
+                             int promiscuous, volatile u32 *upsmr_register)
+{
+       u32 value = 0;
+
+       value = in_be32(upsmr_register);
+
+       if (reject_broadcast)
+               value |= UPSMR_BRO;
+       else
+               value &= ~UPSMR_BRO;
+
+       if (receive_short_frames)
+               value |= UPSMR_RSH;
+       else
+               value &= ~UPSMR_RSH;
+
+       if (promiscuous)
+               value |= UPSMR_PRO;
+       else
+               value &= ~UPSMR_PRO;
+
+       out_be32(upsmr_register, value);
+
+       return 0;
+}
+
+static int init_max_rx_buff_len(u16 max_rx_buf_len,
+                               volatile u16 *mrblr_register)
+{
+       /* max_rx_buf_len value must be a multiple of 128 */
+       if ((max_rx_buf_len == 0)
+           || (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
+               return -EINVAL;
+
+       out_be16(mrblr_register, max_rx_buf_len);
+       return 0;
+}
+
+static int init_min_frame_len(u16 min_frame_length,
+                             volatile u16 *minflr_register,
+                             volatile u16 *mrblr_register)
+{
+       u16 mrblr_value = 0;
+
+       mrblr_value = in_be16(mrblr_register);
+       if (min_frame_length >= (mrblr_value - 4))
+               return -EINVAL;
+
+       out_be16(minflr_register, min_frame_length);
+       return 0;
+}
+
+static int adjust_enet_interface(ucc_geth_private_t *ugeth)
+{
+       ucc_geth_info_t *ug_info;
+       ucc_geth_t *ug_regs;
+       ucc_fast_t *uf_regs;
+       enet_speed_e speed;
+       int ret_val, rpm = 0, tbi = 0, r10m = 0, rmm =
+           0, limited_to_full_duplex = 0;
+       u32 upsmr, maccfg2, utbipar, tbiBaseAddress;
+       u16 value;
+
+       ugeth_vdbg("%s: IN", __FUNCTION__);
+
+       ug_info = ugeth->ug_info;
+       ug_regs = ugeth->ug_regs;
+       uf_regs = ugeth->uccf->uf_regs;
+
+       /* Analyze enet_interface according to Interface Mode Configuration
+       table */
+       ret_val =
+           get_interface_details(ug_info->enet_interface, &speed, &r10m, &rmm,
+                                 &rpm, &tbi, &limited_to_full_duplex);
+       if (ret_val != 0) {
+               ugeth_err
+                 ("%s: half duplex not supported in requested configuration.",
+                    __FUNCTION__);
+               return ret_val;
+       }
+
+       /*                    Set MACCFG2                    */
+       maccfg2 = in_be32(&ug_regs->maccfg2);
+       maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
+       if ((speed == ENET_SPEED_10BT) || (speed == ENET_SPEED_100BT))
+               maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
+       else if (speed == ENET_SPEED_1000BT)
+               maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
+       maccfg2 |= ug_info->padAndCrc;
+       out_be32(&ug_regs->maccfg2, maccfg2);
+
+       /*                    Set UPSMR                      */
+       upsmr = in_be32(&uf_regs->upsmr);
+       upsmr &= ~(UPSMR_RPM | UPSMR_R10M | UPSMR_TBIM | UPSMR_RMM);
+       if (rpm)
+               upsmr |= UPSMR_RPM;
+       if (r10m)
+               upsmr |= UPSMR_R10M;
+       if (tbi)
+               upsmr |= UPSMR_TBIM;
+       if (rmm)
+               upsmr |= UPSMR_RMM;
+       out_be32(&uf_regs->upsmr, upsmr);
+
+       /*                    Set UTBIPAR                    */
+       utbipar = in_be32(&ug_regs->utbipar);
+       utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
+       if (tbi)
+               utbipar |=
+                   (ug_info->phy_address +
+                    ugeth->ug_info->uf_info.
+                    ucc_num) << UTBIPAR_PHY_ADDRESS_SHIFT;
+       else
+               utbipar |=
+                   (0x10 +
+                    ugeth->ug_info->uf_info.
+                    ucc_num) << UTBIPAR_PHY_ADDRESS_SHIFT;
+       out_be32(&ug_regs->utbipar, utbipar);
+
+       /* Disable autonegotiation in tbi mode, because by default it
+       comes up in autonegotiation mode. */
+       /* Note that this depends on proper setting in utbipar register. */
+       if (tbi) {
+               tbiBaseAddress = in_be32(&ug_regs->utbipar);
+               tbiBaseAddress &= UTBIPAR_PHY_ADDRESS_MASK;
+               tbiBaseAddress >>= UTBIPAR_PHY_ADDRESS_SHIFT;
+               value =
+                   ugeth->mii_info->mdio_read(ugeth->dev, (u8) tbiBaseAddress,
+                                              ENET_TBI_MII_CR);
+               value &= ~0x1000;       /* Turn off autonegotiation */
+               ugeth->mii_info->mdio_write(ugeth->dev, (u8) tbiBaseAddress,
+                                           ENET_TBI_MII_CR, value);
+       }
+
+       ret_val = init_mac_duplex_mode(1,
+                                      limited_to_full_duplex,
+                                      &ug_regs->maccfg2);
+       if (ret_val != 0) {
+               ugeth_err
+               ("%s: half duplex not supported in requested configuration.",
+                    __FUNCTION__);
+               return ret_val;
+       }
+
+       init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
+
+       ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
+       if (ret_val != 0) {
+               ugeth_err
+                   ("%s: Preamble length must be between 3 and 7 inclusive.",
+                    __FUNCTION__);
+               return ret_val;
+       }
+
+       return 0;
+}
+
+/* Called every time the controller might need to be made
+ * aware of new link state.  The PHY code conveys this
+ * information through variables in the ugeth structure, and this
+ * function converts those variables into the appropriate
+ * register values, and can bring down the device if needed.
+ */
+static void adjust_link(struct net_device *dev)
+{
+       ucc_geth_private_t *ugeth = netdev_priv(dev);
+       ucc_geth_t *ug_regs;
+       u32 tempval;
+       struct ugeth_mii_info *mii_info = ugeth->mii_info;
+
+       ug_regs = ugeth->ug_regs;
+
+       if (mii_info->link) {
+               /* Now we make sure that we can be in full duplex mode.
+                * If not, we operate in half-duplex mode. */
+               if (mii_info->duplex != ugeth->oldduplex) {
+                       if (!(mii_info->duplex)) {
+                               tempval = in_be32(&ug_regs->maccfg2);
+                               tempval &= ~(MACCFG2_FDX);
+                               out_be32(&ug_regs->maccfg2, tempval);
+
+                               ugeth_info("%s: Half Duplex", dev->name);
+                       } else {
+                               tempval = in_be32(&ug_regs->maccfg2);
+                               tempval |= MACCFG2_FDX;
+                               out_be32(&ug_regs->maccfg2, tempval);
+
+                               ugeth_info("%s: Full Duplex", dev->name);
+                       }
+
+                       ugeth->oldduplex = mii_info->duplex;
+               }
+
+               if (mii_info->speed != ugeth->oldspeed) {
+                       switch (mii_info->speed) {
+                       case 1000:
+#ifdef CONFIG_MPC836x
+/* FIXME: This code is for 100Mbs BUG fixing,
+remove this when it is fixed!!! */
+                               if (ugeth->ug_info->enet_interface ==
+                                   ENET_1000_GMII)
+                               /* Run the commands which initialize the PHY */
+                               {
+                                       tempval =
+                                           (u32) mii_info->mdio_read(ugeth->
+                                               dev, mii_info->mii_id, 0x1b);
+                                       tempval |= 0x000f;
+                                       mii_info->mdio_write(ugeth->dev,
+                                               mii_info->mii_id, 0x1b,
+                                               (u16) tempval);
+                                       tempval =
+                                           (u32) mii_info->mdio_read(ugeth->
+                                               dev, mii_info->mii_id,
+                                               MII_BMCR);
+                                       mii_info->mdio_write(ugeth->dev,
+                           &nb