static struct resource mipidsi0_resources[] = {
[0] = {
.start = 0xffc60000,
- .end = 0xffc68fff,
+ .end = 0xffc63073,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = 0xffc68000,
+ .end = 0xffc680ef,
.flags = IORESOURCE_MEM,
},
};
static struct sh_mipi_dsi_info mipidsi0_info = {
.data_format = MIPI_RGB888,
.lcd_chan = &lcdc_info.ch[0],
+ .vsynw_offset = 17,
};
static struct platform_device mipidsi0_device = {
},
};
-/* This function will disappear when we switch to (runtime) PM */
-static int __init ap4evb_init_display_clk(void)
-{
- struct clk *lcdc_clk;
- struct clk *dsitx_clk;
- int ret;
-
- lcdc_clk = clk_get(&lcdc_device.dev, "sh_mobile_lcdc_fb.0");
- if (IS_ERR(lcdc_clk))
- return PTR_ERR(lcdc_clk);
-
- dsitx_clk = clk_get(&mipidsi0_device.dev, "sh-mipi-dsi.0");
- if (IS_ERR(dsitx_clk)) {
- ret = PTR_ERR(dsitx_clk);
- goto eclkdsitxget;
- }
-
- ret = clk_enable(lcdc_clk);
- if (ret < 0)
- goto eclklcdcon;
-
- ret = clk_enable(dsitx_clk);
- if (ret < 0)
- goto eclkdsitxon;
-
- return 0;
-
-eclkdsitxon:
- clk_disable(lcdc_clk);
-eclklcdcon:
- clk_put(dsitx_clk);
-eclkdsitxget:
- clk_put(lcdc_clk);
-
- return ret;
-}
-device_initcall(ap4evb_init_display_clk);
-
static struct platform_device *qhd_devices[] __initdata = {
&mipidsi0_device,
&keysc_device,
},
};
+static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
+ unsigned long *parent_freq);
+
+
static struct sh_mobile_hdmi_info hdmi_info = {
.lcd_chan = &sh_mobile_lcdc1_info.ch[0],
.lcd_dev = &lcdc1_device.dev,
.flags = HDMI_SND_SRC_SPDIF,
+ .clk_optimize_parent = ap4evb_clk_optimize,
};
static struct resource hdmi_resources[] = {
},
};
+static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
+ unsigned long *parent_freq)
+{
+ struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
+ long error;
+
+ if (IS_ERR(hdmi_ick)) {
+ int ret = PTR_ERR(hdmi_ick);
+ pr_err("Cannot get HDMI ICK: %d\n", ret);
+ return ret;
+ }
+
+ error = clk_round_parent(hdmi_ick, target, best_freq, parent_freq, 1, 64);
+
+ clk_put(hdmi_ick);
+
+ return error;
+}
+
static struct gpio_led ap4evb_leds[] = {
{
.name = "led4",
MSTP223,
MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
MSTP329, MSTP328, MSTP323, MSTP322, MSTP314, MSTP313, MSTP312,
- MSTP415, MSTP413, MSTP411, MSTP410, MSTP406, MSTP403,
+ MSTP423, MSTP415, MSTP413, MSTP411, MSTP410, MSTP406, MSTP403,
MSTP_NR };
#define MSTP(_parent, _reg, _bit, _flags) \
[MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
[MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
[MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */
+ [MSTP423] = MSTP(&div4_clks[DIV4_B], SMSTPCR4, 23, 0), /* DSITX1 */
[MSTP415] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */
[MSTP413] = MSTP(&pllc1_div2_clk, SMSTPCR4, 13, 0), /* HDMI */
[MSTP411] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 11, 0), /* IIC3 */
CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
CLKDEV_CON_ID("hdmi_clk", &div6_reparent_clks[DIV6_HDMI]),
- CLKDEV_CON_ID("dsit_clk", &div6_clks[DIV6_DSIT]),
- CLKDEV_CON_ID("dsi0p_clk", &div6_clks[DIV6_DSI0P]),
- CLKDEV_CON_ID("dsi1p_clk", &div6_clks[DIV6_DSI1P]),
+ CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
+ CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
+ CLKDEV_ICK_ID("dsi0p_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
+ CLKDEV_ICK_ID("dsi1p_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
/* MSTP32 clocks */
CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2 */
CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
- CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
+ CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX0 */
CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */
CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMC */
+ CLKDEV_DEV_ID("sh-mipi-dsi.1", &mstp_clks[MSTP423]), /* DSITX1 */
CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), /* SDHI2 */
CLKDEV_DEV_ID("sh-mobile-hdmi", &mstp_clks[MSTP413]), /* HDMI */
CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* IIC3 */
source "drivers/staging/vt6656/Kconfig"
-source "drivers/staging/udlfb/Kconfig"
-
source "drivers/staging/hv/Kconfig"
source "drivers/staging/vme/Kconfig"
obj-$(CONFIG_OCTEON_ETHERNET) += octeon/
obj-$(CONFIG_VT6655) += vt6655/
obj-$(CONFIG_VT6656) += vt6656/
-obj-$(CONFIG_FB_UDL) += udlfb/
obj-$(CONFIG_HYPERV) += hv/
obj-$(CONFIG_VME_BUS) += vme/
obj-$(CONFIG_MRST_RAR_HANDLER) += memrar/
+++ /dev/null
-config FB_UDL
- tristate "Displaylink USB Framebuffer support"
- depends on FB && USB
- select FB_MODE_HELPERS
- select FB_SYS_FILLRECT
- select FB_SYS_COPYAREA
- select FB_SYS_IMAGEBLIT
- select FB_SYS_FOPS
- select FB_DEFERRED_IO
- ---help---
- This is a kernel framebuffer driver for DisplayLink USB devices.
- Supports fbdev clients like xf86-video-fbdev, kdrive, fbi, and
- mplayer -vo fbdev. Supports all USB 2.0 era DisplayLink devices.
- To compile as a module, choose M here: the module name is udlfb.
+++ /dev/null
-obj-$(CONFIG_FB_UDL) += udlfb.o
depends on FB
default n
+config FB_WMT_GE_ROPS
+ tristate
+ depends on FB
+ default n
+ ---help---
+ Include functions for accelerated rectangle filling and area
+ copying using WonderMedia Graphics Engine operations.
+
config FB_DEFERRED_IO
bool
depends on FB
To compile this driver as a module, choose M here: the
module will be called bfin-lq035q1-fb.
+config FB_BF537_LQ035
+ tristate "SHARP LQ035 TFT LCD (BF537 STAMP)"
+ depends on FB && (BF534 || BF536 || BF537) && I2C_BLACKFIN_TWI
+ select FB_CFB_FILLRECT
+ select FB_CFB_COPYAREA
+ select FB_CFB_IMAGEBLIT
+ select BFIN_GPTIMERS
+ help
+ This is the framebuffer device for a SHARP LQ035Q7DB03 TFT LCD
+ attached to a BF537.
+
+ To compile this driver as a module, choose M here: the
+ module will be called bf537-lq035.
+
+config FB_BFIN_7393
+ tristate "Blackfin ADV7393 Video encoder"
+ depends on FB && BLACKFIN
+ select I2C
+ select FB_CFB_FILLRECT
+ select FB_CFB_COPYAREA
+ select FB_CFB_IMAGEBLIT
+ help
+ This is the framebuffer device for a ADV7393 video encoder
+ attached to a Blackfin on the PPI port.
+ If your Blackfin board has a ADV7393 select Y.
+
+ To compile this driver as a module, choose M here: the
+ module will be called bfin_adv7393fb.
+
+choice
+ prompt "Video mode support"
+ depends on FB_BFIN_7393
+ default NTSC
+
+config NTSC
+ bool 'NTSC 720x480'
+
+config PAL
+ bool 'PAL 720x576'
+
+config NTSC_640x480
+ bool 'NTSC 640x480 (Experimental)'
+
+config PAL_640x480
+ bool 'PAL 640x480 (Experimental)'
+
+config NTSC_YCBCR
+ bool 'NTSC 720x480 YCbCR input'
+
+config PAL_YCBCR
+ bool 'PAL 720x576 YCbCR input'
+
+endchoice
+
+choice
+ prompt "Size of ADV7393 frame buffer memory Single/Double Size"
+ depends on (FB_BFIN_7393)
+ default ADV7393_1XMEM
+
+config ADV7393_1XMEM
+ bool 'Single'
+
+config ADV7393_2XMEM
+ bool 'Double'
+endchoice
+
config FB_STI
tristate "HP STI frame buffer device support"
depends on FB && PARISC
config FB_HGA
tristate "Hercules mono graphics support"
depends on FB && X86
- select FB_CFB_FILLRECT
- select FB_CFB_COPYAREA
- select FB_CFB_IMAGEBLIT
help
Say Y here if you have a Hercules mono graphics card.
To compile this driver as a module, choose M here: the
module will be called hgafb.
- As this card technology is 15 years old, most people will answer N
- here.
-
-config FB_HGA_ACCEL
- bool "Hercules mono Acceleration functions (EXPERIMENTAL)"
- depends on FB_HGA && EXPERIMENTAL
- ---help---
- This will compile the Hercules mono graphics with
- acceleration functions.
+ As this card technology is at least 25 years old,
+ most people will answer N here.
config FB_SGIVW
tristate "SGI Visual Workstation framebuffer support"
various panels and CRTs by passing in kernel cmd line option
au1200fb:panel=<name>.
+config FB_VT8500
+ bool "VT8500 LCD Driver"
+ depends on (FB = y) && ARM && ARCH_VT8500 && VTWM_VERSION_VT8500
+ select FB_WMT_GE_ROPS
+ select FB_SYS_IMAGEBLIT
+ help
+ This is the framebuffer driver for VIA VT8500 integrated LCD
+ controller.
+
+config FB_WM8505
+ bool "WM8505 frame buffer support"
+ depends on (FB = y) && ARM && ARCH_VT8500 && VTWM_VERSION_WM8505
+ select FB_WMT_GE_ROPS
+ select FB_SYS_IMAGEBLIT
+ help
+ This is the framebuffer driver for WonderMedia WM8505
+ integrated LCD controller.
+
source "drivers/video/geode/Kconfig"
config FB_HIT
If unsure, say N.
+config FB_UDL
+ tristate "Displaylink USB Framebuffer support"
+ depends on FB && USB
+ select FB_MODE_HELPERS
+ select FB_SYS_FILLRECT
+ select FB_SYS_COPYAREA
+ select FB_SYS_IMAGEBLIT
+ select FB_SYS_FOPS
+ select FB_DEFERRED_IO
+ ---help---
+ This is a kernel framebuffer driver for DisplayLink USB devices.
+ Supports fbdev clients like xf86-video-fbdev, kdrive, fbi, and
+ mplayer -vo fbdev. Supports all USB 2.0 era DisplayLink devices.
+ To compile as a module, choose M here: the module name is udlfb.
config FB_PNX4008_DUM
tristate "Display Update Module support on Philips PNX4008 board"
obj-$(CONFIG_FB_MACMODES) += macmodes.o
obj-$(CONFIG_FB_DDC) += fb_ddc.o
obj-$(CONFIG_FB_DEFERRED_IO) += fb_defio.o
+obj-$(CONFIG_FB_WMT_GE_ROPS) += wmt_ge_rops.o
# Hardware specific drivers go first
obj-$(CONFIG_FB_AMIGA) += amifb.o c2p_planar.o
obj-$(CONFIG_FB_TMIO) += tmiofb.o
obj-$(CONFIG_FB_AU1100) += au1100fb.o
obj-$(CONFIG_FB_AU1200) += au1200fb.o
+obj-$(CONFIG_FB_VT8500) += vt8500lcdfb.o
+obj-$(CONFIG_FB_WM8505) += wm8505fb.o
obj-$(CONFIG_FB_PMAG_AA) += pmag-aa-fb.o
obj-$(CONFIG_FB_PMAG_BA) += pmag-ba-fb.o
obj-$(CONFIG_FB_PMAGB_B) += pmagb-b-fb.o
obj-$(CONFIG_FB_IBM_GXT4500) += gxt4500.o
obj-$(CONFIG_FB_PS3) += ps3fb.o
obj-$(CONFIG_FB_SM501) += sm501fb.o
+obj-$(CONFIG_FB_UDL) += udlfb.o
obj-$(CONFIG_FB_XILINX) += xilinxfb.o
obj-$(CONFIG_SH_MIPI_DSI) += sh_mipi_dsi.o
obj-$(CONFIG_FB_SH_MOBILE_HDMI) += sh_mobile_hdmi.o
obj-$(CONFIG_FB_EFI) += efifb.o
obj-$(CONFIG_FB_VGA16) += vga16fb.o
obj-$(CONFIG_FB_OF) += offb.o
+obj-$(CONFIG_FB_BF537_LQ035) += bf537-lq035.o
obj-$(CONFIG_FB_BF54X_LQ043) += bf54x-lq043fb.o
obj-$(CONFIG_FB_BFIN_LQ035Q1) += bfin-lq035q1-fb.o
obj-$(CONFIG_FB_BFIN_T350MCQB) += bfin-t350mcqb-fb.o
+obj-$(CONFIG_FB_BFIN_7393) += bfin_adv7393fb.o
obj-$(CONFIG_FB_MX3) += mx3fb.o
obj-$(CONFIG_FB_DA8XX) += da8xx-fb.o
--- /dev/null
+/*
+ * Analog Devices Blackfin(BF537 STAMP) + SHARP TFT LCD.
+ * http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:tft-lcd
+ *
+ * Copyright 2006-2010 Analog Devices Inc.
+ * Licensed under the GPL-2.
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/delay.h>
+#include <linux/fb.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/sched.h>
+#include <linux/timer.h>
+#include <linux/device.h>
+#include <linux/backlight.h>
+#include <linux/lcd.h>
+#include <linux/i2c.h>
+#include <linux/spinlock.h>
+#include <linux/dma-mapping.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+
+#include <asm/blackfin.h>
+#include <asm/irq.h>
+#include <asm/dpmc.h>
+#include <asm/dma.h>
+#include <asm/portmux.h>
+
+#define NO_BL 1
+
+#define MAX_BRIGHENESS 95
+#define MIN_BRIGHENESS 5
+#define NBR_PALETTE 256
+
+static const unsigned short ppi_pins[] = {
+ P_PPI0_CLK, P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
+ P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
+ P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
+ P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15, 0
+};
+
+static unsigned char *fb_buffer; /* RGB Buffer */
+static unsigned long *dma_desc_table;
+static int t_conf_done, lq035_open_cnt;
+static DEFINE_SPINLOCK(bfin_lq035_lock);
+
+static int landscape;
+module_param(landscape, int, 0);
+MODULE_PARM_DESC(landscape,
+ "LANDSCAPE use 320x240 instead of Native 240x320 Resolution");
+
+static int bgr;
+module_param(bgr, int, 0);
+MODULE_PARM_DESC(bgr,
+ "BGR use 16-bit BGR-565 instead of RGB-565");
+
+static int nocursor = 1;
+module_param(nocursor, int, 0644);
+MODULE_PARM_DESC(nocursor, "cursor enable/disable");
+
+static unsigned long current_brightness; /* backlight */
+
+/* AD5280 vcomm */
+static unsigned char vcomm_value = 150;
+static struct i2c_client *ad5280_client;
+
+static void set_vcomm(void)
+{
+ int nr;
+
+ if (!ad5280_client)
+ return;
+
+ nr = i2c_smbus_write_byte_data(ad5280_client, 0x00, vcomm_value);
+ if (nr)
+ pr_err("i2c_smbus_write_byte_data fail: %d\n", nr);
+}
+
+static int __devinit ad5280_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ int ret;
+ if (!i2c_check_functionality(client->adapter,
+ I2C_FUNC_SMBUS_BYTE_DATA)) {
+ dev_err(&client->dev, "SMBUS Byte Data not Supported\n");
+ return -EIO;
+ }
+
+ ret = i2c_smbus_write_byte_data(client, 0x00, vcomm_value);
+ if (ret) {
+ dev_err(&client->dev, "write fail: %d\n", ret);
+ return ret;
+ }
+
+ ad5280_client = client;
+
+ return 0;
+}
+
+static int __devexit ad5280_remove(struct i2c_client *client)
+{
+ ad5280_client = NULL;
+ return 0;
+}
+
+static const struct i2c_device_id ad5280_id[] = {
+ {"bf537-lq035-ad5280", 0},
+ {}
+};
+
+MODULE_DEVICE_TABLE(i2c, ad5280_id);
+
+static struct i2c_driver ad5280_driver = {
+ .driver = {
+ .name = "bf537-lq035-ad5280",
+ },
+ .probe = ad5280_probe,
+ .remove = __devexit_p(ad5280_remove),
+ .id_table = ad5280_id,
+};
+
+#ifdef CONFIG_PNAV10
+#define MOD GPIO_PH13
+
+#define bfin_write_TIMER_LP_CONFIG bfin_write_TIMER0_CONFIG
+#define bfin_write_TIMER_LP_WIDTH bfin_write_TIMER0_WIDTH
+#define bfin_write_TIMER_LP_PERIOD bfin_write_TIMER0_PERIOD
+#define bfin_read_TIMER_LP_COUNTER bfin_read_TIMER0_COUNTER
+#define TIMDIS_LP TIMDIS0
+#define TIMEN_LP TIMEN0
+
+#define bfin_write_TIMER_SPS_CONFIG bfin_write_TIMER1_CONFIG
+#define bfin_write_TIMER_SPS_WIDTH bfin_write_TIMER1_WIDTH
+#define bfin_write_TIMER_SPS_PERIOD bfin_write_TIMER1_PERIOD
+#define TIMDIS_SPS TIMDIS1
+#define TIMEN_SPS TIMEN1
+
+#define bfin_write_TIMER_SP_CONFIG bfin_write_TIMER5_CONFIG
+#define bfin_write_TIMER_SP_WIDTH bfin_write_TIMER5_WIDTH
+#define bfin_write_TIMER_SP_PERIOD bfin_write_TIMER5_PERIOD
+#define TIMDIS_SP TIMDIS5
+#define TIMEN_SP TIMEN5
+
+#define bfin_write_TIMER_PS_CLS_CONFIG bfin_write_TIMER2_CONFIG
+#define bfin_write_TIMER_PS_CLS_WIDTH bfin_write_TIMER2_WIDTH
+#define bfin_write_TIMER_PS_CLS_PERIOD bfin_write_TIMER2_PERIOD
+#define TIMDIS_PS_CLS TIMDIS2
+#define TIMEN_PS_CLS TIMEN2
+
+#define bfin_write_TIMER_REV_CONFIG bfin_write_TIMER3_CONFIG
+#define bfin_write_TIMER_REV_WIDTH bfin_write_TIMER3_WIDTH
+#define bfin_write_TIMER_REV_PERIOD bfin_write_TIMER3_PERIOD
+#define TIMDIS_REV TIMDIS3
+#define TIMEN_REV TIMEN3
+#define bfin_read_TIMER_REV_COUNTER bfin_read_TIMER3_COUNTER
+
+#define FREQ_PPI_CLK (5*1024*1024) /* PPI_CLK 5MHz */
+
+#define TIMERS {P_TMR0, P_TMR1, P_TMR2, P_TMR3, P_TMR5, 0}
+
+#else
+
+#define UD GPIO_PF13 /* Up / Down */
+#define MOD GPIO_PF10
+#define LBR GPIO_PF14 /* Left Right */
+
+#define bfin_write_TIMER_LP_CONFIG bfin_write_TIMER6_CONFIG
+#define bfin_write_TIMER_LP_WIDTH bfin_write_TIMER6_WIDTH
+#define bfin_write_TIMER_LP_PERIOD bfin_write_TIMER6_PERIOD
+#define bfin_read_TIMER_LP_COUNTER bfin_read_TIMER6_COUNTER
+#define TIMDIS_LP TIMDIS6
+#define TIMEN_LP TIMEN6
+
+#define bfin_write_TIMER_SPS_CONFIG bfin_write_TIMER1_CONFIG
+#define bfin_write_TIMER_SPS_WIDTH bfin_write_TIMER1_WIDTH
+#define bfin_write_TIMER_SPS_PERIOD bfin_write_TIMER1_PERIOD
+#define TIMDIS_SPS TIMDIS1
+#define TIMEN_SPS TIMEN1
+
+#define bfin_write_TIMER_SP_CONFIG bfin_write_TIMER0_CONFIG
+#define bfin_write_TIMER_SP_WIDTH bfin_write_TIMER0_WIDTH
+#define bfin_write_TIMER_SP_PERIOD bfin_write_TIMER0_PERIOD
+#define TIMDIS_SP TIMDIS0
+#define TIMEN_SP TIMEN0
+
+#define bfin_write_TIMER_PS_CLS_CONFIG bfin_write_TIMER7_CONFIG
+#define bfin_write_TIMER_PS_CLS_WIDTH bfin_write_TIMER7_WIDTH
+#define bfin_write_TIMER_PS_CLS_PERIOD bfin_write_TIMER7_PERIOD
+#define TIMDIS_PS_CLS TIMDIS7
+#define TIMEN_PS_CLS TIMEN7
+
+#define bfin_write_TIMER_REV_CONFIG bfin_write_TIMER5_CONFIG
+#define bfin_write_TIMER_REV_WIDTH bfin_write_TIMER5_WIDTH
+#define bfin_write_TIMER_REV_PERIOD bfin_write_TIMER5_PERIOD
+#define TIMDIS_REV TIMDIS5
+#define TIMEN_REV TIMEN5
+#define bfin_read_TIMER_REV_COUNTER bfin_read_TIMER5_COUNTER
+
+#define FREQ_PPI_CLK (6*1000*1000) /* PPI_CLK 6MHz */
+#define TIMERS {P_TMR0, P_TMR1, P_TMR5, P_TMR6, P_TMR7, 0}
+
+#endif
+
+#define LCD_X_RES 240 /* Horizontal Resolution */
+#define LCD_Y_RES 320 /* Vertical Resolution */
+
+#define LCD_BBP 16 /* Bit Per Pixel */
+
+/* the LCD and the DMA start counting differently;
+ * since one starts at 0 and the other starts at 1,
+ * we have a difference of 1 between START_LINES
+ * and U_LINES.
+ */
+#define START_LINES 8 /* lines for field flyback or field blanking signal */
+#define U_LINES 9 /* number of undisplayed blanking lines */
+
+#define FRAMES_PER_SEC (60)
+
+#define DCLKS_PER_FRAME (FREQ_PPI_CLK/FRAMES_PER_SEC)
+#define DCLKS_PER_LINE (DCLKS_PER_FRAME/(LCD_Y_RES+U_LINES))
+
+#define PPI_CONFIG_VALUE (PORT_DIR|XFR_TYPE|DLEN_16|POLS)
+#define PPI_DELAY_VALUE (0)
+#define TIMER_CONFIG (PWM_OUT|PERIOD_CNT|TIN_SEL|CLK_SEL)
+
+#define ACTIVE_VIDEO_MEM_OFFSET (LCD_X_RES*START_LINES*(LCD_BBP/8))
+#define ACTIVE_VIDEO_MEM_SIZE (LCD_Y_RES*LCD_X_RES*(LCD_BBP/8))
+#define TOTAL_VIDEO_MEM_SIZE ((LCD_Y_RES+U_LINES)*LCD_X_RES*(LCD_BBP/8))
+#define TOTAL_DMA_DESC_SIZE (2 * sizeof(u32) * (LCD_Y_RES + U_LINES))
+
+static void start_timers(void) /* CHECK with HW */
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+
+ bfin_write_TIMER_ENABLE(TIMEN_REV);
+ SSYNC();
+
+ while (bfin_read_TIMER_REV_COUNTER() <= 11)
+ continue;
+ bfin_write_TIMER_ENABLE(TIMEN_LP);
+ SSYNC();
+
+ while (bfin_read_TIMER_LP_COUNTER() < 3)
+ continue;
+ bfin_write_TIMER_ENABLE(TIMEN_SP|TIMEN_SPS|TIMEN_PS_CLS);
+ SSYNC();
+ t_conf_done = 1;
+ local_irq_restore(flags);
+}
+
+static void config_timers(void)
+{
+ /* Stop timers */
+ bfin_write_TIMER_DISABLE(TIMDIS_SP|TIMDIS_SPS|TIMDIS_REV|
+ TIMDIS_LP|TIMDIS_PS_CLS);
+ SSYNC();
+
+ /* LP, timer 6 */
+ bfin_write_TIMER_LP_CONFIG(TIMER_CONFIG|PULSE_HI);
+ bfin_write_TIMER_LP_WIDTH(1);
+
+ bfin_write_TIMER_LP_PERIOD(DCLKS_PER_LINE);
+ SSYNC();
+
+ /* SPS, timer 1 */
+ bfin_write_TIMER_SPS_CONFIG(TIMER_CONFIG|PULSE_HI);
+ bfin_write_TIMER_SPS_WIDTH(DCLKS_PER_LINE*2);
+ bfin_write_TIMER_SPS_PERIOD((DCLKS_PER_LINE * (LCD_Y_RES+U_LINES)));
+ SSYNC();
+
+ /* SP, timer 0 */
+ bfin_write_TIMER_SP_CONFIG(TIMER_CONFIG|PULSE_HI);
+ bfin_write_TIMER_SP_WIDTH(1);
+ bfin_write_TIMER_SP_PERIOD(DCLKS_PER_LINE);
+ SSYNC();
+
+ /* PS & CLS, timer 7 */
+ bfin_write_TIMER_PS_CLS_CONFIG(TIMER_CONFIG);
+ bfin_write_TIMER_PS_CLS_WIDTH(LCD_X_RES + START_LINES);
+ bfin_write_TIMER_PS_CLS_PERIOD(DCLKS_PER_LINE);
+
+ SSYNC();
+
+#ifdef NO_BL
+ /* REV, timer 5 */
+ bfin_write_TIMER_REV_CONFIG(TIMER_CONFIG|PULSE_HI);
+
+ bfin_write_TIMER_REV_WIDTH(DCLKS_PER_LINE);
+ bfin_write_TIMER_REV_PERIOD(DCLKS_PER_LINE*2);
+
+ SSYNC();
+#endif
+}
+
+static void config_ppi(void)
+{
+ bfin_write_PPI_DELAY(PPI_DELAY_VALUE);
+ bfin_write_PPI_COUNT(LCD_X_RES-1);
+ /* 0x10 -> PORT_CFG -> 2 or 3 frame syncs */
+ bfin_write_PPI_CONTROL((PPI_CONFIG_VALUE|0x10) & (~POLS));
+}
+
+static int config_dma(void)
+{
+ u32 i;
+
+ if (landscape) {
+
+ for (i = 0; i < U_LINES; ++i) {
+ /* blanking lines point to first line of fb_buffer */
+ dma_desc_table[2*i] = (unsigned long)&dma_desc_table[2*i+2];
+ dma_desc_table[2*i+1] = (unsigned long)fb_buffer;
+ }
+
+ for (i = U_LINES; i < U_LINES + LCD_Y_RES; ++i) {
+ /* visible lines */
+ dma_desc_table[2*i] = (unsigned long)&dma_desc_table[2*i+2];
+ dma_desc_table[2*i+1] = (unsigned long)fb_buffer +
+ (LCD_Y_RES+U_LINES-1-i)*2;
+ }
+
+ /* last descriptor points to first */
+ dma_desc_table[2*(LCD_Y_RES+U_LINES-1)] = (unsigned long)&dma_desc_table[0];
+
+ set_dma_x_count(CH_PPI, LCD_X_RES);
+ set_dma_x_modify(CH_PPI, LCD_Y_RES * (LCD_BBP / 8));
+ set_dma_y_count(CH_PPI, 0);
+ set_dma_y_modify(CH_PPI, 0);
+ set_dma_next_desc_addr(CH_PPI, (void *)dma_desc_table[0]);
+ set_dma_config(CH_PPI, DMAFLOW_LARGE | NDSIZE_4 | WDSIZE_16);
+
+ } else {
+
+ set_dma_config(CH_PPI, set_bfin_dma_config(DIR_READ,
+ DMA_FLOW_AUTO,
+ INTR_DISABLE,
+ DIMENSION_2D,
+ DATA_SIZE_16,
+ DMA_NOSYNC_KEEP_DMA_BUF));
+ set_dma_x_count(CH_PPI, LCD_X_RES);
+ set_dma_x_modify(CH_PPI, LCD_BBP / 8);
+ set_dma_y_count(CH_PPI, LCD_Y_RES+U_LINES);
+ set_dma_y_modify(CH_PPI, LCD_BBP / 8);
+ set_dma_start_addr(CH_PPI, (unsigned long) fb_buffer);
+ }
+
+ return 0;
+}
+
+static int __devinit request_ports(void)
+{
+ u16 tmr_req[] = TIMERS;
+
+ /*
+ UD: PF13
+ MOD: PF10
+ LBR: PF14
+ PPI_CLK: PF15
+ */
+
+ if (peripheral_request_list(ppi_pins, KBUILD_MODNAME)) {
+ pr_err("requesting PPI peripheral failed\n");
+ return -EBUSY;
+ }
+
+ if (peripheral_request_list(tmr_req, KBUILD_MODNAME)) {
+ peripheral_free_list(ppi_pins);
+ pr_err("requesting timer peripheral failed\n");
+ return -EBUSY;
+ }
+
+#if (defined(UD) && defined(LBR))
+ if (gpio_request(UD, KBUILD_MODNAME)) {
+ pr_err("requesting GPIO %d failed\n", UD);
+ return -EBUSY;
+ }
+
+ if (gpio_request(LBR, KBUILD_MODNAME)) {
+ pr_err("requesting GPIO %d failed\n", LBR);
+ gpio_free(UD);
+ return -EBUSY;
+ }
+
+ gpio_direction_output(UD, 0);
+ gpio_direction_output(LBR, 1);
+
+#endif
+
+ if (gpio_request(MOD, KBUILD_MODNAME)) {
+ pr_err("requesting GPIO %d failed\n", MOD);
+#if (defined(UD) && defined(LBR))
+ gpio_free(LBR);
+ gpio_free(UD);
+#endif
+ return -EBUSY;
+ }
+
+ gpio_direction_output(MOD, 1);
+
+ SSYNC();
+ return 0;
+}
+
+static void free_ports(void)
+{
+ u16 tmr_req[] = TIMERS;
+
+ peripheral_free_list(ppi_pins);
+ peripheral_free_list(tmr_req);
+
+#if defined(UD) && defined(LBR)
+ gpio_free(LBR);
+ gpio_free(UD);
+#endif
+ gpio_free(MOD);
+}
+
+static struct fb_info bfin_lq035_fb;
+
+static struct fb_var_screeninfo bfin_lq035_fb_defined = {
+ .bits_per_pixel = LCD_BBP,
+ .activate = FB_ACTIVATE_TEST,
+ .xres = LCD_X_RES, /*default portrait mode RGB*/
+ .yres = LCD_Y_RES,
+ .xres_virtual = LCD_X_RES,
+ .yres_virtual = LCD_Y_RES,
+ .height = -1,
+ .width = -1,
+ .left_margin = 0,
+ .right_margin = 0,
+ .upper_margin = 0,
+ .lower_margin = 0,
+ .red = {11, 5, 0},
+ .green = {5, 6, 0},
+ .blue = {0, 5, 0},
+ .transp = {0, 0, 0},
+};
+
+static struct fb_fix_screeninfo bfin_lq035_fb_fix __devinitdata = {
+ .id = KBUILD_MODNAME,
+ .smem_len = ACTIVE_VIDEO_MEM_SIZE,
+ .type = FB_TYPE_PACKED_PIXELS,
+ .visual = FB_VISUAL_TRUECOLOR,
+ .xpanstep = 0,
+ .ypanstep = 0,
+ .line_length = LCD_X_RES*(LCD_BBP/8),
+ .accel = FB_ACCEL_NONE,
+};
+
+
+static int bfin_lq035_fb_open(struct fb_info *info, int user)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&bfin_lq035_lock, flags);
+ lq035_open_cnt++;
+ spin_unlock_irqrestore(&bfin_lq035_lock, flags);
+
+ if (lq035_open_cnt <= 1) {
+ bfin_write_PPI_CONTROL(0);
+ SSYNC();
+
+ set_vcomm();
+ config_dma();
+ config_ppi();
+
+ /* start dma */
+ enable_dma(CH_PPI);
+ SSYNC();
+ bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN);
+ SSYNC();
+
+ if (!t_conf_done) {
+ config_timers();
+ start_timers();
+ }
+ /* gpio_set_value(MOD,1); */
+ }
+
+ return 0;
+}
+
+static int bfin_lq035_fb_release(struct fb_info *info, int user)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&bfin_lq035_lock, flags);
+ lq035_open_cnt--;
+ spin_unlock_irqrestore(&bfin_lq035_lock, flags);
+
+
+ if (lq035_open_cnt <= 0) {
+
+ bfin_write_PPI_CONTROL(0);
+ SSYNC();
+
+ disable_dma(CH_PPI);
+ }
+
+ return 0;
+}
+
+
+static int bfin_lq035_fb_check_var(struct fb_var_screeninfo *var,
+ struct fb_info *info)
+{
+ switch (var->bits_per_pixel) {
+ case 16:/* DIRECTCOLOUR, 64k */
+ var->red.offset = info->var.red.offset;
+ var->green.offset = info->var.green.offset;
+ var->blue.offset = info->var.blue.offset;
+ var->red.length = info->var.red.length;
+ var->green.length = info->var.green.length;
+ var->blue.length = info->var.blue.length;
+ var->transp.offset = 0;
+ var->transp.length = 0;
+ var->transp.msb_right = 0;
+ var->red.msb_right = 0;
+ var->green.msb_right = 0;
+ var->blue.msb_right = 0;
+ break;
+ default:
+ pr_debug("%s: depth not supported: %u BPP\n", __func__,
+ var->bits_per_pixel);
+ return -EINVAL;
+ }
+
+ if (info->var.xres != var->xres ||
+ info->var.yres != var->yres ||
+ info->var.xres_virtual != var->xres_virtual ||
+ info->var.yres_virtual != var->yres_virtual) {
+ pr_debug("%s: Resolution not supported: X%u x Y%u\n",
+ __func__, var->xres, var->yres);
+ return -EINVAL;
+ }
+
+ /*
+ * Memory limit
+ */
+
+ if ((info->fix.line_length * var->yres_virtual) > info->fix.smem_len) {
+ pr_debug("%s: Memory Limit requested yres_virtual = %u\n",
+ __func__, var->yres_virtual);
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+/* fb_rotate
+ * Rotate the display of this angle. This doesn't seems to be used by the core,
+ * but as our hardware supports it, so why not implementing it...
+ */
+static void bfin_lq035_fb_rotate(struct fb_info *fbi, int angle)
+{
+ pr_debug("%s: %p %d", __func__, fbi, angle);
+#if (defined(UD) && defined(LBR))
+ switch (angle) {
+
+ case 180:
+ gpio_set_value(LBR, 0);
+ gpio_set_value(UD, 1);
+ break;
+ default:
+ gpio_set_value(LBR, 1);
+ gpio_set_value(UD, 0);
+ break;
+ }
+#endif
+}
+
+static int bfin_lq035_fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
+{
+ if (nocursor)
+ return 0;
+ else
+ return -EINVAL; /* just to force soft_cursor() call */
+}
+
+static int bfin_lq035_fb_setcolreg(u_int regno, u_int red, u_int green,
+ u_int blue, u_int transp,
+ struct fb_info *info)
+{
+ if (regno >= NBR_PALETTE)
+ return -EINVAL;
+
+ if (info->var.grayscale)
+ /* grayscale = 0.30*R + 0.59*G + 0.11*B */
+ red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
+
+ if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
+
+ u32 value;
+ /* Place color in the pseudopalette */
+ if (regno > 16)
+ return -EINVAL;
+
+ red >>= (16 - info->var.red.length);
+ green >>= (16 - info->var.green.length);
+ blue >>= (16 - info->var.blue.length);
+
+ value = (red << info->var.red.offset) |
+ (green << info->var.green.offset)|
+ (blue << info->var.blue.offset);
+ value &= 0xFFFF;
+
+ ((u32 *) (info->pseudo_palette))[regno] = value;
+
+ }
+
+ return 0;
+}
+
+static struct fb_ops bfin_lq035_fb_ops = {
+ .owner = THIS_MODULE,
+ .fb_open = bfin_lq035_fb_open,
+ .fb_release = bfin_lq035_fb_release,
+ .fb_check_var = bfin_lq035_fb_check_var,
+ .fb_rotate = bfin_lq035_fb_rotate,
+ .fb_fillrect = cfb_fillrect,
+ .fb_copyarea = cfb_copyarea,
+ .fb_imageblit = cfb_imageblit,
+ .fb_cursor = bfin_lq035_fb_cursor,
+ .fb_setcolreg = bfin_lq035_fb_setcolreg,
+};
+
+static int bl_get_brightness(struct backlight_device *bd)
+{
+ return current_brightness;
+}
+
+static const struct backlight_ops bfin_lq035fb_bl_ops = {
+ .get_brightness = bl_get_brightness,
+};
+
+static struct backlight_device *bl_dev;
+
+static int bfin_lcd_get_power(struct lcd_device *dev)
+{
+ return 0;
+}
+
+static int bfin_lcd_set_power(struct lcd_device *dev, int power)
+{
+ return 0;
+}
+
+static int bfin_lcd_get_contrast(struct lcd_device *dev)
+{
+ return (int)vcomm_value;
+}
+
+static int bfin_lcd_set_contrast(struct lcd_device *dev, int contrast)
+{
+ if (contrast > 255)
+ contrast = 255;
+ if (contrast < 0)
+ contrast = 0;
+
+ vcomm_value = (unsigned char)contrast;
+ set_vcomm();
+ return 0;
+}
+
+static int bfin_lcd_check_fb(struct lcd_device *lcd, struct fb_info *fi)
+{
+ if (!fi || (fi == &bfin_lq035_fb))
+ return 1;
+ return 0;
+}
+
+static struct lcd_ops bfin_lcd_ops = {
+ .get_power = bfin_lcd_get_power,
+ .set_power = bfin_lcd_set_power,
+ .get_contrast = bfin_lcd_get_contrast,
+ .set_contrast = bfin_lcd_set_contrast,
+ .check_fb = bfin_lcd_check_fb,
+};
+
+static struct lcd_device *lcd_dev;
+
+static int __devinit bfin_lq035_probe(struct platform_device *pdev)
+{
+ struct backlight_properties props;
+ dma_addr_t dma_handle;
+
+ if (request_dma(CH_PPI, KBUILD_MODNAME)) {
+ pr_err("couldn't request PPI DMA\n");
+ return -EFAULT;
+ }
+
+ if (request_ports()) {
+ pr_err("couldn't request gpio port\n");
+ free_dma(CH_PPI);
+ return -EFAULT;
+ }
+
+ fb_buffer = dma_alloc_coherent(NULL, TOTAL_VIDEO_MEM_SIZE,
+ &dma_handle, GFP_KERNEL);
+ if (fb_buffer == NULL) {
+ pr_err("couldn't allocate dma buffer\n");
+ free_dma(CH_PPI);
+ free_ports();
+ return -ENOMEM;
+ }
+
+ if (L1_DATA_A_LENGTH)
+ dma_desc_table = l1_data_sram_zalloc(TOTAL_DMA_DESC_SIZE);
+ else
+ dma_desc_table = dma_alloc_coherent(NULL, TOTAL_DMA_DESC_SIZE,
+ &dma_handle, 0);
+
+ if (dma_desc_table == NULL) {
+ pr_err("couldn't allocate dma descriptor\n");
+ free_dma(CH_PPI);
+ free_ports();
+ dma_free_coherent(NULL, TOTAL_VIDEO_MEM_SIZE, fb_buffer, 0);
+ return -ENOMEM;
+ }
+
+ bfin_lq035_fb.screen_base = (void *)fb_buffer;
+ bfin_lq035_fb_fix.smem_start = (int)fb_buffer;
+ if (landscape) {
+ bfin_lq035_fb_defined.xres = LCD_Y_RES;
+ bfin_lq035_fb_defined.yres = LCD_X_RES;
+ bfin_lq035_fb_defined.xres_virtual = LCD_Y_RES;
+ bfin_lq035_fb_defined.yres_virtual = LCD_X_RES;
+
+ bfin_lq035_fb_fix.line_length = LCD_Y_RES*(LCD_BBP/8);
+ } else {
+ bfin_lq035_fb.screen_base += ACTIVE_VIDEO_MEM_OFFSET;
+ bfin_lq035_fb_fix.smem_start += ACTIVE_VIDEO_MEM_OFFSET;
+ }
+
+ bfin_lq035_fb_defined.green.msb_right = 0;
+ bfin_lq035_fb_defined.red.msb_right = 0;
+ bfin_lq035_fb_defined.blue.msb_right = 0;
+ bfin_lq035_fb_defined.green.offset = 5;
+ bfin_lq035_fb_defined.green.length = 6;
+ bfin_lq035_fb_defined.red.length = 5;
+ bfin_lq035_fb_defined.blue.length = 5;
+
+ if (bgr) {
+ bfin_lq035_fb_defined.red.offset = 0;
+ bfin_lq035_fb_defined.blue.offset = 11;
+ } else {
+ bfin_lq035_fb_defined.red.offset = 11;
+ bfin_lq035_fb_defined.blue.offset = 0;
+ }
+
+ bfin_lq035_fb.fbops = &bfin_lq035_fb_ops;
+ bfin_lq035_fb.var = bfin_lq035_fb_defined;
+
+ bfin_lq035_fb.fix = bfin_lq035_fb_fix;
+ bfin_lq035_fb.flags = FBINFO_DEFAULT;
+
+
+ bfin_lq035_fb.pseudo_palette = kzalloc(sizeof(u32) * 16, GFP_KERNEL);
+ if (bfin_lq035_fb.pseudo_palette == NULL) {
+ pr_err("failed to allocate pseudo_palette\n");
+ free_dma(CH_PPI);
+ free_ports();
+ dma_free_coherent(NULL, TOTAL_VIDEO_MEM_SIZE, fb_buffer, 0);
+ return -ENOMEM;
+ }
+
+ if (fb_alloc_cmap(&bfin_lq035_fb.cmap, NBR_PALETTE, 0) < 0) {
+ pr_err("failed to allocate colormap (%d entries)\n",
+ NBR_PALETTE);
+ free_dma(CH_PPI);
+ free_ports();
+ dma_free_coherent(NULL, TOTAL_VIDEO_MEM_SIZE, fb_buffer, 0);
+ kfree(bfin_lq035_fb.pseudo_palette);
+ return -EFAULT;
+ }
+
+ if (register_framebuffer(&bfin_lq035_fb) < 0) {
+ pr_err("unable to register framebuffer\n");
+ free_dma(CH_PPI);
+ free_ports();
+ dma_free_coherent(NULL, TOTAL_VIDEO_MEM_SIZE, fb_buffer, 0);
+ fb_buffer = NULL;
+ kfree(bfin_lq035_fb.pseudo_palette);
+ fb_dealloc_cmap(&bfin_lq035_fb.cmap);
+ return -EINVAL;
+ }
+
+ i2c_add_driver(&ad5280_driver);
+
+ memset(&props, 0, sizeof(props));
+ props.max_brightness = MAX_BRIGHENESS;
+ bl_dev = backlight_device_register("bf537-bl", NULL, NULL,
+ &bfin_lq035fb_bl_ops, &props);
+
+ lcd_dev = lcd_device_register(KBUILD_MODNAME, &pdev->dev, NULL,
+ &bfin_lcd_ops);
+ lcd_dev->props.max_contrast = 255,
+
+ pr_info("initialized");
+
+ return 0;
+}
+
+static int __devexit bfin_lq035_remove(struct platform_device *pdev)
+{
+ if (fb_buffer != NULL)
+ dma_free_coherent(NULL, TOTAL_VIDEO_MEM_SIZE, fb_buffer, 0);
+
+ if (L1_DATA_A_LENGTH)
+ l1_data_sram_free(dma_desc_table);
+ else
+ dma_free_coherent(NULL, TOTAL_DMA_DESC_SIZE, NULL, 0);
+
+ bfin_write_TIMER_DISABLE(TIMEN_SP|TIMEN_SPS|TIMEN_PS_CLS|
+ TIMEN_LP|TIMEN_REV);
+ t_conf_done = 0;
+
+ free_dma(CH_PPI);
+
+
+ kfree(bfin_lq035_fb.pseudo_palette);
+ fb_dealloc_cmap(&bfin_lq035_fb.cmap);
+
+
+ lcd_device_unregister(lcd_dev);
+ backlight_device_unregister(bl_dev);
+
+ unregister_framebuffer(&bfin_lq035_fb);
+ i2c_del_driver(&ad5280_driver);
+
+ free_ports();
+
+ pr_info("unregistered LCD driver\n");
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int bfin_lq035_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ if (lq035_open_cnt > 0) {
+ bfin_write_PPI_CONTROL(0);
+ SSYNC();
+ disable_dma(CH_PPI);
+ }
+
+ return 0;
+}
+
+static int bfin_lq035_resume(struct platform_device *pdev)
+{
+ if (lq035_open_cnt > 0) {
+ bfin_write_PPI_CONTROL(0);
+ SSYNC();
+
+ config_dma();
+ config_ppi();
+
+ enable_dma(CH_PPI);
+ bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN);
+ SSYNC();
+
+ config_timers();
+ start_timers();
+ } else {
+ t_conf_done = 0;
+ }
+
+ return 0;
+}
+#else
+# define bfin_lq035_suspend NULL
+# define bfin_lq035_resume NULL
+#endif
+
+static struct platform_driver bfin_lq035_driver = {
+ .probe = bfin_lq035_probe,
+ .remove = __devexit_p(bfin_lq035_remove),
+ .suspend = bfin_lq035_suspend,
+ .resume = bfin_lq035_resume,
+ .driver = {
+ .name = KBUILD_MODNAME,
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init bfin_lq035_driver_init(void)
+{
+ request_module("i2c-bfin-twi");
+ return platform_driver_register(&bfin_lq035_driver);
+}
+module_init(bfin_lq035_driver_init);
+
+static void __exit bfin_lq035_driver_cleanup(void)
+{
+ platform_driver_unregister(&bfin_lq035_driver);
+}
+module_exit(bfin_lq035_driver_cleanup);
+
+MODULE_DESCRIPTION("SHARP LQ035Q7DB03 TFT LCD Driver");
+MODULE_LICENSE("GPL");
--- /dev/null
+/*
+ * Frame buffer driver for ADV7393/2 video encoder
+ *
+ * Copyright 2006-2009 Analog Devices Inc.
+ * Licensed under the GPL-2 or late.
+ */
+
+/*
+ * TODO: Remove Globals
+ * TODO: Code Cleanup
+ */
+
+#define pr_fmt(fmt) DRIVER_NAME ": " fmt
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/tty.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/fb.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/sched.h>
+#include <asm/blackfin.h>
+#include <asm/irq.h>
+#include <asm/dma.h>
+#include <linux/uaccess.h>
+#include <linux/gpio.h>
+#include <asm/portmux.h>
+
+#include <linux/dma-mapping.h>
+#include <linux/proc_fs.h>
+#include <linux/platform_device.h>
+
+#include <linux/i2c.h>
+#include <linux/i2c-dev.h>
+
+#include "bfin_adv7393fb.h"
+
+static int mode = VMODE;
+static int mem = VMEM;
+static int nocursor = 1;
+
+static const unsigned short ppi_pins[] = {
+ P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
+ P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
+ P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
+ P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
+ P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
+ 0
+};
+
+/*
+ * card parameters
+ */
+
+static struct bfin_adv7393_fb_par {
+ /* structure holding blackfin / adv7393 paramters when
+ screen is blanked */
+ struct {
+ u8 Mode; /* ntsc/pal/? */
+ } vga_state;
+ atomic_t ref_count;
+} bfin_par;
+
+/* --------------------------------------------------------------------- */
+
+static struct fb_var_screeninfo bfin_adv7393_fb_defined = {
+ .xres = 720,
+ .yres = 480,
+ .xres_virtual = 720,
+ .yres_virtual = 480,
+ .bits_per_pixel = 16,
+ .activate = FB_ACTIVATE_TEST,
+ .height = -1,
+ .width = -1,
+ .left_margin = 0,
+ .right_margin = 0,
+ .upper_margin = 0,
+ .lower_margin = 0,
+ .vmode = FB_VMODE_INTERLACED,
+ .red = {11, 5, 0},
+ .green = {5, 6, 0},
+ .blue = {0, 5, 0},
+ .transp = {0, 0, 0},
+};
+
+static struct fb_fix_screeninfo bfin_adv7393_fb_fix __devinitdata = {
+ .id = "BFIN ADV7393",
+ .smem_len = 720 * 480 * 2,
+ .type = FB_TYPE_PACKED_PIXELS,
+ .visual = FB_VISUAL_TRUECOLOR,
+ .xpanstep = 0,
+ .ypanstep = 0,
+ .line_length = 720 * 2,
+ .accel = FB_ACCEL_NONE
+};
+
+static struct fb_ops bfin_adv7393_fb_ops = {
+ .owner = THIS_MODULE,
+ .fb_open = bfin_adv7393_fb_open,
+ .fb_release = bfin_adv7393_fb_release,
+ .fb_check_var = bfin_adv7393_fb_check_var,
+ .fb_pan_display = bfin_adv7393_fb_pan_display,
+ .fb_blank = bfin_adv7393_fb_blank,
+ .fb_fillrect = cfb_fillrect,
+ .fb_copyarea = cfb_copyarea,
+ .fb_imageblit = cfb_imageblit,
+ .fb_cursor = bfin_adv7393_fb_cursor,
+ .fb_setcolreg = bfin_adv7393_fb_setcolreg,
+};
+
+static int dma_desc_list(struct adv7393fb_device *fbdev, u16 arg)
+{
+ if (arg == BUILD) { /* Build */
+ fbdev->vb1 = l1_data_sram_zalloc(sizeof(struct dmasg));
+ if (fbdev->vb1 == NULL)
+ goto error;
+
+ fbdev->av1 = l1_data_sram_zalloc(sizeof(struct dmasg));
+ if (fbdev->av1 == NULL)
+ goto error;
+
+ fbdev->vb2 = l1_data_sram_zalloc(sizeof(struct dmasg));
+ if (fbdev->vb2 == NULL)
+ goto error;
+
+ fbdev->av2 = l1_data_sram_zalloc(sizeof(struct dmasg));
+ if (fbdev->av2 == NULL)
+ goto error;
+
+ /* Build linked DMA descriptor list */
+ fbdev->vb1->next_desc_addr = fbdev->av1;
+ fbdev->av1->next_desc_addr = fbdev->vb2;
+ fbdev->vb2->next_desc_addr = fbdev->av2;
+ fbdev->av2->next_desc_addr = fbdev->vb1;
+
+ /* Save list head */
+ fbdev->descriptor_list_head = fbdev->av2;
+
+ /* Vertical Blanking Field 1 */
+ fbdev->vb1->start_addr = VB_DUMMY_MEMORY_SOURCE;
+ fbdev->vb1->cfg = DMA_CFG_VAL;
+
+ fbdev->vb1->x_count =
+ fbdev->modes[mode].xres + fbdev->modes[mode].boeft_blank;
+
+ fbdev->vb1->x_modify = 0;
+ fbdev->vb1->y_count = fbdev->modes[mode].vb1_lines;
+ fbdev->vb1->y_modify = 0;
+
+ /* Active Video Field 1 */
+
+ fbdev->av1->start_addr = (unsigned long)fbdev->fb_mem;
+ fbdev->av1->cfg = DMA_CFG_VAL;
+ fbdev->av1->x_count =
+ fbdev->modes[mode].xres + fbdev->modes[mode].boeft_blank;
+ fbdev->av1->x_modify = fbdev->modes[mode].bpp / 8;
+ fbdev->av1->y_count = fbdev->modes[mode].a_lines;
+ fbdev->av1->y_modify =
+ (fbdev->modes[mode].xres - fbdev->modes[mode].boeft_blank +
+ 1) * (fbdev->modes[mode].bpp / 8);
+
+ /* Vertical Blanking Field 2 */
+
+ fbdev->vb2->start_addr = VB_DUMMY_MEMORY_SOURCE;
+ fbdev->vb2->cfg = DMA_CFG_VAL;
+ fbdev->vb2->x_count =
+ fbdev->modes[mode].xres + fbdev->modes[mode].boeft_blank;
+
+ fbdev->vb2->x_modify = 0;
+ fbdev->vb2->y_count = fbdev->modes[mode].vb2_lines;
+ fbdev->vb2->y_modify = 0;
+
+ /* Active Video Field 2 */
+
+ fbdev->av2->start_addr =
+ (unsigned long)fbdev->fb_mem + fbdev->line_len;
+
+ fbdev->av2->cfg = DMA_CFG_VAL;
+
+ fbdev->av2->x_count =
+ fbdev->modes[mode].xres + fbdev->modes[mode].boeft_blank;
+
+ fbdev->av2->x_modify = (fbdev->modes[mode].bpp / 8);
+ fbdev->av2->y_count = fbdev->modes[mode].a_lines;
+
+ fbdev->av2->y_modify =
+ (fbdev->modes[mode].xres - fbdev->modes[mode].boeft_blank +
+ 1) * (fbdev->modes[mode].bpp / 8);
+
+ return 1;
+ }
+
+error:
+ l1_data_sram_free(fbdev->vb1);
+ l1_data_sram_free(fbdev->av1);
+ l1_data_sram_free(fbdev->vb2);
+ l1_data_sram_free(fbdev->av2);
+
+ return 0;
+}
+
+static int bfin_config_dma(struct adv7393fb_device *fbdev)
+{
+ BUG_ON(!(fbdev->fb_mem));
+
+ set_dma_x_count(CH_PPI, fbdev->descriptor_list_head->x_count);
+ set_dma_x_modify(CH_PPI, fbdev->descriptor_list_head->x_modify);
+ set_dma_y_count(CH_PPI, fbdev->descriptor_list_head->y_count);
+ set_dma_y_modify(CH_PPI, fbdev->descriptor_list_head->y_modify);
+ set_dma_start_addr(CH_PPI, fbdev->descriptor_list_head->start_addr);
+ set_dma_next_desc_addr(CH_PPI,
+ fbdev->descriptor_list_head->next_desc_addr);
+ set_dma_config(CH_PPI, fbdev->descriptor_list_head->cfg);
+
+ return 1;
+}
+
+static void bfin_disable_dma(void)
+{
+ bfin_write_DMA0_CONFIG(bfin_read_DMA0_CONFIG() & ~DMAEN);
+}
+
+static void bfin_config_ppi(struct adv7393fb_device *fbdev)
+{
+ if (ANOMALY_05000183) {
+ bfin_write_TIMER2_CONFIG(WDTH_CAP);
+ bfin_write_TIMER_ENABLE(TIMEN2);
+ }
+
+ bfin_write_PPI_CONTROL(0x381E);
+ bfin_write_PPI_FRAME(fbdev->modes[mode].tot_lines);
+ bfin_write_PPI_COUNT(fbdev->modes[mode].xres +
+ fbdev->modes[mode].boeft_blank - 1);
+ bfin_write_PPI_DELAY(fbdev->modes[mode].aoeft_blank - 1);
+}
+
+static void bfin_enable_ppi(void)
+{
+ bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN);
+}
+
+static void bfin_disable_ppi(void)
+{
+ bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() & ~PORT_EN);
+}
+
+static inline int adv7393_write(struct i2c_client *client, u8 reg, u8 value)
+{
+ return i2c_smbus_write_byte_data(client, reg, value);
+}
+
+static inline int adv7393_read(struct i2c_client *client, u8 reg)
+{
+ return i2c_smbus_read_byte_data(client, reg);
+}
+
+static int
+adv7393_write_block(struct i2c_client *client,
+ const u8 *data, unsigned int len)
+{
+ int ret = -1;
+ u8 reg;
+
+ while (len >= 2) {
+ reg = *data++;
+ ret = adv7393_write(client, reg, *data++);
+ if (ret < 0)
+ break;
+ len -= 2;
+ }
+
+ return ret;
+}
+
+static int adv7393_mode(struct i2c_client *client, u16 mode)
+{
+ switch (mode) {
+ case POWER_ON: /* ADV7393 Sleep mode OFF */
+ adv7393_write(client, 0x00, 0x1E);
+ break;
+ case POWER_DOWN: /* ADV7393 Sleep mode ON */
+ adv7393_write(client, 0x00, 0x1F);
+ break;
+ case BLANK_OFF: /* Pixel Data Valid */
+ adv7393_write(client, 0x82, 0xCB);
+ break;
+ case BLANK_ON: /* Pixel Data Invalid */
+ adv7393_write(client, 0x82, 0x8B);
+ break;
+ default:
+ return -EINVAL;
+ break;
+ }
+ return 0;
+}
+
+static irqreturn_t ppi_irq_error(int irq, void *dev_id)
+{
+
+ struct adv7393fb_device *fbdev = (struct adv7393fb_device *)dev_id;
+
+ u16 status = bfin_read_PPI_STATUS();
+
+ pr_debug("%s: PPI Status = 0x%X\n", __func__, status);
+
+ if (status) {
+ bfin_disable_dma(); /* TODO: Check Sequence */
+ bfin_disable_ppi();
+ bfin_clear_PPI_STATUS();
+ bfin_config_dma(fbdev);
+ bfin_enable_ppi();
+ }
+
+ return IRQ_HANDLED;
+
+}
+
+static int proc_output(char *buf)
+{
+ char *p = buf;
+
+ p += sprintf(p,
+ "Usage:\n"
+ "echo 0x[REG][Value] > adv7393\n"
+ "example: echo 0x1234 >adv7393\n"
+ "writes 0x34 into Register 0x12\n");
+
+ return p - buf;
+}
+
+static int
+adv7393_read_proc(char *page, char **start, off_t off,
+ int count, int *eof, void *data)
+{
+ int len;
+
+ len = proc_output(page);
+ if (len <= off + count)
+ *eof = 1;
+ *start = page + off;
+ len -= off;
+ if (len > count)
+ len = count;
+ if (len < 0)
+ len = 0;
+ return len;
+}
+
+static int
+adv7393_write_proc(struct file *file, const char __user * buffer,
+ unsigned long count, void *data)
+{
+ struct adv7393fb_device *fbdev = data;
+ char line[8];
+ unsigned int val;
+ int ret;
+
+ ret = copy_from_user(line, buffer, count);
+ if (ret)
+ return -EFAULT;
+
+ val = simple_strtoul(line, NULL, 0);
+ adv7393_write(fbdev->client, val >> 8, val & 0xff);
+
+ return count;
+}
+
+static int __devinit bfin_adv7393_fb_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ int ret = 0;
+ struct proc_dir_entry *entry;
+ int num_modes = ARRAY_SIZE(known_modes);
+
+ struct adv7393fb_device *fbdev = NULL;
+
+ if (mem > 2) {
+ dev_err(&client->dev, "mem out of allowed range [1;2]\n");
+ return -EINVAL;
+ }
+
+ if (mode > num_modes) {
+ dev_err(&client->dev, "mode %d: not supported", mode);
+ return -EFAULT;
+ }
+
+ fbdev = kzalloc(sizeof(*fbdev), GFP_KERNEL);
+ if (!fbdev) {
+ dev_err(&client->dev, "failed to allocate device private record");
+ return -ENOMEM;
+ }
+
+ i2c_set_clientdata(client, fbdev);
+
+ fbdev->modes = known_modes;
+ fbdev->client = client;
+
+ fbdev->fb_len =
+ mem * fbdev->modes[mode].xres * fbdev->modes[mode].xres *
+ (fbdev->modes[mode].bpp / 8);
+
+ fbdev->line_len =
+ fbdev->modes[mode].xres * (fbdev->modes[mode].bpp / 8);
+
+ /* Workaround "PPI Does Not Start Properly In Specific Mode" */
+ if (ANOMALY_05000400) {
+ if (gpio_request(P_IDENT(P_PPI0_FS3), "PPI0_FS3")) {
+ dev_err(&client->dev, "PPI0_FS3 GPIO request failed\n");
+ ret = -EBUSY;
+ goto out_8;
+ }
+ gpio_direction_output(P_IDENT(P_PPI0_FS3), 0);
+ }
+
+ if (peripheral_request_list(ppi_pins, DRIVER_NAME)) {
+ dev_err(&client->dev, "requesting PPI peripheral failed\n");
+ ret = -EFAULT;
+ goto out_8;
+ }
+
+ fbdev->fb_mem =
+ dma_alloc_coherent(NULL, fbdev->fb_len, &fbdev->dma_handle,
+ GFP_KERNEL);
+
+ if (NULL == fbdev->fb_mem) {
+ dev_err(&client->dev, "couldn't allocate dma buffer (%d bytes)\n",
+ (u32) fbdev->fb_len);
+ ret = -ENOMEM;
+ goto out_7;
+ }
+
+ fbdev->info.screen_base = (void *)fbdev->fb_mem;
+ bfin_adv7393_fb_fix.smem_start = (int)fbdev->fb_mem;
+
+ bfin_adv7393_fb_fix.smem_len = fbdev->fb_len;
+ bfin_adv7393_fb_fix.line_length = fbdev->line_len;
+
+ if (mem > 1)
+ bfin_adv7393_fb_fix.ypanstep = 1;
+
+ bfin_adv7393_fb_defined.red.length = 5;
+ bfin_adv7393_fb_defined.green.length = 6;
+ bfin_adv7393_fb_defined.blue.length = 5;
+
+ bfin_adv7393_fb_defined.xres = fbdev->modes[mode].xres;
+ bfin_adv7393_fb_defined.yres = fbdev->modes[mode].yres;
+ bfin_adv7393_fb_defined.xres_virtual = fbdev->modes[mode].xres;
+ bfin_adv7393_fb_defined.yres_virtual = mem * fbdev->modes[mode].yres;
+ bfin_adv7393_fb_defined.bits_per_pixel = fbdev->modes[mode].bpp;
+
+ fbdev->info.fbops = &bfin_adv7393_fb_ops;
+ fbdev->info.var = bfin_adv7393_fb_defined;
+ fbdev->info.fix = bfin_adv7393_fb_fix;
+ fbdev->info.par = &bfin_par;
+ fbdev->info.flags = FBINFO_DEFAULT;
+
+ fbdev->info.pseudo_palette = kzalloc(sizeof(u32) * 16, GFP_KERNEL);
+ if (!fbdev->info.pseudo_palette) {
+ dev_err(&client->dev, "failed to allocate pseudo_palette\n");
+ ret = -ENOMEM;
+ goto out_6;
+ }
+
+ if (fb_alloc_cmap(&fbdev->info.cmap, BFIN_LCD_NBR_PALETTE_ENTRIES, 0) < 0) {
+ dev_err(&client->dev, "failed to allocate colormap (%d entries)\n",
+ BFIN_LCD_NBR_PALETTE_ENTRIES);
+ ret = -EFAULT;
+ goto out_5;
+ }
+
+ if (request_dma(CH_PPI, "BF5xx_PPI_DMA") < 0) {
+ dev_err(&client->dev, "unable to request PPI DMA\n");
+ ret = -EFAULT;
+ goto out_4;
+ }
+
+ if (request_irq(IRQ_PPI_ERROR, ppi_irq_error, IRQF_DISABLED,
+ "PPI ERROR", fbdev) < 0) {
+ dev_err(&client->dev, "unable to request PPI ERROR IRQ\n");
+ ret = -EFAULT;
+ goto out_3;
+ }
+
+ fbdev->open = 0;
+
+ ret = adv7393_write_block(client, fbdev->modes[mode].adv7393_i2c_initd,
+ fbdev->modes[mode].adv7393_i2c_initd_len);
+
+ if (ret) {
+ dev_err(&client->dev, "i2c attach: init error\n");
+ goto out_1;
+ }
+
+
+ if (register_framebuffer(&fbdev->info) < 0) {
+ dev_err(&client->dev, "unable to register framebuffer\n");
+ ret = -EFAULT;
+ goto out_1;
+ }
+
+ dev_info(&client->dev, "fb%d: %s frame buffer device\n",
+ fbdev->info.node, fbdev->info.fix.id);
+ dev_info(&client->dev, "fb memory address : 0x%p\n", fbdev->fb_mem);
+
+ entry = create_proc_entry("driver/adv7393", 0, NULL);
+ if (!entry) {
+ dev_err(&client->dev, "unable to create /proc entry\n");
+ ret = -EFAULT;
+ goto out_0;
+ }
+
+ entry->read_proc = adv7393_read_proc;
+ entry->write_proc = adv7393_write_proc;
+ entry->data = fbdev;
+
+ return 0;
+
+ out_0:
+ unregister_framebuffer(&fbdev->info);
+ out_1:
+ free_irq(IRQ_PPI_ERROR, fbdev);
+ out_3:
+ free_dma(CH_PPI);
+ out_4:
+ dma_free_coherent(NULL, fbdev->fb_len, fbdev->fb_mem,
+ fbdev->dma_handle);
+ out_5:
+ fb_dealloc_cmap(&fbdev->info.cmap);
+ out_6:
+ kfree(fbdev->info.pseudo_palette);
+ out_7:
+ peripheral_free_list(ppi_pins);
+ out_8:
+ kfree(fbdev);
+
+ return ret;
+}
+
+static int bfin_adv7393_fb_open(struct fb_info *info, int user)
+{
+ struct adv7393fb_device *fbdev = to_adv7393fb_device(info);
+
+ fbdev->info.screen_base = (void *)fbdev->fb_mem;
+ if (!fbdev->info.screen_base) {
+ dev_err(&fbdev->client->dev, "unable to map device\n");
+ return -ENOMEM;
+ }
+
+ fbdev->open = 1;
+ dma_desc_list(fbdev, BUILD);
+ adv7393_mode(fbdev->client, BLANK_OFF);
+ bfin_config_ppi(fbdev);
+ bfin_config_dma(fbdev);
+ bfin_enable_ppi();
+
+ return 0;
+}
+
+static int bfin_adv7393_fb_release(struct fb_info *info, int user)
+{
+ struct adv7393fb_device *fbdev = to_adv7393fb_device(info);
+
+ adv7393_mode(fbdev->client, BLANK_ON);
+ bfin_disable_dma();
+ bfin_disable_ppi();
+ dma_desc_list(fbdev, DESTRUCT);
+ fbdev->open = 0;
+ return 0;
+}
+
+static int
+bfin_adv7393_fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
+{
+
+ switch (var->bits_per_pixel) {
+ case 16:/* DIRECTCOLOUR, 64k */
+ var->red.offset = info->var.red.offset;
+ var->green.offset = info->var.green.offset;
+ var->blue.offset = info->var.blue.offset;
+ var->red.length = info->var.red.length;
+ var->green.length = info->var.green.length;
+ var->blue.length = info->var.blue.length;
+ var->transp.offset = 0;
+ var->transp.length = 0;
+ var->transp.msb_right = 0;
+ var->red.msb_right = 0;
+ var->green.msb_right = 0;
+ var->blue.msb_right = 0;
+ break;
+ default:
+ pr_debug("%s: depth not supported: %u BPP\n", __func__,
+ var->bits_per_pixel);
+ return -EINVAL;
+ }
+
+ if (info->var.xres != var->xres ||
+ info->var.yres != var->yres ||
+ info->var.xres_virtual != var->xres_virtual ||
+ info->var.yres_virtual != var->yres_virtual) {
+ pr_debug("%s: Resolution not supported: X%u x Y%u\n",
+ __func__, var->xres, var->yres);
+ return -EINVAL;
+ }
+
+ /*
+ * Memory limit
+ */
+
+ if ((info->fix.line_length * var->yres_virtual) > info->fix.smem_len) {
+ pr_debug("%s: Memory Limit requested yres_virtual = %u\n",
+ __func__, var->yres_virtual);
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+static int
+bfin_adv7393_fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
+{
+ int dy;
+ u32 dmaaddr;
+ struct adv7393fb_device *fbdev = to_adv7393fb_device(info);
+
+ if (!var || !info)
+ return -EINVAL;
+
+ if (var->xoffset - info->var.xoffset) {
+ /* No support for X panning for now! */
+ return -EINVAL;
+ }
+ dy = var->yoffset - info->var.yoffset;
+
+ if (dy) {
+ pr_debug("%s: Panning screen of %d lines\n", __func__, dy);
+
+ dmaaddr = fbdev->av1->start_addr;
+ dmaaddr += (info->fix.line_length * dy);
+ /* TODO: Wait for current frame to finished */
+
+ fbdev->av1->start_addr = (unsigned long)dmaaddr;
+ fbdev->av2->start_addr = (unsigned long)dmaaddr + fbdev->line_len;
+ }
+
+ return 0;
+
+}
+
+/* 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off */
+static int bfin_adv7393_fb_blank(int blank, struct fb_info *info)
+{
+ struct adv7393fb_device *fbdev = to_adv7393fb_device(info);
+
+ switch (blank) {
+
+ case VESA_NO_BLANKING:
+ /* Turn on panel */
+ adv7393_mode(fbdev->client, BLANK_OFF);
+ break;
+
+ case VESA_VSYNC_SUSPEND:
+ case VESA_HSYNC_SUSPEND:
+ case VESA_POWERDOWN:
+ /* Turn off panel */
+ adv7393_mode(fbdev->client, BLANK_ON);
+ break;
+
+ default:
+ return -EINVAL;
+ break;
+ }
+ return 0;
+}
+
+int bfin_adv7393_fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
+{
+ if (nocursor)
+ return 0;
+ else
+ return -EINVAL; /* just to force soft_cursor() call */
+}
+
+static int bfin_adv7393_fb_setcolreg(u_int regno, u_int red, u_int green,
+ u_int blue, u_int transp,
+ struct fb_info *info)
+{
+ if (regno >= BFIN_LCD_NBR_PALETTE_ENTRIES)
+ return -EINVAL;
+
+ if (info->var.grayscale)
+ /* grayscale = 0.30*R + 0.59*G + 0.11*B */
+ red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
+
+ if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
+ u32 value;
+ /* Place color in the pseudopalette */
+ if (regno > 16)
+ return -EINVAL;
+
+ red >>= (16 - info->var.red.length);
+ green >>= (16 - info->var.green.length);
+ blue >>= (16 - info->var.blue.length);
+
+ value = (red << info->var.red.offset) |
+ (green << info->var.green.offset)|
+ (blue << info->var.blue.offset);
+ value &= 0xFFFF;
+
+ ((u32 *) (info->pseudo_palette))[regno] = value;
+ }
+
+ return 0;
+}
+
+static int __devexit bfin_adv7393_fb_remove(struct i2c_client *client)
+{
+ struct adv7393fb_device *fbdev = i2c_get_clientdata(client);
+
+ adv7393_mode(client, POWER_DOWN);
+
+ if (fbdev->fb_mem)
+ dma_free_coherent(NULL, fbdev->fb_len, fbdev->fb_mem, fbdev->dma_handle);
+ free_dma(CH_PPI);
+ free_irq(IRQ_PPI_ERROR, fbdev);
+ unregister_framebuffer(&fbdev->info);
+ remove_proc_entry("driver/adv7393", NULL);
+ fb_dealloc_cmap(&fbdev->info.cmap);
+ kfree(fbdev->info.pseudo_palette);
+
+ if (ANOMALY_05000400)
+ gpio_free(P_IDENT(P_PPI0_FS3)); /* FS3 */
+ peripheral_free_list(ppi_pins);
+ kfree(fbdev);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int bfin_adv7393_fb_suspend(struct device *dev)
+{
+ struct adv7393fb_device *fbdev = dev_get_drvdata(dev);
+
+ if (fbdev->open) {
+ bfin_disable_dma();
+ bfin_disable_ppi();
+ dma_desc_list(fbdev, DESTRUCT);
+ }
+ adv7393_mode(fbdev->client, POWER_DOWN);
+
+ return 0;
+}
+
+static int bfin_adv7393_fb_resume(struct device *dev)
+{
+ struct adv7393fb_device *fbdev = dev_get_drvdata(dev);
+
+ adv7393_mode(fbdev->client, POWER_ON);
+
+ if (fbdev->open) {
+ dma_desc_list(fbdev, BUILD);
+ bfin_config_ppi(fbdev);
+ bfin_config_dma(fbdev);
+ bfin_enable_ppi();
+ }
+
+ return 0;
+}
+
+static const struct dev_pm_ops bfin_adv7393_dev_pm_ops = {
+ .suspend = bfin_adv7393_fb_suspend,
+ .resume = bfin_adv7393_fb_resume,
+};
+#endif
+
+static const struct i2c_device_id bfin_adv7393_id[] = {
+ {DRIVER_NAME, 0},
+ {}
+};
+
+MODULE_DEVICE_TABLE(i2c, bfin_adv7393_id);
+
+static struct i2c_driver bfin_adv7393_fb_driver = {
+ .driver = {
+ .name = DRIVER_NAME,
+#ifdef CONFIG_PM
+ .pm = &bfin_adv7393_dev_pm_ops,
+#endif
+ },
+ .probe = bfin_adv7393_fb_probe,
+ .remove = __devexit_p(bfin_adv7393_fb_remove),
+ .id_table = bfin_adv7393_id,
+};
+
+static int __init bfin_adv7393_fb_driver_init(void)
+{
+#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+ request_module("i2c-bfin-twi");
+#else
+ request_module("i2c-gpio");
+#endif
+
+ return i2c_add_driver(&bfin_adv7393_fb_driver);
+}
+module_init(bfin_adv7393_fb_driver_init);
+
+static void __exit bfin_adv7393_fb_driver_cleanup(void)
+{
+ i2c_del_driver(&bfin_adv7393_fb_driver);
+}
+module_exit(bfin_adv7393_fb_driver_cleanup);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
+MODULE_DESCRIPTION("Frame buffer driver for ADV7393/2 Video Encoder");
+
+module_param(mode, int, 0);
+MODULE_PARM_DESC(mode,
+ "Video Mode (0=NTSC,1=PAL,2=NTSC 640x480,3=PAL 640x480,4=NTSC YCbCr input,5=PAL YCbCr input)");
+
+module_param(mem, int, 0);
+MODULE_PARM_DESC(mem,
+ "Size of frame buffer memory 1=Single 2=Double Size (allows y-panning / frame stacking)");
+
+module_param(nocursor, int, 0644);
+MODULE_PARM_DESC(nocursor, "cursor enable/disable");
--- /dev/null
+/*
+ * Frame buffer driver for ADV7393/2 video encoder
+ *
+ * Copyright 2006-2009 Analog Devices Inc.
+ * Licensed under the GPL-2 or late.
+ */
+
+#ifndef __BFIN_ADV7393FB_H__
+#define __BFIN_ADV7393FB_H__
+
+#define BFIN_LCD_NBR_PALETTE_ENTRIES 256
+
+#ifdef CONFIG_NTSC
+# define VMODE 0
+#endif
+#ifdef CONFIG_PAL
+# define VMODE 1
+#endif
+#ifdef CONFIG_NTSC_640x480
+# define VMODE 2
+#endif
+#ifdef CONFIG_PAL_640x480
+# define VMODE 3
+#endif
+#ifdef CONFIG_NTSC_YCBCR
+# define VMODE 4
+#endif
+#ifdef CONFIG_PAL_YCBCR
+# define VMODE 5
+#endif
+
+#ifndef VMODE
+# define VMODE 1
+#endif
+
+#ifdef CONFIG_ADV7393_2XMEM
+# define VMEM 2
+#else
+# define VMEM 1
+#endif
+
+#if defined(CONFIG_BF537) || defined(CONFIG_BF536) || defined(CONFIG_BF534)
+# define DMA_CFG_VAL 0x7935 /* Set Sync Bit */
+# define VB_DUMMY_MEMORY_SOURCE L1_DATA_B_START
+#else
+# define DMA_CFG_VAL 0x7915
+# define VB_DUMMY_MEMORY_SOURCE BOOT_ROM_START
+#endif
+
+enum {
+ DESTRUCT,
+ BUILD,
+};
+
+enum {
+ POWER_ON,
+ POWER_DOWN,
+ BLANK_ON,
+ BLANK_OFF,
+};
+
+#define DRIVER_NAME "bfin-adv7393"
+
+struct adv7393fb_modes {
+ const s8 name[25]; /* Full name */
+ u16 xres; /* Active Horizonzal Pixels */
+ u16 yres; /* Active Vertical Pixels */
+ u16 bpp;
+ u16 vmode;
+ u16 a_lines; /* Active Lines per Field */
+ u16 vb1_lines; /* Vertical Blanking Field 1 Lines */
+ u16 vb2_lines; /* Vertical Blanking Field 2 Lines */
+ u16 tot_lines; /* Total Lines per Frame */
+ u16 boeft_blank; /* Before Odd/Even Field Transition No. of Blank Pixels */
+ u16 aoeft_blank; /* After Odd/Even Field Transition No. of Blank Pixels */
+ const s8 *adv7393_i2c_initd;
+ u16 adv7393_i2c_initd_len;
+};
+
+static const u8 init_NTSC_TESTPATTERN[] = {
+ 0x00, 0x1E, /* Power up all DACs and PLL */
+ 0x01, 0x00, /* SD-Only Mode */
+ 0x80, 0x10, /* SSAF Luma Filter Enabled, NTSC Mode */
+ 0x82, 0xCB, /* Step control on, pixel data valid, pedestal on, PrPb SSAF on, CVBS/YC output */
+ 0x84, 0x40, /* SD Color Bar Test Pattern Enabled, DAC 2 = Luma, DAC 3 = Chroma */
+};
+
+static const u8 init_NTSC[] = {
+ 0x00, 0x1E, /* Power up all DACs and PLL */
+ 0xC3, 0x26, /* Program RGB->YCrCb Color Space convertion matrix */
+ 0xC5, 0x12, /* Program RGB->YCrCb Color Space convertion matrix */
+ 0xC2, 0x4A, /* Program RGB->YCrCb Color Space convertion matrix */
+ 0xC6, 0x5E, /* Program RGB->YCrCb Color Space convertion matrix */
+ 0xBD, 0x19, /* Program RGB->YCrCb Color Space convertion matrix */
+ 0xBF, 0x42, /* Program RGB->YCrCb Color Space convertion matrix */
+ 0x8C, 0x1F, /* NTSC Subcarrier Frequency */
+ 0x8D, 0x7C, /* NTSC Subcarrier Frequency */
+ 0x8E, 0xF0, /* NTSC Subcarrier Frequency */
+ 0x8F, 0x21, /* NTSC Subcarrier Frequency */
+ 0x01, 0x00, /* SD-Only Mode */
+ 0x80, 0x30, /* SSAF Luma Filter Enabled, NTSC Mode */
+ 0x82, 0x8B, /* Step control on, pixel data invalid, pedestal on, PrPb SSAF on, CVBS/YC output */
+ 0x87, 0x80, /* SD Color Bar Test Pattern Enabled, DAC 2 = Luma, DAC 3 = Chroma */
+ 0x86, 0x82,
+ 0x8B, 0x11,
+ 0x88, 0x20,
+ 0x8A, 0x0d,
+};
+
+static const u8 init_PAL[] = {
+ 0x00, 0x1E, /* Power up all DACs and PLL */
+ 0xC3, 0x26, /* Program RGB->YCrCb Color Space convertion matrix */
+ 0xC5, 0x12, /* Program RGB->YCrCb Color Space convertion matrix */
+ 0xC2, 0x4A, /* Program RGB->YCrCb Color Space convertion matrix */
+ 0xC6, 0x5E, /* Program RGB->YCrCb Color Space convertion matrix */
+ 0xBD, 0x19, /* Program RGB->YCrCb Color Space convertion matrix */
+ 0xBF, 0x42, /* Program RGB->YCrCb Color Space convertion matrix */
+ 0x8C, 0xCB, /* PAL Subcarrier Frequency */
+ 0x8D, 0x8A, /* PAL Subcarrier Frequency */
+ 0x8E, 0x09, /* PAL Subcarrier Frequency */
+ 0x8F, 0x2A, /* PAL Subcarrier Frequency */
+ 0x01, 0x00, /* SD-Only Mode */
+ 0x80, 0x11, /* SSAF Luma Filter Enabled, PAL Mode */
+ 0x82, 0x8B, /* Step control on, pixel data invalid, pedestal on, PrPb SSAF on, CVBS/YC output */
+ 0x87, 0x80, /* SD Color Bar Test Pattern Enabled, DAC 2 = Luma, DAC 3 = Chroma */
+ 0x86, 0x82,
+ 0x8B, 0x11,
+ 0x88, 0x20,
+ 0x8A, 0x0d,
+};
+
+static const u8 init_NTSC_YCbCr[] = {
+ 0x00, 0x1E, /* Power up all DACs and PLL */
+ 0x8C, 0x1F, /* NTSC Subcarrier Frequency */
+ 0x8D, 0x7C, /* NTSC Subcarrier Frequency */
+ 0x8E, 0xF0, /* NTSC Subcarrier Frequency */
+ 0x8F, 0x21, /* NTSC Subcarrier Frequency */
+ 0x01, 0x00, /* SD-Only Mode */
+ 0x80, 0x30, /* SSAF Luma Filter Enabled, NTSC Mode */
+ 0x82, 0x8B, /* Step control on, pixel data invalid, pedestal on, PrPb SSAF on, CVBS/YC output */
+ 0x87, 0x00, /* DAC 2 = Luma, DAC 3 = Chroma */
+ 0x86, 0x82,
+ 0x8B, 0x11,
+ 0x88, 0x08,
+ 0x8A, 0x0d,
+};
+
+static const u8 init_PAL_YCbCr[] = {
+ 0x00, 0x1E, /* Power up all DACs and PLL */
+ 0x8C, 0xCB, /* PAL Subcarrier Frequency */
+ 0x8D, 0x8A, /* PAL Subcarrier Frequency */
+ 0x8E, 0x09, /* PAL Subcarrier Frequency */
+ 0x8F, 0x2A, /* PAL Subcarrier Frequency */
+ 0x01, 0x00, /* SD-Only Mode */
+ 0x80, 0x11, /* SSAF Luma Filter Enabled, PAL Mode */
+ 0x82, 0x8B, /* Step control on, pixel data invalid, pedestal on, PrPb SSAF on, CVBS/YC output */
+ 0x87, 0x00, /* DAC 2 = Luma, DAC 3 = Chroma */
+ 0x86, 0x82,
+ 0x8B, 0x11,
+ 0x88, 0x08,
+ 0x8A, 0x0d,
+};
+
+static struct adv7393fb_modes known_modes[] = {
+ /* NTSC 720x480 CRT */
+ {
+ .name = "NTSC 720x480",
+ .xres = 720,
+ .yres = 480,
+ .bpp = 16,
+ .vmode = FB_VMODE_INTERLACED,
+ .a_lines = 240,
+ .vb1_lines = 22,
+ .vb2_lines = 23,
+ .tot_lines = 525,
+ .boeft_blank = 16,
+ .aoeft_blank = 122,
+ .adv7393_i2c_initd = init_NTSC,
+ .adv7393_i2c_initd_len = sizeof(init_NTSC)
+ },
+ /* PAL 720x480 CRT */
+ {
+ .name = "PAL 720x576",
+ .xres = 720,
+ .yres = 576,
+ .bpp = 16,
+ .vmode = FB_VMODE_INTERLACED,
+ .a_lines = 288,
+ .vb1_lines = 24,
+ .vb2_lines = 25,
+ .tot_lines = 625,
+ .boeft_blank = 12,
+ .aoeft_blank = 132,
+ .adv7393_i2c_initd = init_PAL,
+ .adv7393_i2c_initd_len = sizeof(init_PAL)
+ },
+ /* NTSC 640x480 CRT Experimental */
+ {
+ .name = "NTSC 640x480",
+ .xres = 640,
+ .yres = 480,
+ .bpp = 16,
+ .vmode = FB_VMODE_INTERLACED,
+ .a_lines = 240,
+ .vb1_lines = 22,
+ .vb2_lines = 23,
+ .tot_lines = 525,
+ .boeft_blank = 16 + 40,
+ .aoeft_blank = 122 + 40,
+ .adv7393_i2c_initd = init_NTSC,
+ .adv7393_i2c_initd_len = sizeof(init_NTSC)
+ },
+ /* PAL 640x480 CRT Experimental */
+ {
+ .name = "PAL 640x480",
+ .xres = 640,
+ .yres = 480,
+ .bpp = 16,
+ .vmode = FB_VMODE_INTERLACED,
+ .a_lines = 288 - 20,
+ .vb1_lines = 24 + 20,
+ .vb2_lines = 25 + 20,
+ .tot_lines = 625,
+ .boeft_blank = 12 + 40,
+ .aoeft_blank = 132 + 40,
+ .adv7393_i2c_initd = init_PAL,
+ .adv7393_i2c_initd_len = sizeof(init_PAL)
+ },
+ /* NTSC 720x480 YCbCR */
+ {
+ .name = "NTSC 720x480 YCbCR",
+ .xres = 720,
+ .yres = 480,
+ .bpp = 16,
+ .vmode = FB_VMODE_INTERLACED,
+ .a_lines = 240,
+ .vb1_lines = 22,
+ .vb2_lines = 23,
+ .tot_lines = 525,
+ .boeft_blank = 16,
+ .aoeft_blank = 122,
+ .adv7393_i2c_initd = init_NTSC_YCbCr,
+ .adv7393_i2c_initd_len = sizeof(init_NTSC_YCbCr)
+ },
+ /* PAL 720x480 CRT */
+ {
+ .name = "PAL 720x576 YCbCR",
+ .xres = 720,
+ .yres = 576,
+ .bpp = 16,
+ .vmode = FB_VMODE_INTERLACED,
+ .a_lines = 288,
+ .vb1_lines = 24,
+ .vb2_lines = 25,
+ .tot_lines = 625,
+ .boeft_blank = 12,
+ .aoeft_blank = 132,
+ .adv7393_i2c_initd = init_PAL_YCbCr,
+ .adv7393_i2c_initd_len = sizeof(init_PAL_YCbCr)
+ }
+};
+
+struct adv7393fb_regs {
+
+};
+
+struct adv7393fb_device {
+ struct fb_info info; /* FB driver info record */
+
+ struct i2c_client *client;
+
+ struct dmasg *descriptor_list_head;
+ struct dmasg *vb1;
+ struct dmasg *av1;
+ struct dmasg *vb2;
+ struct dmasg *av2;
+
+ dma_addr_t dma_handle;
+
+ struct fb_info bfin_adv7393_fb;
+
+ struct adv7393fb_modes *modes;
+
+ struct adv7393fb_regs *regs; /* Registers memory map */
+ size_t regs_len;
+ size_t fb_len;
+ size_t line_len;
+ u16 open;
+ u16 *fb_mem; /* RGB Buffer */
+
+};
+
+#define to_adv7393fb_device(_info) \
+ (_info ? container_of(_info, struct adv7393fb_device, info) : NULL);
+
+static int bfin_adv7393_fb_open(struct fb_info *info, int user);
+static int bfin_adv7393_fb_release(struct fb_info *info, int user);
+static int bfin_adv7393_fb_check_var(struct fb_var_screeninfo *var,
+ struct fb_info *info);
+
+static int bfin_adv7393_fb_pan_display(struct fb_var_screeninfo *var,
+ struct fb_info *info);
+
+static int bfin_adv7393_fb_blank(int blank, struct fb_info *info);
+
+static void bfin_config_ppi(struct adv7393fb_device *fbdev);
+static int bfin_config_dma(struct adv7393fb_device *fbdev);
+static void bfin_disable_dma(void);
+static void bfin_enable_ppi(void);
+static void bfin_disable_ppi(void);
+
+static inline int adv7393_write(struct i2c_client *client, u8 reg, u8 value);
+static inline int adv7393_read(struct i2c_client *client, u8 reg);
+static int adv7393_write_block(struct i2c_client *client, const u8 *data,
+ unsigned int len);
+
+int bfin_adv7393_fb_cursor(struct fb_info *info, struct fb_cursor *cursor);
+static int bfin_adv7393_fb_setcolreg(u_int, u_int, u_int, u_int,
+ u_int, struct fb_info *info);
+
+#endif
printk(KERN_ERR "carminefb: Memory bar is only %d bytes, %d "
"are required.", carminefb_fix.smem_len,
CARMINE_TOTAL_DIPLAY_MEM);
- goto err_free_reg_mmio;
+ goto err_unmap_vregs;
}
if (!request_mem_region(carminefb_fix.smem_start,
carminefb_fix.smem_len);
if (!hw->screen_mem) {
printk(KERN_ERR "carmine: Can't ioremap smem area.\n");
- release_mem_region(carminefb_fix.smem_start,
- carminefb_fix.smem_len);
goto err_reg_smem;
}
err_unmap_screen:
iounmap(hw->screen_mem);
err_reg_smem:
- release_mem_region(carminefb_fix.mmio_start, carminefb_fix.mmio_len);
+ release_mem_region(carminefb_fix.smem_start, carminefb_fix.smem_len);
err_unmap_vregs:
iounmap(hw->v_regs);
err_free_reg_mmio:
DPRINTK("========================================\n");
}
+/**
+ * fb_edid_add_monspecs() - add monitor video modes from E-EDID data
+ * @edid: 128 byte array with an E-EDID block
+ * @spacs: monitor specs to be extended
+ */
+void fb_edid_add_monspecs(unsigned char *edid, struct fb_monspecs *specs)
+{
+ unsigned char *block;
+ struct fb_videomode *m;
+ int num = 0, i;
+ u8 svd[64], edt[(128 - 4) / DETAILED_TIMING_DESCRIPTION_SIZE];
+ u8 pos = 4, svd_n = 0;
+
+ if (!edid)
+ return;
+
+ if (!edid_checksum(edid))
+ return;
+
+ if (edid[0] != 0x2 ||
+ edid[2] < 4 || edid[2] > 128 - DETAILED_TIMING_DESCRIPTION_SIZE)
+ return;
+
+ DPRINTK(" Short Video Descriptors\n");
+
+ while (pos < edid[2]) {
+ u8 len = edid[pos] & 0x1f, type = (edid[pos] >> 5) & 7;
+ pr_debug("Data block %u of %u bytes\n", type, len);
+ if (type == 2)
+ for (i = pos; i < pos + len; i++) {
+ u8 idx = edid[pos + i] & 0x7f;
+ svd[svd_n++] = idx;
+ pr_debug("N%sative mode #%d\n",
+ edid[pos + i] & 0x80 ? "" : "on-n", idx);
+ }
+ pos += len + 1;
+ }
+
+ block = edid + edid[2];
+
+ DPRINTK(" Extended Detailed Timings\n");
+
+ for (i = 0; i < (128 - edid[2]) / DETAILED_TIMING_DESCRIPTION_SIZE;
+ i++, block += DETAILED_TIMING_DESCRIPTION_SIZE)
+ if (PIXEL_CLOCK)
+ edt[num++] = block - edid;
+
+ /* Yikes, EDID data is totally useless */
+ if (!(num + svd_n))
+ return;
+
+ m = kzalloc((specs->modedb_len + num + svd_n) *
+ sizeof(struct fb_videomode), GFP_KERNEL);
+
+ if (!m)
+ return;
+
+ memcpy(m, specs->modedb, specs->modedb_len * sizeof(struct fb_videomode));
+
+ for (i = specs->modedb_len; i < specs->modedb_len + num; i++) {
+ get_detailed_timing(edid + edt[i - specs->modedb_len], &m[i]);
+ if (i == specs->modedb_len)
+ m[i].flag |= FB_MODE_IS_FIRST;
+ pr_debug("Adding %ux%u@%u\n", m[i].xres, m[i].yres, m[i].refresh);
+ }
+
+ for (i = specs->modedb_len + num; i < specs->modedb_len + num + svd_n; i++) {
+ int idx = svd[i - specs->modedb_len - num];
+ if (!idx || idx > 63) {
+ pr_warning("Reserved SVD code %d\n", idx);
+ } else if (idx > ARRAY_SIZE(cea_modes) || !cea_modes[idx].xres) {
+ pr_warning("Unimplemented SVD code %d\n", idx);
+ } else {
+ memcpy(&m[i], cea_modes + idx, sizeof(m[i]));
+ pr_debug("Adding SVD #%d: %ux%u@%u\n", idx,
+ m[i].xres, m[i].yres, m[i].refresh);
+ }
+ }
+
+ kfree(specs->modedb);
+ specs->modedb = m;
+ specs->modedb_len = specs->modedb_len + num + svd_n;
+}
+
/*
* VESA Generalized Timing Formula (GTF)
*/
{
specs = NULL;
}
+void fb_edid_add_monspecs(unsigned char *edid, struct fb_monspecs *specs)
+{
+}
void fb_destroy_modedb(struct fb_videomode *modedb)
{
}
EXPORT_SYMBOL(fb_parse_edid);
EXPORT_SYMBOL(fb_edid_to_monspecs);
+EXPORT_SYMBOL(fb_edid_add_monspecs);
EXPORT_SYMBOL(fb_get_mode);
EXPORT_SYMBOL(fb_validate_mode);
EXPORT_SYMBOL(fb_destroy_modedb);
/*
* Accel functions
*/
-#ifdef CONFIG_FB_HGA_ACCEL
static void hgafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
u_int rows, y;
dest = rowaddr(info, y) + (rect->dx >> 3);
switch (rect->rop) {
case ROP_COPY:
- //fb_memset(dest, rect->color, (rect->width >> 3));
+ memset_io(dest, rect->color, (rect->width >> 3));
break;
case ROP_XOR:
fb_writeb(~(fb_readb(dest)), dest);
for (rows = area->height; rows--; ) {
src = rowaddr(info, y1) + (area->sx >> 3);
dest = rowaddr(info, y2) + (area->dx >> 3);
- //fb_memmove(dest, src, (area->width >> 3));
+ memmove(dest, src, (area->width >> 3));
y1++;
y2++;
}
for (rows = area->height; rows--;) {
src = rowaddr(info, y1) + (area->sx >> 3);
dest = rowaddr(info, y2) + (area->dx >> 3);
- //fb_memmove(dest, src, (area->width >> 3));
+ memmove(dest, src, (area->width >> 3));
y1--;
y2--;
}
u8 __iomem *dest;
u8 *cdat = (u8 *) image->data;
u_int rows, y = image->dy;
+ u_int x;
u8 d;
for (rows = image->height; rows--; y++) {
- d = *cdat++;
- dest = rowaddr(info, y) + (image->dx >> 3);
- fb_writeb(d, dest);
+ for (x = 0; x < image->width; x+= 8) {
+ d = *cdat++;
+ dest = rowaddr(info, y) + ((image->dx + x)>> 3);
+ fb_writeb(d, dest);
+ }
}
}
-#else /* !CONFIG_FB_HGA_ACCEL */
-#define hgafb_fillrect cfb_fillrect
-#define hgafb_copyarea cfb_copyarea
-#define hgafb_imageblit cfb_imageblit
-#endif /* CONFIG_FB_HGA_ACCEL */
-
static struct fb_ops hgafb_ops = {
.owner = THIS_MODULE,
struct i810fb_par *par = chan->par;
u8 __iomem *mmio = par->mmio_start_virtual;
- i810_writel(mmio, chan->ddc_base, (state ? SCL_VAL_OUT : 0) | SCL_DIR |
- SCL_DIR_MASK | SCL_VAL_MASK);
+ if (state)
+ i810_writel(mmio, chan->ddc_base, SCL_DIR_MASK | SCL_VAL_MASK);
+ else
+ i810_writel(mmio, chan->ddc_base, SCL_DIR | SCL_DIR_MASK | SCL_VAL_MASK);
i810_readl(mmio, chan->ddc_base); /* flush posted write */
}
struct i810fb_par *par = chan->par;
u8 __iomem *mmio = par->mmio_start_virtual;
- i810_writel(mmio, chan->ddc_base, (state ? SDA_VAL_OUT : 0) | SDA_DIR |
- SDA_DIR_MASK | SDA_VAL_MASK);
+ if (state)
+ i810_writel(mmio, chan->ddc_base, SDA_DIR_MASK | SDA_VAL_MASK);
+ else
+ i810_writel(mmio, chan->ddc_base, SDA_DIR | SDA_DIR_MASK | SDA_VAL_MASK);
i810_readl(mmio, chan->ddc_base); /* flush posted write */
}
/* 800x520i @ 50 Hz, 15.625 kHz hsync (PAL RGB) */
NULL, 50, 800, 520, 58823, 144, 64, 72, 28, 80, 5,
0, FB_VMODE_INTERLACED
+ }, {
+ /* 864x480 @ 60 Hz, 35.15 kHz hsync */
+ NULL, 60, 864, 480, 27777, 1, 1, 1, 1, 0, 0,
+ 0, FB_VMODE_NONINTERLACED
},
};
#ifdef CONFIG_FB_MODE_HELPERS
+const struct fb_videomode cea_modes[64] = {
+ /* #1: 640x480p@59.94/60Hz */
+ [1] = {
+ NULL, 60, 640, 480, 39722, 48, 16, 33, 10, 96, 2, 0, FB_VMODE_NONINTERLACED, 0,
+ },
+ /* #3: 720x480p@59.94/60Hz */
+ [3] = {
+ NULL, 60, 720, 480, 37037, 60, 16, 30, 9, 62, 6, 0, FB_VMODE_NONINTERLACED, 0,
+ },
+ /* #5: 1920x1080i@59.94/60Hz */
+ [5] = {
+ NULL, 60, 1920, 1080, 13763, 148, 88, 15, 2, 44, 5,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_INTERLACED, 0,
+ },
+ /* #7: 720(1440)x480iH@59.94/60Hz */
+ [7] = {
+ NULL, 60, 1440, 480, 18554/*37108*/, 114, 38, 15, 4, 124, 3, 0, FB_VMODE_INTERLACED, 0,
+ },
+ /* #9: 720(1440)x240pH@59.94/60Hz */
+ [9] = {
+ NULL, 60, 1440, 240, 18554, 114, 38, 16, 4, 124, 3, 0, FB_VMODE_NONINTERLACED, 0,
+ },
+ /* #18: 720x576pH@50Hz */
+ [18] = {
+ NULL, 50, 720, 576, 37037, 68, 12, 39, 5, 64, 5, 0, FB_VMODE_NONINTERLACED, 0,
+ },
+ /* #19: 1280x720p@50Hz */
+ [19] = {
+ NULL, 50, 1280, 720, 13468, 220, 440, 20, 5, 40, 5,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, 0,
+ },
+ /* #20: 1920x1080i@50Hz */
+ [20] = {
+ NULL, 50, 1920, 1080, 13480, 148, 528, 15, 5, 528, 5,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_INTERLACED, 0,
+ },
+ /* #32: 1920x1080p@23.98/24Hz */
+ [32] = {
+ NULL, 24, 1920, 1080, 13468, 148, 638, 36, 4, 44, 5,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, 0,
+ },
+ /* #35: (2880)x480p4x@59.94/60Hz */
+ [35] = {
+ NULL, 60, 2880, 480, 9250, 240, 64, 30, 9, 248, 6, 0, FB_VMODE_NONINTERLACED, 0,
+ },
+};
+
const struct fb_videomode vesa_modes[] = {
/* 0 640x350-85 VESA */
{ NULL, 85, 640, 350, 31746, 96, 32, 60, 32, 64, 3,
goto eremap;
}
- pr_debug("Remapped %x to %x at %p\n", sdc_reg->start, sdc_reg->end,
- mx3fb->reg_base);
+ pr_debug("Remapped %pR at %p\n", sdc_reg, mx3fb->reg_base);
/* IDMAC interface */
dmaengine_get();
functions to handle bitblt acceleration
************************************************************/
-/**
- * bltbit_wait_bitset - waits for change in register value
- * @info : framebuffer structure
- * @bit : value expected in register
- * @timeout : ...
- *
- * waits until value changes INTO bit
- */
-static u8
-bltbit_wait_bitset(struct fb_info *info, u8 bit, int timeout)
-{
- while (!(s1d13xxxfb_readreg(info->par, S1DREG_BBLT_CTL0) & bit)) {
- udelay(10);
- if (!--timeout) {
- dbg_blit("wait_bitset timeout\n");
- break;
- }
- }
-
- return timeout;
-}
-
/**
* bltbit_wait_bitclear - waits for change in register value
* @info : frambuffer structure
return timeout;
}
-/**
- * bltbit_fifo_status - checks the current status of the fifo
- * @info : framebuffer structure
- *
- * returns number of free words in buffer
- */
-static u8
-bltbit_fifo_status(struct fb_info *info)
-{
- u8 status;
-
- status = s1d13xxxfb_readreg(info->par, S1DREG_BBLT_CTL0);
-
- /* its empty so room for 16 words */
- if (status & BBLT_FIFO_EMPTY)
- return 16;
-
- /* its full so we dont want to add */
- if (status & BBLT_FIFO_FULL)
- return 0;
-
- /* its atleast half full but we can add one atleast */
- if (status & BBLT_FIFO_NOT_FULL)
- return 1;
-
- return 0;
-}
-
/*
* s1d13xxxfb_bitblt_copyarea - accelerated copyarea function
* @info : framebuffer structure
#include <linux/io.h>
#include <linux/uaccess.h>
#include <linux/interrupt.h>
+#include <linux/pm_runtime.h>
#include <mach/map.h>
#include <plat/regs-fb-v4.h>
return ret;
}
+static int s3c_fb_open(struct fb_info *info, int user)
+{
+ struct s3c_fb_win *win = info->par;
+ struct s3c_fb *sfb = win->parent;
+
+ pm_runtime_get_sync(sfb->dev);
+
+ return 0;
+}
+
+static int s3c_fb_release(struct fb_info *info, int user)
+{
+ struct s3c_fb_win *win = info->par;
+ struct s3c_fb *sfb = win->parent;
+
+ pm_runtime_put_sync(sfb->dev);
+
+ return 0;
+}
+
static struct fb_ops s3c_fb_ops = {
.owner = THIS_MODULE,
+ .fb_open = s3c_fb_open,
+ .fb_release = s3c_fb_release,
.fb_check_var = s3c_fb_check_var,
.fb_set_par = s3c_fb_set_par,
.fb_blank = s3c_fb_blank,
clk_enable(sfb->bus_clk);
+ pm_runtime_enable(sfb->dev);
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(dev, "failed to find registers\n");
dev_dbg(dev, "got resources (regs %p), probing windows\n", sfb->regs);
+ platform_set_drvdata(pdev, sfb);
+ pm_runtime_get_sync(sfb->dev);
+
/* setup gpio and output polarity controls */
pd->setup_gpio();
}
platform_set_drvdata(pdev, sfb);
+ pm_runtime_put_sync(sfb->dev);
return 0;
struct s3c_fb *sfb = platform_get_drvdata(pdev);
int win;
+ pm_runtime_get_sync(sfb->dev);
+
for (win = 0; win < S3C_FB_MAX_WIN; win++)
if (sfb->windows[win])
s3c_fb_release_win(sfb, sfb->windows[win]);
kfree(sfb);
+ pm_runtime_put_sync(sfb->dev);
+ pm_runtime_disable(sfb->dev);
+
return 0;
}
#ifdef CONFIG_PM
-static int s3c_fb_suspend(struct platform_device *pdev, pm_message_t state)
+static int s3c_fb_suspend(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct s3c_fb *sfb = platform_get_drvdata(pdev);
+ struct s3c_fb_win *win;
+ int win_no;
+
+ for (win_no = S3C_FB_MAX_WIN - 1; win_no >= 0; win_no--) {
+ win = sfb->windows[win_no];
+ if (!win)
+ continue;
+
+ /* use the blank function to push into power-down */
+ s3c_fb_blank(FB_BLANK_POWERDOWN, win->fbinfo);
+ }
+
+ clk_disable(sfb->bus_clk);
+ return 0;
+}
+
+static int s3c_fb_resume(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct s3c_fb *sfb = platform_get_drvdata(pdev);
+ struct s3c_fb_platdata *pd = sfb->pdata;
+ struct s3c_fb_win *win;
+ int win_no;
+
+ clk_enable(sfb->bus_clk);
+
+ /* setup registers */
+ writel(pd->vidcon1, sfb->regs + VIDCON1);
+
+ /* zero all windows before we do anything */
+ for (win_no = 0; win_no < sfb->variant.nr_windows; win_no++)
+ s3c_fb_clear_win(sfb, win_no);
+
+ for (win_no = 0; win_no < sfb->variant.nr_windows - 1; win_no++) {
+ void __iomem *regs = sfb->regs + sfb->variant.keycon;
+
+ regs += (win_no * 8);
+ writel(0xffffff, regs + WKEYCON0);
+ writel(0xffffff, regs + WKEYCON1);
+ }
+
+ /* restore framebuffers */
+ for (win_no = 0; win_no < S3C_FB_MAX_WIN; win_no++) {
+ win = sfb->windows[win_no];
+ if (!win)
+ continue;
+
+ dev_dbg(&pdev->dev, "resuming window %d\n", win_no);
+ s3c_fb_set_par(win->fbinfo);
+ }
+
+ return 0;
+}
+
+int s3c_fb_runtime_suspend(struct device *dev)
{
+ struct platform_device *pdev = to_platform_device(dev);
struct s3c_fb *sfb = platform_get_drvdata(pdev);
struct s3c_fb_win *win;
int win_no;
return 0;
}
-static int s3c_fb_resume(struct platform_device *pdev)
+int s3c_fb_runtime_resume(struct device *dev)
{
+ struct platform_device *pdev = to_platform_device(dev);
struct s3c_fb *sfb = platform_get_drvdata(pdev);
struct s3c_fb_platdata *pd = sfb->pdata;
struct s3c_fb_win *win;
return 0;
}
+
#else
#define s3c_fb_suspend NULL
#define s3c_fb_resume NULL
+#define s3c_fb_runtime_suspend NULL
+#define s3c_fb_runtime_resume NULL
#endif
};
MODULE_DEVICE_TABLE(platform, s3c_fb_driver_ids);
+static const struct dev_pm_ops s3cfb_pm_ops = {
+ .suspend = s3c_fb_suspend,
+ .resume = s3c_fb_resume,
+ .runtime_suspend = s3c_fb_runtime_suspend,
+ .runtime_resume = s3c_fb_runtime_resume,
+};
+
static struct platform_driver s3c_fb_driver = {
.probe = s3c_fb_probe,
.remove = __devexit_p(s3c_fb_remove),
- .suspend = s3c_fb_suspend,
- .resume = s3c_fb_resume,
.id_table = s3c_fb_driver_ids,
.driver = {
.name = "s3c-fb",
.owner = THIS_MODULE,
+ .pm = &s3cfb_pm_ops,
},
};
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/types.h>
#include <video/sh_mipi_dsi.h>
#include <video/sh_mobile_lcdc.h>
-#define CMTSRTCTR 0x80d0
-#define CMTSRTREQ 0x8070
-
+#define SYSCTRL 0x0000
+#define SYSCONF 0x0004
+#define TIMSET 0x0008
+#define RESREQSET0 0x0018
+#define RESREQSET1 0x001c
+#define HSTTOVSET 0x0020
+#define LPRTOVSET 0x0024
+#define TATOVSET 0x0028
+#define PRTOVSET 0x002c
+#define DSICTRL 0x0030
#define DSIINTE 0x0060
+#define PHYCTRL 0x0070
+
+/* relative to linkbase */
+#define DTCTR 0x0000
+#define VMCTR1 0x0020
+#define VMCTR2 0x0024
+#define VMLEN1 0x0028
+#define CMTSRTREQ 0x0070
+#define CMTSRTCTR 0x00d0
/* E.g., sh7372 has 2 MIPI-DSIs - one for each LCDC */
#define MAX_SH_MIPI_DSI 2
struct sh_mipi {
void __iomem *base;
+ void __iomem *linkbase;
struct clk *dsit_clk;
struct clk *dsip_clk;
+ struct device *dev;
+
+ void *next_board_data;
+ void (*next_display_on)(void *board_data, struct fb_info *info);
+ void (*next_display_off)(void *board_data);
};
static struct sh_mipi *mipi_dsi[MAX_SH_MIPI_DSI];
int cnt = 100;
/* transmit a short packet to LCD panel */
- iowrite32(1 | data, mipi->base + 0x80d0); /* CMTSRTCTR */
- iowrite32(1, mipi->base + 0x8070); /* CMTSRTREQ */
+ iowrite32(1 | data, mipi->linkbase + CMTSRTCTR);
+ iowrite32(1, mipi->linkbase + CMTSRTREQ);
- while ((ioread32(mipi->base + 0x8070) & 1) && --cnt)
+ while ((ioread32(mipi->linkbase + CMTSRTREQ) & 1) && --cnt)
udelay(1);
return cnt ? 0 : -ETIMEDOUT;
* enable LCDC data tx, transition to LPS after completion of each HS
* packet
*/
- iowrite32(0x00000002 | enable, mipi->base + 0x8000); /* DTCTR */
+ iowrite32(0x00000002 | enable, mipi->linkbase + DTCTR);
}
static void sh_mipi_shutdown(struct platform_device *pdev)
{
struct sh_mipi *mipi = arg;
+ pm_runtime_get_sync(mipi->dev);
sh_mipi_dsi_enable(mipi, true);
+
+ if (mipi->next_display_on)
+ mipi->next_display_on(mipi->next_board_data, info);
}
static void mipi_display_off(void *arg)
{
struct sh_mipi *mipi = arg;
+ if (mipi->next_display_off)
+ mipi->next_display_off(mipi->next_board_data);
+
sh_mipi_dsi_enable(mipi, false);
+ pm_runtime_put(mipi->dev);
}
static int __init sh_mipi_setup(struct sh_mipi *mipi,
{
void __iomem *base = mipi->base;
struct sh_mobile_lcdc_chan_cfg *ch = pdata->lcd_chan;
- u32 pctype, datatype, pixfmt;
- u32 linelength;
+ u32 pctype, datatype, pixfmt, linelength, vmctr2 = 0x00e00000;
bool yuv;
/*
return -EINVAL;
/* reset DSI link */
- iowrite32(0x00000001, base); /* SYSCTRL */
+ iowrite32(0x00000001, base + SYSCTRL);
/* Hold reset for 100 cycles of the slowest of bus, HS byte and LP clock */
udelay(50);
- iowrite32(0x00000000, base); /* SYSCTRL */
+ iowrite32(0x00000000, base + SYSCTRL);
/* setup DSI link */
* ECC check enable
* additionally enable first two lanes
*/
- iowrite32(0x00003703, base + 0x04); /* SYSCONF */
+ iowrite32(0x00003703, base + SYSCONF);
/*
* T_wakeup = 0x7000
* T_hs-trail = 3
* T_clk-trail = 3
* T_clk-prepare = 2
*/
- iowrite32(0x70003332, base + 0x08); /* TIMSET */
+ iowrite32(0x70003332, base + TIMSET);
/* no responses requested */
- iowrite32(0x00000000, base + 0x18); /* RESREQSET0 */
+ iowrite32(0x00000000, base + RESREQSET0);
/* request response to packets of type 0x28 */
- iowrite32(0x00000100, base + 0x1c); /* RESREQSET1 */
+ iowrite32(0x00000100, base + RESREQSET1);
/* High-speed transmission timeout, default 0xffffffff */
- iowrite32(0x0fffffff, base + 0x20); /* HSTTOVSET */
+ iowrite32(0x0fffffff, base + HSTTOVSET);
/* LP reception timeout, default 0xffffffff */
- iowrite32(0x0fffffff, base + 0x24); /* LPRTOVSET */
+ iowrite32(0x0fffffff, base + LPRTOVSET);
/* Turn-around timeout, default 0xffffffff */
- iowrite32(0x0fffffff, base + 0x28); /* TATOVSET */
+ iowrite32(0x0fffffff, base + TATOVSET);
/* Peripheral reset timeout, default 0xffffffff */
- iowrite32(0x0fffffff, base + 0x2c); /* PRTOVSET */
+ iowrite32(0x0fffffff, base + PRTOVSET);
/* Enable timeout counters */
- iowrite32(0x00000f00, base + 0x30); /* DSICTRL */
+ iowrite32(0x00000f00, base + DSICTRL);
/* Interrupts not used, disable all */
iowrite32(0, base + DSIINTE);
/* DSI-Tx bias on */
- iowrite32(0x00000001, base + 0x70); /* PHYCTRL */
+ iowrite32(0x00000001, base + PHYCTRL);
udelay(200);
/* Deassert resets, power on, set multiplier */
- iowrite32(0x03070b01, base + 0x70); /* PHYCTRL */
+ iowrite32(0x03070b01, base + PHYCTRL);
/* setup l-bridge */
* Enable transmission of all packets,
* transmit LPS after each HS packet completion
*/
- iowrite32(0x00000006, base + 0x8000); /* DTCTR */
+ iowrite32(0x00000006, mipi->linkbase + DTCTR);
/* VSYNC width = 2 (<< 17) */
- iowrite32(0x00040000 | (pctype << 12) | datatype, base + 0x8020); /* VMCTR1 */
+ iowrite32((ch->lcd_cfg[0].vsync_len << pdata->vsynw_offset) |
+ (pdata->clksrc << 16) | (pctype << 12) | datatype,
+ mipi->linkbase + VMCTR1);
+
/*
* Non-burst mode with sync pulses: VSE and HSE are output,
* HSA period allowed, no commands in LP
*/
- iowrite32(0x00e00000, base + 0x8024); /* VMCTR2 */
+ if (pdata->flags & SH_MIPI_DSI_HSABM)
+ vmctr2 |= 0x20;
+ if (pdata->flags & SH_MIPI_DSI_HSPBM)
+ vmctr2 |= 0x10;
+ iowrite32(vmctr2, mipi->linkbase + VMCTR2);
+
/*
* 0x660 = 1632 bytes per line (RGB24, 544 pixels: see
* sh_mobile_lcdc_info.ch[0].lcd_cfg[0].xres), HSALEN = 1 - default
- * (unused, since VMCTR2[HSABM] = 0)
+ * (unused if VMCTR2[HSABM] = 0)
*/
- iowrite32(1 | (linelength << 16), base + 0x8028); /* VMLEN1 */
+ iowrite32(1 | (linelength << 16), mipi->linkbase + VMLEN1);
msleep(5);
struct sh_mipi *mipi;
struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
unsigned long rate, f_current;
int idx = pdev->id, ret;
char dsip_clk[] = "dsi.p_clk";
- if (!res || idx >= ARRAY_SIZE(mipi_dsi) || !pdata)
+ if (!res || !res2 || idx >= ARRAY_SIZE(mipi_dsi) || !pdata)
return -ENODEV;
mutex_lock(&array_lock);
goto emap;
}
+ if (!request_mem_region(res2->start, resource_size(res2), pdev->name)) {
+ dev_err(&pdev->dev, "MIPI register region 2 already claimed\n");
+ ret = -EBUSY;
+ goto ereqreg2;
+ }
+
+ mipi->linkbase = ioremap(res2->start, resource_size(res2));
+ if (!mipi->linkbase) {
+ ret = -ENOMEM;
+ goto emap2;
+ }
+
+ mipi->dev = &pdev->dev;
+
mipi->dsit_clk = clk_get(&pdev->dev, "dsit_clk");
if (IS_ERR(mipi->dsit_clk)) {
ret = PTR_ERR(mipi->dsit_clk);
mipi_dsi[idx] = mipi;
+ pm_runtime_enable(&pdev->dev);
+ pm_runtime_resume(&pdev->dev);
+
ret = sh_mipi_setup(mipi, pdata);
if (ret < 0)
goto emipisetup;
mutex_unlock(&array_lock);
platform_set_drvdata(pdev, mipi);
+ /* Save original LCDC callbacks */
+ mipi->next_board_data = pdata->lcd_chan->board_cfg.board_data;
+ mipi->next_display_on = pdata->lcd_chan->board_cfg.display_on;
+ mipi->next_display_off = pdata->lcd_chan->board_cfg.display_off;
+
/* Set up LCDC callbacks */
pdata->lcd_chan->board_cfg.board_data = mipi;
pdata->lcd_chan->board_cfg.display_on = mipi_display_on;
pdata->lcd_chan->board_cfg.display_off = mipi_display_off;
+ pdata->lcd_chan->board_cfg.owner = THIS_MODULE;
return 0;
emipisetup:
mipi_dsi[idx] = NULL;
+ pm_runtime_disable(&pdev->dev);
clk_disable(mipi->dsip_clk);
eclkpon:
clk_disable(mipi->dsit_clk);
esettrate:
clk_put(mipi->dsit_clk);
eclktget:
+ iounmap(mipi->linkbase);
+emap2:
+ release_mem_region(res2->start, resource_size(res2));
+ereqreg2:
iounmap(mipi->base);
emap:
release_mem_region(res->start, resource_size(res));
{
struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
struct sh_mipi *mipi = platform_get_drvdata(pdev);
int i, ret;
if (ret < 0)
return ret;
+ pdata->lcd_chan->board_cfg.owner = NULL;
pdata->lcd_chan->board_cfg.display_on = NULL;
pdata->lcd_chan->board_cfg.display_off = NULL;
pdata->lcd_chan->board_cfg.board_data = NULL;
+ pm_runtime_disable(&pdev->dev);
clk_disable(mipi->dsip_clk);
clk_disable(mipi->dsit_clk);
clk_put(mipi->dsit_clk);
clk_put(mipi->dsip_clk);
+ iounmap(mipi->linkbase);
+ if (res2)
+ release_mem_region(res2->start, resource_size(res2));
iounmap(mipi->base);
if (res)
release_mem_region(res->start, resource_size(res));
struct sh_hdmi {
void __iomem *base;
enum hotplug_state hp_state; /* hot-plug status */
- bool preprogrammed_mode; /* use a pre-programmed VIC or the external mode */
+ u8 preprogrammed_vic; /* use a pre-programmed VIC or
+ the external mode */
+ u8 edid_block_addr;
+ u8 edid_segment_nr;
+ u8 edid_blocks;
struct clk *hdmi_clk;
struct device *dev;
struct fb_info *info;
hdmi_write(hdmi, var->vsync_len, HDMI_EXTERNAL_V_DURATION);
/* Set bit 0 of HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS here for external mode */
- if (!hdmi->preprogrammed_mode)
+ if (!hdmi->preprogrammed_vic)
hdmi_write(hdmi, sync | 1 | (voffset << 4),
HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
}
*/
static void sh_hdmi_phy_config(struct sh_hdmi *hdmi)
{
- if (hdmi->var.yres > 480) {
+ if (hdmi->var.pixclock < 10000) {
+ /* for 1080p8bit 148MHz */
+ hdmi_write(hdmi, 0x1d, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
+ hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
+ hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
+ hdmi_write(hdmi, 0x4c, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
+ hdmi_write(hdmi, 0x1e, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
+ hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
+ hdmi_write(hdmi, 0x0e, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
+ hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
+ hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
+ } else if (hdmi->var.pixclock < 30000) {
/* 720p, 8bit, 74.25MHz. Might need to be adjusted for other formats */
/*
* [1:0] Speed_A
hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
/*
- * VIC = 1280 x 720p: ignored if external config is used
- * Send 2 for 720 x 480p, 16 for 1080p, ignored in external mode
+ * VIC should be ignored if external config is used, so, we could just use 0,
+ * but play safe and use a valid value in any case just in case
*/
- if (hdmi->var.yres == 1080 && hdmi->var.xres == 1920)
- vic = 16;
- else if (hdmi->var.yres == 480 && hdmi->var.xres == 720)
- vic = 2;
+ if (hdmi->preprogrammed_vic)
+ vic = hdmi->preprogrammed_vic;
else
vic = 4;
hdmi_write(hdmi, vic, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
}
static unsigned long sh_hdmi_rate_error(struct sh_hdmi *hdmi,
- const struct fb_videomode *mode)
+ const struct fb_videomode *mode,
+ unsigned long *hdmi_rate, unsigned long *parent_rate)
{
- long target = PICOS2KHZ(mode->pixclock) * 1000,
- rate = clk_round_rate(hdmi->hdmi_clk, target);
- unsigned long rate_error = rate > 0 ? abs(rate - target) : ULONG_MAX;
+ unsigned long target = PICOS2KHZ(mode->pixclock) * 1000, rate_error;
+ struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
+
+ *hdmi_rate = clk_round_rate(hdmi->hdmi_clk, target);
+ if ((long)*hdmi_rate < 0)
+ *hdmi_rate = clk_get_rate(hdmi->hdmi_clk);
+
+ rate_error = (long)*hdmi_rate > 0 ? abs(*hdmi_rate - target) : ULONG_MAX;
+ if (rate_error && pdata->clk_optimize_parent)
+ rate_error = pdata->clk_optimize_parent(target, hdmi_rate, parent_rate);
+ else if (clk_get_parent(hdmi->hdmi_clk))
+ *parent_rate = clk_get_rate(clk_get_parent(hdmi->hdmi_clk));
dev_dbg(hdmi->dev, "%u-%u-%u-%u x %u-%u-%u-%u\n",
mode->left_margin, mode->xres,
mode->upper_margin, mode->yres,
mode->lower_margin, mode->vsync_len);
- dev_dbg(hdmi->dev, "\t@%lu(+/-%lu)Hz, e=%lu / 1000, r=%uHz\n", target,
- rate_error, rate_error ? 10000 / (10 * target / rate_error) : 0,
- mode->refresh);
+ dev_dbg(hdmi->dev, "\t@%lu(+/-%lu)Hz, e=%lu / 1000, r=%uHz, p=%luHz\n", target,
+ rate_error, rate_error ? 10000 / (10 * target / rate_error) : 0,
+ mode->refresh, *parent_rate);
return rate_error;
}
-static int sh_hdmi_read_edid(struct sh_hdmi *hdmi)
+static int sh_hdmi_read_edid(struct sh_hdmi *hdmi, unsigned long *hdmi_rate,
+ unsigned long *parent_rate)
{
struct fb_var_screeninfo tmpvar;
struct fb_var_screeninfo *var = &tmpvar;
printk(KERN_CONT "\n");
#endif
- fb_edid_to_monspecs(edid, &hdmi->monspec);
+ if (!hdmi->edid_blocks) {
+ fb_edid_to_monspecs(edid, &hdmi->monspec);
+ hdmi->edid_blocks = edid[126] + 1;
+
+ dev_dbg(hdmi->dev, "%d main modes, %d extension blocks\n",
+ hdmi->monspec.modedb_len, hdmi->edid_blocks - 1);
+ } else {
+ dev_dbg(hdmi->dev, "Extension %u detected, DTD start %u\n",
+ edid[0], edid[2]);
+ fb_edid_add_monspecs(edid, &hdmi->monspec);
+ }
+
+ if (hdmi->edid_blocks > hdmi->edid_segment_nr * 2 +
+ (hdmi->edid_block_addr >> 7) + 1) {
+ /* More blocks to read */
+ if (hdmi->edid_block_addr) {
+ hdmi->edid_block_addr = 0;
+ hdmi->edid_segment_nr++;
+ } else {
+ hdmi->edid_block_addr = 0x80;
+ }
+ /* Set EDID word address */
+ hdmi_write(hdmi, hdmi->edid_block_addr, HDMI_EDID_WORD_ADDRESS);
+ /* Enable EDID interrupt */
+ hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
+ /* Set EDID segment pointer - starts reading EDID */
+ hdmi_write(hdmi, hdmi->edid_segment_nr, HDMI_EDID_SEGMENT_POINTER);
+ return -EAGAIN;
+ }
+
+ /* All E-EDID blocks ready */
+ dev_dbg(hdmi->dev, "%d main and extended modes\n", hdmi->monspec.modedb_len);
fb_get_options("sh_mobile_lcdc", &forced);
if (forced && *forced) {
for (i = 0, mode = hdmi->monspec.modedb;
f_width && f_height && i < hdmi->monspec.modedb_len && !exact_match;
i++, mode++) {
- unsigned long rate_error = sh_hdmi_rate_error(hdmi, mode);
+ unsigned long rate_error;
/* No interest in unmatching modes */
if (f_width != mode->xres || f_height != mode->yres)
continue;
+
+ rate_error = sh_hdmi_rate_error(hdmi, mode, hdmi_rate, parent_rate);
+
if (f_refresh == mode->refresh || (!f_refresh && !rate_error))
/*
* Exact match if either the refresh rate matches or it
if (modelist) {
found = &modelist->mode;
- found_rate_error = sh_hdmi_rate_error(hdmi, found);
+ found_rate_error = sh_hdmi_rate_error(hdmi, found, hdmi_rate, parent_rate);
}
}
if (!found)
return -ENXIO;
- dev_info(hdmi->dev, "Using %s mode %ux%u@%uHz (%luHz), clock error %luHz\n",
- modelist ? "default" : "EDID", found->xres, found->yres,
- found->refresh, PICOS2KHZ(found->pixclock) * 1000, found_rate_error);
-
- if ((found->xres == 720 && found->yres == 480) ||
- (found->xres == 1280 && found->yres == 720) ||
- (found->xres == 1920 && found->yres == 1080))
- hdmi->preprogrammed_mode = true;
+ if (found->xres == 640 && found->yres == 480 && found->refresh == 60)
+ hdmi->preprogrammed_vic = 1;
+ else if (found->xres == 720 && found->yres == 480 && found->refresh == 60)
+ hdmi->preprogrammed_vic = 2;
+ else if (found->xres == 720 && found->yres == 576 && found->refresh == 50)
+ hdmi->preprogrammed_vic = 17;
+ else if (found->xres == 1280 && found->yres == 720 && found->refresh == 60)
+ hdmi->preprogrammed_vic = 4;
+ else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 24)
+ hdmi->preprogrammed_vic = 32;
+ else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 50)
+ hdmi->preprogrammed_vic = 31;
+ else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 60)
+ hdmi->preprogrammed_vic = 16;
else
- hdmi->preprogrammed_mode = false;
+ hdmi->preprogrammed_vic = 0;
+
+ dev_dbg(hdmi->dev, "Using %s %s mode %ux%u@%uHz (%luHz), clock error %luHz\n",
+ modelist ? "default" : "EDID", hdmi->preprogrammed_vic ? "VIC" : "external",
+ found->xres, found->yres, found->refresh,
+ PICOS2KHZ(found->pixclock) * 1000, found_rate_error);
fb_videomode_to_var(&hdmi->var, found);
sh_hdmi_external_video_param(hdmi);
/* Check, if hot plug & MSENS pin status are both high */
if ((msens & 0xC0) == 0xC0) {
/* Display plug in */
+ hdmi->edid_segment_nr = 0;
+ hdmi->edid_block_addr = 0;
+ hdmi->edid_blocks = 0;
hdmi->hp_state = HDMI_HOTPLUG_CONNECTED;
/* Set EDID word address */
hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
- /* Set EDID segment pointer */
- hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
/* Enable EDID interrupt */
hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
+ /* Set EDID segment pointer - starts reading EDID */
+ hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
} else if (!(status1 & 0x80)) {
/* Display unplug, beware multiple interrupts */
- if (hdmi->hp_state != HDMI_HOTPLUG_DISCONNECTED)
+ if (hdmi->hp_state != HDMI_HOTPLUG_DISCONNECTED) {
+ hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
schedule_delayed_work(&hdmi->edid_work, 0);
-
- hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
+ }
/* display_off will switch back to mode_a */
}
} else if (status1 & 2) {
/* EDID error interrupt: retry */
/* Set EDID word address */
- hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
+ hdmi_write(hdmi, hdmi->edid_block_addr, HDMI_EDID_WORD_ADDRESS);
/* Set EDID segment pointer */
- hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
+ hdmi_write(hdmi, hdmi->edid_segment_nr, HDMI_EDID_SEGMENT_POINTER);
} else if (status1 & 4) {
/* Disable EDID interrupt */
hdmi_write(hdmi, 0xC0, HDMI_INTERRUPT_MASK_1);
- hdmi->hp_state = HDMI_HOTPLUG_EDID_DONE;
schedule_delayed_work(&hdmi->edid_work, msecs_to_jiffies(10));
}
/**
* sh_hdmi_clk_configure() - set HDMI clock frequency and enable the clock
- * @hdmi: driver context
- * @pixclock: pixel clock period in picoseconds
- * return: configured positive rate if successful
- * 0 if couldn't set the rate, but managed to enable the clock
- * negative error, if couldn't enable the clock
+ * @hdmi: driver context
+ * @hdmi_rate: HDMI clock frequency in Hz
+ * @parent_rate: if != 0 - set parent clock rate for optimal precision
+ * return: configured positive rate if successful
+ * 0 if couldn't set the rate, but managed to enable the
+ * clock, negative error, if couldn't enable the clock
*/
-static long sh_hdmi_clk_configure(struct sh_hdmi *hdmi, unsigned long pixclock)
+static long sh_hdmi_clk_configure(struct sh_hdmi *hdmi, unsigned long hdmi_rate,
+ unsigned long parent_rate)
{
- long rate;
int ret;
- rate = PICOS2KHZ(pixclock) * 1000;
- rate = clk_round_rate(hdmi->hdmi_clk, rate);
- if (rate > 0) {
- ret = clk_set_rate(hdmi->hdmi_clk, rate);
+ if (parent_rate && clk_get_parent(hdmi->hdmi_clk)) {
+ ret = clk_set_rate(clk_get_parent(hdmi->hdmi_clk), parent_rate);
if (ret < 0) {
- dev_warn(hdmi->dev, "Cannot set rate %ld: %d\n", rate, ret);
- rate = 0;
+ dev_warn(hdmi->dev, "Cannot set parent rate %ld: %d\n", parent_rate, ret);
+ hdmi_rate = clk_round_rate(hdmi->hdmi_clk, hdmi_rate);
} else {
- dev_dbg(hdmi->dev, "HDMI set frequency %lu\n", rate);
+ dev_dbg(hdmi->dev, "HDMI set parent frequency %lu\n", parent_rate);
}
- } else {
- rate = 0;
- dev_warn(hdmi->dev, "Cannot get suitable rate: %ld\n", rate);
}
- ret = clk_enable(hdmi->hdmi_clk);
+ ret = clk_set_rate(hdmi->hdmi_clk, hdmi_rate);
if (ret < 0) {
- dev_err(hdmi->dev, "Cannot enable clock: %d\n", ret);
- return ret;
+ dev_warn(hdmi->dev, "Cannot set rate %ld: %d\n", hdmi_rate, ret);
+ hdmi_rate = 0;
+ } else {
+ dev_dbg(hdmi->dev, "HDMI set frequency %lu\n", hdmi_rate);
}
- return rate;
+ return hdmi_rate;
}
/* Hotplug interrupt occurred, read EDID */
mutex_lock(&hdmi->mutex);
- if (hdmi->hp_state == HDMI_HOTPLUG_EDID_DONE) {
+ if (hdmi->hp_state == HDMI_HOTPLUG_CONNECTED) {
+ unsigned long parent_rate = 0, hdmi_rate;
+
/* A device has been plugged in */
pm_runtime_get_sync(hdmi->dev);
- ret = sh_hdmi_read_edid(hdmi);
+ ret = sh_hdmi_read_edid(hdmi, &hdmi_rate, &parent_rate);
if (ret < 0)
goto out;
+ hdmi->hp_state = HDMI_HOTPLUG_EDID_DONE;
+
/* Reconfigure the clock */
- clk_disable(hdmi->hdmi_clk);
- ret = sh_hdmi_clk_configure(hdmi, hdmi->var.pixclock);
+ ret = sh_hdmi_clk_configure(hdmi, hdmi_rate, parent_rate);
if (ret < 0)
goto out;
}
out:
- if (ret < 0)
+ if (ret < 0 && ret != -EAGAIN)
hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
mutex_unlock(&hdmi->mutex);
goto egetclk;
}
- /* Some arbitrary relaxed pixclock just to get things started */
- rate = sh_hdmi_clk_configure(hdmi, 37037);
+ /* An arbitrary relaxed pixclock just to get things started: from standard 480p */
+ rate = clk_round_rate(hdmi->hdmi_clk, PICOS2KHZ(37037));
+ if (rate > 0)
+ rate = sh_hdmi_clk_configure(hdmi, rate, 0);
+
if (rate < 0) {
ret = rate;
goto erate;
}
+ ret = clk_enable(hdmi->hdmi_clk);
+ if (ret < 0) {
+ dev_err(hdmi->dev, "Cannot enable clock: %d\n", ret);
+ goto erate;
+ }
+
dev_dbg(&pdev->dev, "Enabled HDMI clock at %luHz\n", rate);
if (!request_mem_region(res->start, resource_size(res), dev_name(&pdev->dev))) {
platform_set_drvdata(pdev, hdmi);
- /* Product and revision IDs are 0 in sh-mobile version */
- dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n",
- hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID));
-
/* Set up LCDC callbacks */
board_cfg = &pdata->lcd_chan->board_cfg;
board_cfg->owner = THIS_MODULE;
pm_runtime_enable(&pdev->dev);
pm_runtime_resume(&pdev->dev);
+ /* Product and revision IDs are 0 in sh-mobile version */
+ dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n",
+ hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID));
+
ret = request_irq(irq, sh_hdmi_hotplug, 0,
dev_name(&pdev->dev), hdmi);
if (ret < 0) {
struct notifier_block notifier;
unsigned long saved_shared_regs[NR_SHARED_REGS];
int started;
+ int forced_bpp; /* 2 channel LCDC must share bpp setting */
};
static bool banked(int reg_nr)
struct sh_mobile_lcdc_chan *ch;
struct sh_mobile_lcdc_board_cfg *board_cfg;
unsigned long tmp;
+ int bpp = 0;
int k, m;
int ret = 0;
/* enable clocks before accessing the hardware */
- for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
- if (priv->ch[k].enabled)
+ for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
+ if (priv->ch[k].enabled) {
sh_mobile_lcdc_clk_on(priv);
+ if (!bpp)
+ bpp = priv->ch[k].info->var.bits_per_pixel;
+ }
+ }
/* reset */
lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LCDC_RESET);
}
/* word and long word swap */
- lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 6);
+ switch (bpp) {
+ case 16:
+ lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 6);
+ break;
+ case 24:
+ lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 7);
+ break;
+ case 32:
+ lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 4);
+ break;
+ }
for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
ch = &priv->ch[k];
/* set bpp format in PKF[4:0] */
tmp = lcdc_read_chan(ch, LDDFR);
tmp &= ~0x0001001f;
- tmp |= (ch->info->var.bits_per_pixel == 16) ? 3 : 0;
+ switch (ch->info->var.bits_per_pixel) {
+ case 16:
+ tmp |= 0x03;
+ break;
+ case 24:
+ tmp |= 0x0b;
+ break;
+ case 32:
+ break;
+ }
lcdc_write_chan(ch, LDDFR, tmp);
/* point out our frame buffer */
static int sh_mobile_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct sh_mobile_lcdc_chan *ch = info->par;
+ struct sh_mobile_lcdc_priv *p = ch->lcdc;
if (var->xres > MAX_XRES || var->yres > MAX_YRES ||
var->xres * var->yres * (ch->cfg.bpp / 8) * 2 > info->fix.smem_len) {
- dev_warn(info->dev, "Invalid info: %u-%u-%u-%u x %u-%u-%u-%u @ %ukHz!\n",
+ dev_warn(info->dev, "Invalid info: %u-%u-%u-%u x %u-%u-%u-%u @ %lukHz!\n",
var->left_margin, var->xres, var->right_margin, var->hsync_len,
var->upper_margin, var->yres, var->lower_margin, var->vsync_len,
PICOS2KHZ(var->pixclock));
return -EINVAL;
}
+
+ /* only accept the forced_bpp for dual channel configurations */
+ if (p->forced_bpp && p->forced_bpp != var->bits_per_pixel)
+ return -EINVAL;
+
+ switch (var->bits_per_pixel) {
+ case 16: /* PKF[4:0] = 00011 - RGB 565 */
+ case 24: /* PKF[4:0] = 01011 - RGB 888 */
+ case 32: /* PKF[4:0] = 00000 - RGBA 888 */
+ break;
+ default:
+ return -EINVAL;
+ }
+
return 0;
}
var->transp.length = 0;
break;
- case 32: /* PKF[4:0] = 00000 - RGB 888
- * sh7722 pdf says 00RRGGBB but reality is GGBB00RR
- * this may be because LDDDSR has word swap enabled..
- */
- var->red.offset = 0;
+ case 24: /* PKF[4:0] = 01011 - RGB 888 */
+ var->red.offset = 16;
var->red.length = 8;
- var->green.offset = 24;
+ var->green.offset = 8;
var->green.length = 8;
- var->blue.offset = 16;
+ var->blue.offset = 0;
var->blue.length = 8;
var->transp.offset = 0;
var->transp.length = 0;
break;
+
+ case 32: /* PKF[4:0] = 00000 - RGBA 888 */
+ var->red.offset = 16;
+ var->red.length = 8;
+ var->green.offset = 8;
+ var->green.length = 8;
+ var->blue.offset = 0;
+ var->blue.length = 8;
+ var->transp.offset = 24;
+ var->transp.length = 8;
+ break;
default:
return -EINVAL;
}
goto err1;
}
+ /* for dual channel LCDC (MAIN + SUB) force shared bpp setting */
+ if (j == 2)
+ priv->forced_bpp = pdata->ch[0].bpp;
+
priv->base = ioremap_nocache(res->start, resource_size(res));
if (!priv->base)
goto err1;
* Used by permission.
*/
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
#include "init.h"
#ifdef CONFIG_FB_SIS_300
/*********************************************/
void
-SiS_SetReg(SISIOADDRESS port, unsigned short index, unsigned short data)
+SiS_SetReg(SISIOADDRESS port, u8 index, u8 data)
{
- outb((u8)index, port);
- outb((u8)data, port + 1);
+ outb(index, port);
+ outb(data, port + 1);
}
void
-SiS_SetRegByte(SISIOADDRESS port, unsigned short data)
+SiS_SetRegByte(SISIOADDRESS port, u8 data)
{
- outb((u8)data, port);
+ outb(data, port);
}
void
-SiS_SetRegShort(SISIOADDRESS port, unsigned short data)
+SiS_SetRegShort(SISIOADDRESS port, u16 data)
{
- outw((u16)data, port);
+ outw(data, port);
}
void
-SiS_SetRegLong(SISIOADDRESS port, unsigned int data)
+SiS_SetRegLong(SISIOADDRESS port, u32 data)
{
- outl((u32)data, port);
+ outl(data, port);
}
-unsigned char
-SiS_GetReg(SISIOADDRESS port, unsigned short index)
+u8
+SiS_GetReg(SISIOADDRESS port, u8 index)
{
- outb((u8)index, port);
+ outb(index, port);
return inb(port + 1);
}
-unsigned char
+u8
SiS_GetRegByte(SISIOADDRESS port)
{
return inb(port);
}
-unsigned short
+u16
SiS_GetRegShort(SISIOADDRESS port)
{
return inw(port);
}
-unsigned int
+u32
SiS_GetRegLong(SISIOADDRESS port)
{
return inl(port);
}
void
-SiS_SetRegANDOR(SISIOADDRESS Port, unsigned short Index, unsigned short DataAND, unsigned short DataOR)
+SiS_SetRegANDOR(SISIOADDRESS Port, u8 Index, u8 DataAND, u8 DataOR)
{
- unsigned short temp;
+ u8 temp;
temp = SiS_GetReg(Port, Index);
temp = (temp & (DataAND)) | DataOR;
}
void
-SiS_SetRegAND(SISIOADDRESS Port, unsigned short Index, unsigned short DataAND)
+SiS_SetRegAND(SISIOADDRESS Port, u8 Index, u8 DataAND)
{
- unsigned short temp;
+ u8 temp;
temp = SiS_GetReg(Port, Index);
temp &= DataAND;
}
void
-SiS_SetRegOR(SISIOADDRESS Port, unsigned short Index, unsigned short DataOR)
+SiS_SetRegOR(SISIOADDRESS Port, u8 Index, u8 DataOR)
{
- unsigned short temp;
+ u8 temp;
temp = SiS_GetReg(Port, Index);
temp |= DataOR;
unsigned short SiS_GetModeID_VGA2(int VGAEngine, unsigned int VBFlags, int HDisplay,
int VDisplay, int Depth, unsigned int VBFlags2);
-void SiS_SetReg(SISIOADDRESS port, unsigned short index, unsigned short data);
-void SiS_SetRegByte(SISIOADDRESS port, unsigned short data);
-void SiS_SetRegShort(SISIOADDRESS port, unsigned short data);
-void SiS_SetRegLong(SISIOADDRESS port, unsigned int data);
-unsigned char SiS_GetReg(SISIOADDRESS port, unsigned short index);
-unsigned char SiS_GetRegByte(SISIOADDRESS port);
-unsigned short SiS_GetRegShort(SISIOADDRESS port);
-unsigned int SiS_GetRegLong(SISIOADDRESS port);
-void SiS_SetRegANDOR(SISIOADDRESS Port, unsigned short Index, unsigned short DataAND,
- unsigned short DataOR);
-void SiS_SetRegAND(SISIOADDRESS Port,unsigned short Index, unsigned short DataAND);
-void SiS_SetRegOR(SISIOADDRESS Port,unsigned short Index, unsigned short DataOR);
-
void SiS_DisplayOn(struct SiS_Private *SiS_Pr);
void SiS_DisplayOff(struct SiS_Private *SiS_Pr);
void SiSRegInit(struct SiS_Private *SiS_Pr, SISIOADDRESS BaseAddr);
*
*/
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
#if 1
#define SET_EMI /* 302LV/ELV: Set EMI values */
#endif
temp = tempax & 0x00FF;
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x43,temp);
temp = ((tempax & 0xFF00) >> 8) << 3;
- SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x44,~0x0F8,temp);
+ SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port, 0x44, 0x07, temp);
tempax = SiS_Pr->SiS_VDE; /* BDxWadrst1 = BDxWadrst0 + BDxWadroff * VDE */
if(SiS_Pr->SiS_LCDResInfo == Panel_320x240_1 ||
temp = ((tempeax & 0xFF0000) >> 16) | 0x10;
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x40,temp);
temp = ((tempeax & 0x01000000) >> 24) << 7;
- SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x3C,~0x080,temp);
+ SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port, 0x3C, 0x7F, temp);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x2F,0x03);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x03,0x50);
static void SiS_FinalizeLCD(struct SiS_Private *, unsigned short, unsigned short);
#endif
-extern void SiS_SetReg(SISIOADDRESS, unsigned short, unsigned short);
-extern void SiS_SetRegByte(SISIOADDRESS, unsigned short);
-extern void SiS_SetRegShort(SISIOADDRESS, unsigned short);
-extern void SiS_SetRegLong(SISIOADDRESS, unsigned int);
-extern unsigned char SiS_GetReg(SISIOADDRESS, unsigned short);
-extern unsigned char SiS_GetRegByte(SISIOADDRESS);
-extern unsigned short SiS_GetRegShort(SISIOADDRESS);
-extern unsigned int SiS_GetRegLong(SISIOADDRESS);
-extern void SiS_SetRegANDOR(SISIOADDRESS, unsigned short, unsigned short, unsigned short);
-extern void SiS_SetRegOR(SISIOADDRESS, unsigned short, unsigned short);
-extern void SiS_SetRegAND(SISIOADDRESS, unsigned short, unsigned short);
extern void SiS_DisplayOff(struct SiS_Private *SiS_Pr);
extern void SiS_DisplayOn(struct SiS_Private *SiS_Pr);
extern bool SiS_SearchModeID(struct SiS_Private *, unsigned short *, unsigned short *);
#define VB2_LCDOVER1600BRIDGE (VB2_307T | VB2_307LV)
#define VB2_RAMDAC202MHZBRIDGE (VB2_301C | VB2_307T)
-/* I/O port access macros */
-#define inSISREG(base) inb(base)
-
-#define outSISREG(base,val) outb(val,base)
-
-#define orSISREG(base,val) \
- do { \
- u8 __Temp = inSISREG(base); \
- outSISREG(base, __Temp | (val));\
- } while (0)
-
-#define andSISREG(base,val) \
- do { \
- u8 __Temp = inSISREG(base); \
- outSISREG(base, __Temp & (val));\
- } while (0)
-
-#define inSISIDXREG(base,idx,var) \
- do { \
- outSISREG(base, idx); \
- var = inSISREG((base)+1); \
- } while (0)
-
-#define outSISIDXREG(base,idx,val) \
- do { \
- outSISREG(base, idx); \
- outSISREG((base)+1, val); \
- } while (0)
-
-#define orSISIDXREG(base,idx,val) \
- do { \
- u8 __Temp; \
- outSISREG(base, idx); \
- __Temp = inSISREG((base)+1) | (val); \
- outSISREG((base)+1, __Temp); \
- } while (0)
-
-#define andSISIDXREG(base,idx,and) \
- do { \
- u8 __Temp; \
- outSISREG(base, idx); \
- __Temp = inSISREG((base)+1) & (and); \
- outSISREG((base)+1, __Temp); \
- } while (0)
-
-#define setSISIDXREG(base,idx,and,or) \
- do { \
- u8 __Temp; \
- outSISREG(base, idx); \
- __Temp = (inSISREG((base)+1) & (and)) | (or); \
- outSISREG((base)+1, __Temp); \
- } while (0)
+/* I/O port access functions */
+
+void SiS_SetReg(SISIOADDRESS, u8, u8);
+void SiS_SetRegByte(SISIOADDRESS, u8);
+void SiS_SetRegShort(SISIOADDRESS, u16);
+void SiS_SetRegLong(SISIOADDRESS, u32);
+void SiS_SetRegANDOR(SISIOADDRESS, u8, u8, u8);
+void SiS_SetRegAND(SISIOADDRESS, u8, u8);
+void SiS_SetRegOR(SISIOADDRESS, u8, u8);
+u8 SiS_GetReg(SISIOADDRESS, u8);
+u8 SiS_GetRegByte(SISIOADDRESS);
+u16 SiS_GetRegShort(SISIOADDRESS);
+u32 SiS_GetRegLong(SISIOADDRESS);
/* MMIO access macros */
#define MMIO_IN8(base, offset) readb((base+offset))
if(!(ivideo->vbflags2 & VB2_VIDEOBRIDGE))
return false;
- inSISIDXREG(SISPART1,0x00,P1_00);
+ P1_00 = SiS_GetReg(SISPART1, 0x00);
if( ((ivideo->sisvga_engine == SIS_300_VGA) && (P1_00 & 0xa0) == 0x20) ||
((ivideo->sisvga_engine == SIS_315_VGA) && (P1_00 & 0x50) == 0x10) ) {
return true;
{
u8 temp;
- inSISIDXREG(SISCR,0x17,temp);
+ temp = SiS_GetReg(SISCR, 0x17);
if(!(temp & 0x80))
return false;
- inSISIDXREG(SISSR,0x1f,temp);
+ temp = SiS_GetReg(SISSR, 0x1f);
if(temp & 0xc0)
return false;
if(!sisfballowretracecrt1(ivideo))
return false;
- if(inSISREG(SISINPSTAT) & 0x08)
+ if (SiS_GetRegByte(SISINPSTAT) & 0x08)
return true;
else
return false;
return;
watchdog = 65536;
- while((!(inSISREG(SISINPSTAT) & 0x08)) && --watchdog);
+ while ((!(SiS_GetRegByte(SISINPSTAT) & 0x08)) && --watchdog);
watchdog = 65536;
- while((inSISREG(SISINPSTAT) & 0x08) && --watchdog);
+ while ((SiS_GetRegByte(SISINPSTAT) & 0x08) && --watchdog);
}
static bool
default: return false;
}
- inSISIDXREG(SISPART1, reg, temp);
+ temp = SiS_GetReg(SISPART1, reg);
if(temp & 0x02)
return true;
else
default:
case SIS_315_VGA: idx = 0x30; break;
}
- inSISIDXREG(SISPART1,(idx+0),reg1); /* 30 */
- inSISIDXREG(SISPART1,(idx+1),reg2); /* 31 */
- inSISIDXREG(SISPART1,(idx+2),reg3); /* 32 */
- inSISIDXREG(SISPART1,(idx+3),reg4); /* 33 */
+ reg1 = SiS_GetReg(SISPART1, (idx+0)); /* 30 */
+ reg2 = SiS_GetReg(SISPART1, (idx+1)); /* 31 */
+ reg3 = SiS_GetReg(SISPART1, (idx+2)); /* 32 */
+ reg4 = SiS_GetReg(SISPART1, (idx+3)); /* 33 */
if(reg1 & 0x01) ret |= FB_VBLANK_VBLANKING;
if(reg1 & 0x02) ret |= FB_VBLANK_VSYNCING;
if(reg4 & 0x80) ret |= FB_VBLANK_HBLANKING;
FB_VBLANK_HAVE_VBLANK |
FB_VBLANK_HAVE_VCOUNT |
FB_VBLANK_HAVE_HCOUNT);
- reg1 = inSISREG(SISINPSTAT);
+ reg1 = SiS_GetRegByte(SISINPSTAT);
if(reg1 & 0x08) ret |= FB_VBLANK_VSYNCING;
if(reg1 & 0x01) ret |= FB_VBLANK_VBLANKING;
- inSISIDXREG(SISCR,0x20,reg1);
- inSISIDXREG(SISCR,0x1b,reg1);
- inSISIDXREG(SISCR,0x1c,reg2);
- inSISIDXREG(SISCR,0x1d,reg3);
+ reg1 = SiS_GetReg(SISCR, 0x20);
+ reg1 = SiS_GetReg(SISCR, 0x1b);
+ reg2 = SiS_GetReg(SISCR, 0x1c);
+ reg3 = SiS_GetReg(SISCR, 0x1d);
(*vcount) = reg2 | ((reg3 & 0x07) << 8);
(*hcount) = (reg1 | ((reg3 & 0x10) << 4)) << 3;
}
(ivideo->sisfb_thismonitor.feature & 0xe0))) {
if(ivideo->sisvga_engine == SIS_315_VGA) {
- setSISIDXREG(SISCR, ivideo->SiS_Pr.SiS_MyCR63, 0xbf, cr63);
+ SiS_SetRegANDOR(SISCR, ivideo->SiS_Pr.SiS_MyCR63, 0xbf, cr63);
}
if(!(sisfb_bridgeisslave(ivideo))) {
- setSISIDXREG(SISSR, 0x01, ~0x20, sr01);
- setSISIDXREG(SISSR, 0x1f, 0x3f, sr1f);
+ SiS_SetRegANDOR(SISSR, 0x01, ~0x20, sr01);
+ SiS_SetRegANDOR(SISSR, 0x1f, 0x3f, sr1f);
}
}
(ivideo->vbflags2 & (VB2_301|VB2_30xBDH|VB2_LVDS))) ||
((ivideo->sisvga_engine == SIS_315_VGA) &&
((ivideo->vbflags2 & (VB2_LVDS | VB2_CHRONTEL)) == VB2_LVDS))) {
- setSISIDXREG(SISSR, 0x11, ~0x0c, sr11);
+ SiS_SetRegANDOR(SISSR, 0x11, ~0x0c, sr11);
}
if(ivideo->sisvga_engine == SIS_300_VGA) {
if((ivideo->vbflags2 & VB2_30xB) &&
(!(ivideo->vbflags2 & VB2_30xBDH))) {
- setSISIDXREG(SISPART1, 0x13, 0x3f, p1_13);
+ SiS_SetRegANDOR(SISPART1, 0x13, 0x3f, p1_13);
}
} else if(ivideo->sisvga_engine == SIS_315_VGA) {
if((ivideo->vbflags2 & VB2_30xB) &&
(!(ivideo->vbflags2 & VB2_30xBDH))) {
- setSISIDXREG(SISPART2, 0x00, 0x1f, p2_0);
+ SiS_SetRegANDOR(SISPART2, 0x00, 0x1f, p2_0);
}
}
} else if(ivideo->currentvbflags & CRT2_VGA) {
if(ivideo->vbflags2 & VB2_30xB) {
- setSISIDXREG(SISPART2, 0x00, 0x1f, p2_0);
+ SiS_SetRegANDOR(SISPART2, 0x00, 0x1f, p2_0);
}
}
/* We need to set pitch for CRT1 if bridge is in slave mode, too */
if((ivideo->currentvbflags & VB_DISPTYPE_DISP1) || (isslavemode)) {
- outSISIDXREG(SISCR,0x13,(HDisplay1 & 0xFF));
- setSISIDXREG(SISSR,0x0E,0xF0,(HDisplay1 >> 8));
+ SiS_SetReg(SISCR, 0x13, (HDisplay1 & 0xFF));
+ SiS_SetRegANDOR(SISSR, 0x0E, 0xF0, (HDisplay1 >> 8));
}
/* We must not set the pitch for CRT2 if bridge is in slave mode */
if((ivideo->currentvbflags & VB_DISPTYPE_DISP2) && (!isslavemode)) {
- orSISIDXREG(SISPART1,ivideo->CRT2_write_enable,0x01);
- outSISIDXREG(SISPART1,0x07,(HDisplay2 & 0xFF));
- setSISIDXREG(SISPART1,0x09,0xF0,(HDisplay2 >> 8));
+ SiS_SetRegOR(SISPART1, ivideo->CRT2_write_enable, 0x01);
+ SiS_SetReg(SISPART1, 0x07, (HDisplay2 & 0xFF));
+ SiS_SetRegANDOR(SISPART1, 0x09, 0xF0, (HDisplay2 >> 8));
}
}
/* >=2.6.12's fbcon clears the screen anyway */
modeno |= 0x80;
- outSISIDXREG(SISSR, IND_SIS_PASSWORD, SIS_PASSWORD);
+ SiS_SetReg(SISSR, IND_SIS_PASSWORD, SIS_PASSWORD);
sisfb_pre_setmode(ivideo);
return -EINVAL;
}
- outSISIDXREG(SISSR, IND_SIS_PASSWORD, SIS_PASSWORD);
+ SiS_SetReg(SISSR, IND_SIS_PASSWORD, SIS_PASSWORD);
sisfb_post_setmode(ivideo);
static void
sisfb_set_base_CRT1(struct sis_video_info *ivideo, unsigned int base)
{
- outSISIDXREG(SISSR, IND_SIS_PASSWORD, SIS_PASSWORD);
+ SiS_SetReg(SISSR, IND_SIS_PASSWORD, SIS_PASSWORD);
- outSISIDXREG(SISCR, 0x0D, base & 0xFF);
- outSISIDXREG(SISCR, 0x0C, (base >> 8) & 0xFF);
- outSISIDXREG(SISSR, 0x0D, (base >> 16) & 0xFF);
+ SiS_SetReg(SISCR, 0x0D, base & 0xFF);
+ SiS_SetReg(SISCR, 0x0C, (base >> 8) & 0xFF);
+ SiS_SetReg(SISSR, 0x0D, (base >> 16) & 0xFF);
if(ivideo->sisvga_engine == SIS_315_VGA) {
- setSISIDXREG(SISSR, 0x37, 0xFE, (base >> 24) & 0x01);
+ SiS_SetRegANDOR(SISSR, 0x37, 0xFE, (base >> 24) & 0x01);
}
}
sisfb_set_base_CRT2(struct sis_video_info *ivideo, unsigned int base)
{
if(ivideo->currentvbflags & VB_DISPTYPE_DISP2) {
- orSISIDXREG(SISPART1, ivideo->CRT2_write_enable, 0x01);
- outSISIDXREG(SISPART1, 0x06, (base & 0xFF));
- outSISIDXREG(SISPART1, 0x05, ((base >> 8) & 0xFF));
- outSISIDXREG(SISPART1, 0x04, ((base >> 16) & 0xFF));
+ SiS_SetRegOR(SISPART1, ivideo->CRT2_write_enable, 0x01);
+ SiS_SetReg(SISPART1, 0x06, (base & 0xFF));
+ SiS_SetReg(SISPART1, 0x05, ((base >> 8) & 0xFF));
+ SiS_SetReg(SISPART1, 0x04, ((base >> 16) & 0xFF));
if(ivideo->sisvga_engine == SIS_315_VGA) {
- setSISIDXREG(SISPART1, 0x02, 0x7F, ((base >> 24) & 0x01) << 7);
+ SiS_SetRegANDOR(SISPART1, 0x02, 0x7F, ((base >> 24) & 0x01) << 7);
}
}
}
switch(info->var.bits_per_pixel) {
case 8:
- outSISREG(SISDACA, regno);
- outSISREG(SISDACD, (red >> 10));
- outSISREG(SISDACD, (green >> 10));
- outSISREG(SISDACD, (blue >> 10));
+ SiS_SetRegByte(SISDACA, regno);
+ SiS_SetRegByte(SISDACD, (red >> 10));
+ SiS_SetRegByte(SISDACD, (green >> 10));
+ SiS_SetRegByte(SISDACD, (blue >> 10));
if(ivideo->currentvbflags & VB_DISPTYPE_DISP2) {
- outSISREG(SISDAC2A, regno);
- outSISREG(SISDAC2D, (red >> 8));
- outSISREG(SISDAC2D, (green >> 8));
- outSISREG(SISDAC2D, (blue >> 8));
+ SiS_SetRegByte(SISDAC2A, regno);
+ SiS_SetRegByte(SISDAC2D, (red >> 8));
+ SiS_SetRegByte(SISDAC2D, (green >> 8));
+ SiS_SetRegByte(SISDAC2D, (blue >> 8));
}
break;
case 16:
switch(ivideo->chip) {
#ifdef CONFIG_FB_SIS_300
case SIS_300:
- inSISIDXREG(SISSR, 0x14, reg);
+ reg = SiS_GetReg(SISSR, 0x14);
ivideo->video_size = ((reg & 0x3F) + 1) << 20;
break;
case SIS_540:
case SIS_315H:
case SIS_315PRO:
case SIS_315:
- inSISIDXREG(SISSR, 0x14, reg);
+ reg = SiS_GetReg(SISSR, 0x14);
ivideo->video_size = (1 << ((reg & 0xf0) >> 4)) << 20;
switch((reg >> 2) & 0x03) {
case 0x01:
}
break;
case SIS_330:
- inSISIDXREG(SISSR, 0x14, reg);
+ reg = SiS_GetReg(SISSR, 0x14);
ivideo->video_size = (1 << ((reg & 0xf0) >> 4)) << 20;
if(reg & 0x0c) ivideo->video_size <<= 1;
break;
case SIS_550:
case SIS_650:
case SIS_740:
- inSISIDXREG(SISSR, 0x14, reg);
+ reg = SiS_GetReg(SISSR, 0x14);
ivideo->video_size = (((reg & 0x3f) + 1) << 2) << 20;
break;
case SIS_661:
case SIS_741:
- inSISIDXREG(SISCR, 0x79, reg);
+ reg = SiS_GetReg(SISCR, 0x79);
ivideo->video_size = (1 << ((reg & 0xf0) >> 4)) << 20;
break;
case SIS_660:
case SIS_760:
case SIS_761:
- inSISIDXREG(SISCR, 0x79, reg);
+ reg = SiS_GetReg(SISCR, 0x79);
reg = (reg & 0xf0) >> 4;
if(reg) {
ivideo->video_size = (1 << reg) << 20;
ivideo->UMAsize = ivideo->video_size;
}
- inSISIDXREG(SISCR, 0x78, reg);
+ reg = SiS_GetReg(SISCR, 0x78);
reg &= 0x30;
if(reg) {
if(reg == 0x10) {
case SIS_340:
case XGI_20:
case XGI_40:
- inSISIDXREG(SISSR, 0x14, reg);
+ reg = SiS_GetReg(SISSR, 0x14);
ivideo->video_size = (1 << ((reg & 0xf0) >> 4)) << 20;
if(ivideo->chip != XGI_20) {
reg = (reg & 0x0c) >> 2;
#ifdef CONFIG_FB_SIS_300
if(ivideo->sisvga_engine == SIS_300_VGA) {
- inSISIDXREG(SISSR, 0x17, temp);
+ temp = SiS_GetReg(SISSR, 0x17);
if((temp & 0x0F) && (ivideo->chip != SIS_300)) {
/* PAL/NTSC is stored on SR16 on such machines */
if(!(ivideo->vbflags & (TV_PAL | TV_NTSC | TV_PALM | TV_PALN))) {
- inSISIDXREG(SISSR, 0x16, temp);
+ temp = SiS_GetReg(SISSR, 0x16);
if(temp & 0x20)
ivideo->vbflags |= TV_PAL;
else
}
#endif
- inSISIDXREG(SISCR, 0x32, cr32);
+ cr32 = SiS_GetReg(SISCR, 0x32);
if(cr32 & SIS_CRT1) {
ivideo->sisfb_crt1off = 0;
}
if(!(ivideo->vbflags & (TV_PAL | TV_NTSC | TV_PALM | TV_PALN | TV_NTSCJ))) {
if(ivideo->sisvga_engine == SIS_300_VGA) {
- inSISIDXREG(SISSR, 0x38, temp);
+ temp = SiS_GetReg(SISSR, 0x38);
if(temp & 0x01) ivideo->vbflags |= TV_PAL;
else ivideo->vbflags |= TV_NTSC;
} else if((ivideo->chip <= SIS_315PRO) || (ivideo->chip >= SIS_330)) {
- inSISIDXREG(SISSR, 0x38, temp);
+ temp = SiS_GetReg(SISSR, 0x38);
if(temp & 0x01) ivideo->vbflags |= TV_PAL;
else ivideo->vbflags |= TV_NTSC;
} else {
- inSISIDXREG(SISCR, 0x79, temp);
+ temp = SiS_GetReg(SISCR, 0x79);
if(temp & 0x20) ivideo->vbflags |= TV_PAL;
else ivideo->vbflags |= TV_NTSC;
}
u16 temp = 0xffff;
int i;
- inSISIDXREG(SISSR,0x1F,sr1F);
- orSISIDXREG(SISSR,0x1F,0x04);
- andSISIDXREG(SISSR,0x1F,0x3F);
+ sr1F = SiS_GetReg(SISSR, 0x1F);
+ SiS_SetRegOR(SISSR, 0x1F, 0x04);
+ SiS_SetRegAND(SISSR, 0x1F, 0x3F);
if(sr1F & 0xc0) mustwait = true;
#ifdef CONFIG_FB_SIS_315
if(ivideo->sisvga_engine == SIS_315_VGA) {
- inSISIDXREG(SISCR,ivideo->SiS_Pr.SiS_MyCR63,cr63);
+ cr63 = SiS_GetReg(SISCR, ivideo->SiS_Pr.SiS_MyCR63);
cr63 &= 0x40;
- andSISIDXREG(SISCR,ivideo->SiS_Pr.SiS_MyCR63,0xBF);
+ SiS_SetRegAND(SISCR, ivideo->SiS_Pr.SiS_MyCR63, 0xBF);
}
#endif
- inSISIDXREG(SISCR,0x17,cr17);
+ cr17 = SiS_GetReg(SISCR, 0x17);
cr17 &= 0x80;
if(!cr17) {
- orSISIDXREG(SISCR,0x17,0x80);
+ SiS_SetRegOR(SISCR, 0x17, 0x80);
mustwait = true;
- outSISIDXREG(SISSR, 0x00, 0x01);
- outSISIDXREG(SISSR, 0x00, 0x03);
+ SiS_SetReg(SISSR, 0x00, 0x01);
+ SiS_SetReg(SISSR, 0x00, 0x03);
}
if(mustwait) {
#ifdef CONFIG_FB_SIS_315
if(ivideo->chip >= SIS_330) {
- andSISIDXREG(SISCR,0x32,~0x20);
+ SiS_SetRegAND(SISCR, 0x32, ~0x20);
if(ivideo->chip >= SIS_340) {
- outSISIDXREG(SISCR, 0x57, 0x4a);
+ SiS_SetReg(SISCR, 0x57, 0x4a);
} else {
- outSISIDXREG(SISCR, 0x57, 0x5f);
+ SiS_SetReg(SISCR, 0x57, 0x5f);
}
- orSISIDXREG(SISCR, 0x53, 0x02);
- while((inSISREG(SISINPSTAT)) & 0x01) break;
- while(!((inSISREG(SISINPSTAT)) & 0x01)) break;
- if((inSISREG(SISMISCW)) & 0x10) temp = 1;
- andSISIDXREG(SISCR, 0x53, 0xfd);
- andSISIDXREG(SISCR, 0x57, 0x00);
+ SiS_SetRegOR(SISCR, 0x53, 0x02);
+ while ((SiS_GetRegByte(SISINPSTAT)) & 0x01) break;
+ while (!((SiS_GetRegByte(SISINPSTAT)) & 0x01)) break;
+ if ((SiS_GetRegByte(SISMISCW)) & 0x10) temp = 1;
+ SiS_SetRegAND(SISCR, 0x53, 0xfd);
+ SiS_SetRegAND(SISCR, 0x57, 0x00);
}
#endif
}
if((temp) && (temp != 0xffff)) {
- orSISIDXREG(SISCR,0x32,0x20);
+ SiS_SetRegOR(SISCR, 0x32, 0x20);
}
#ifdef CONFIG_FB_SIS_315
if(ivideo->sisvga_engine == SIS_315_VGA) {
- setSISIDXREG(SISCR,ivideo->SiS_Pr.SiS_MyCR63,0xBF,cr63);
+ SiS_SetRegANDOR(SISCR, ivideo->SiS_Pr.SiS_MyCR63, 0xBF, cr63);
}
#endif
- setSISIDXREG(SISCR,0x17,0x7F,cr17);
+ SiS_SetRegANDOR(SISCR, 0x17, 0x7F, cr17);
- outSISIDXREG(SISSR,0x1F,sr1F);
+ SiS_SetReg(SISSR, 0x1F, sr1F);
}
/* Determine and detect attached devices on SiS30x */
return;
/* If LCD already set up by BIOS, skip it */
- inSISIDXREG(SISCR, 0x32, reg);
+ reg = SiS_GetReg(SISCR, 0x32);
if(reg & 0x08)
return;
else
cr37 |= 0xc0;
- outSISIDXREG(SISCR, 0x36, paneltype);
+ SiS_SetReg(SISCR, 0x36, paneltype);
cr37 &= 0xf1;
- setSISIDXREG(SISCR, 0x37, 0x0c, cr37);
- orSISIDXREG(SISCR, 0x32, 0x08);
+ SiS_SetRegANDOR(SISCR, 0x37, 0x0c, cr37);
+ SiS_SetRegOR(SISCR, 0x32, 0x08);
ivideo->SiS_Pr.PanelSelfDetected = true;
}
result = 0;
for(i = 0; i < 3; i++) {
mytest = test;
- outSISIDXREG(SISPART4,0x11,(type & 0x00ff));
+ SiS_SetReg(SISPART4, 0x11, (type & 0x00ff));
temp = (type >> 8) | (mytest & 0x00ff);
- setSISIDXREG(SISPART4,0x10,0xe0,temp);
+ SiS_SetRegANDOR(SISPART4, 0x10, 0xe0, temp);
SiS_DDC2Delay(&ivideo->SiS_Pr, 0x1500);
mytest >>= 8;
mytest &= 0x7f;
- inSISIDXREG(SISPART4,0x03,temp);
+ temp = SiS_GetReg(SISPART4, 0x03);
temp ^= 0x0e;
temp &= mytest;
if(temp == mytest) result++;
#if 1
- outSISIDXREG(SISPART4,0x11,0x00);
- andSISIDXREG(SISPART4,0x10,0xe0);
+ SiS_SetReg(SISPART4, 0x11, 0x00);
+ SiS_SetRegAND(SISPART4, 0x10, 0xe0);
SiS_DDC2Delay(&ivideo->SiS_Pr, 0x1000);
#endif
}
if(ivideo->vbflags2 & VB2_301) {
svhs = 0x00b9; cvbs = 0x00b3; vga2 = 0x00d1;
- inSISIDXREG(SISPART4,0x01,myflag);
+ myflag = SiS_GetReg(SISPART4, 0x01);
if(myflag & 0x04) {
svhs = 0x00dd; cvbs = 0x00ee; vga2 = 0x00fd;
}
}
if(ivideo->chip == SIS_300) {
- inSISIDXREG(SISSR,0x3b,myflag);
+ myflag = SiS_GetReg(SISSR, 0x3b);
if(!(myflag & 0x01)) vga2 = vga2_c = 0;
}
vga2 = vga2_c = 0;
}
- inSISIDXREG(SISSR,0x1e,backupSR_1e);
- orSISIDXREG(SISSR,0x1e,0x20);
+ backupSR_1e = SiS_GetReg(SISSR, 0x1e);
+ SiS_SetRegOR(SISSR, 0x1e, 0x20);
- inSISIDXREG(SISPART4,0x0d,backupP4_0d);
+ backupP4_0d = SiS_GetReg(SISPART4, 0x0d);
if(ivideo->vbflags2 & VB2_30xC) {
- setSISIDXREG(SISPART4,0x0d,~0x07,0x01);
+ SiS_SetRegANDOR(SISPART4, 0x0d, ~0x07, 0x01);
} else {
- orSISIDXREG(SISPART4,0x0d,0x04);
+ SiS_SetRegOR(SISPART4, 0x0d, 0x04);
}
SiS_DDC2Delay(&ivideo->SiS_Pr, 0x2000);
- inSISIDXREG(SISPART2,0x00,backupP2_00);
- outSISIDXREG(SISPART2,0x00,((backupP2_00 | 0x1c) & 0xfc));
+ backupP2_00 = SiS_GetReg(SISPART2, 0x00);
+ SiS_SetReg(SISPART2, 0x00, ((backupP2_00 | 0x1c) & 0xfc));
- inSISIDXREG(SISPART2,0x4d,backupP2_4d);
+ backupP2_4d = SiS_GetReg(SISPART2, 0x4d);
if(ivideo->vbflags2 & VB2_SISYPBPRBRIDGE) {
- outSISIDXREG(SISPART2,0x4d,(backupP2_4d & ~0x10));
+ SiS_SetReg(SISPART2, 0x4d, (backupP2_4d & ~0x10));
}
if(!(ivideo->vbflags2 & VB2_30xCLV)) {
SISDoSense(ivideo, 0, 0);
}
- andSISIDXREG(SISCR, 0x32, ~0x14);
+ SiS_SetRegAND(SISCR, 0x32, ~0x14);
if(vga2_c || vga2) {
if(SISDoSense(ivideo, vga2, vga2_c)) {
if(biosflag & 0x01) {
printk(KERN_INFO "%s %s SCART output\n", stdstr, tvstr);
- orSISIDXREG(SISCR, 0x32, 0x04);
+ SiS_SetRegOR(SISCR, 0x32, 0x04);
} else {
printk(KERN_INFO "%s secondary VGA connection\n", stdstr);
- orSISIDXREG(SISCR, 0x32, 0x10);
+ SiS_SetRegOR(SISCR, 0x32, 0x10);
}
}
}
- andSISIDXREG(SISCR, 0x32, 0x3f);
+ SiS_SetRegAND(SISCR, 0x32, 0x3f);
if(ivideo->vbflags2 & VB2_30xCLV) {
- orSISIDXREG(SISPART4,0x0d,0x04);
+ SiS_SetRegOR(SISPART4, 0x0d, 0x04);
}
if((ivideo->sisvga_engine == SIS_315_VGA) && (ivideo->vbflags2 & VB2_SISYPBPRBRIDGE)) {
- outSISIDXREG(SISPART2,0x4d,(backupP2_4d | 0x10));
+ SiS_SetReg(SISPART2, 0x4d, (backupP2_4d | 0x10));
SiS_DDC2Delay(&ivideo->SiS_Pr, 0x2000);
if((result = SISDoSense(ivideo, svhs, 0x0604))) {
if((result = SISDoSense(ivideo, cvbs, 0x0804))) {
printk(KERN_INFO "%s %s YPbPr component output\n", stdstr, tvstr);
- orSISIDXREG(SISCR,0x32,0x80);
+ SiS_SetRegOR(SISCR, 0x32, 0x80);
}
}
- outSISIDXREG(SISPART2,0x4d,backupP2_4d);
+ SiS_SetReg(SISPART2, 0x4d, backupP2_4d);
}
- andSISIDXREG(SISCR, 0x32, ~0x03);
+ SiS_SetRegAND(SISCR, 0x32, ~0x03);
if(!(ivideo->vbflags & TV_YPBPR)) {
if((result = SISDoSense(ivideo, svhs, svhs_c))) {
printk(KERN_INFO "%s %s SVIDEO output\n", stdstr, tvstr);
- orSISIDXREG(SISCR, 0x32, 0x02);
+ SiS_SetRegOR(SISCR, 0x32, 0x02);
}
if((biosflag & 0x02) || (!result)) {
if(SISDoSense(ivideo, cvbs, cvbs_c)) {
printk(KERN_INFO "%s %s COMPOSITE output\n", stdstr, tvstr);
- orSISIDXREG(SISCR, 0x32, 0x01);
+ SiS_SetRegOR(SISCR, 0x32, 0x01);
}
}
}
SISDoSense(ivideo, 0, 0);
- outSISIDXREG(SISPART2,0x00,backupP2_00);
- outSISIDXREG(SISPART4,0x0d,backupP4_0d);
- outSISIDXREG(SISSR,0x1e,backupSR_1e);
+ SiS_SetReg(SISPART2, 0x00, backupP2_00);
+ SiS_SetReg(SISPART4, 0x0d, backupP4_0d);
+ SiS_SetReg(SISSR, 0x1e, backupSR_1e);
if(ivideo->vbflags2 & VB2_30xCLV) {
- inSISIDXREG(SISPART2,0x00,biosflag);
+ biosflag = SiS_GetReg(SISPART2, 0x00);
if(biosflag & 0x20) {
for(myflag = 2; myflag > 0; myflag--) {
biosflag ^= 0x20;
- outSISIDXREG(SISPART2,0x00,biosflag);
+ SiS_SetReg(SISPART2, 0x00, biosflag);
}
}
}
- outSISIDXREG(SISPART2,0x00,backupP2_00);
+ SiS_SetReg(SISPART2, 0x00, backupP2_00);
}
/* Determine and detect attached TV's on Chrontel */
if(temp1 == 0x02) {
printk(KERN_INFO "%s SVIDEO output\n", stdstr);
ivideo->vbflags |= TV_SVIDEO;
- orSISIDXREG(SISCR, 0x32, 0x02);
- andSISIDXREG(SISCR, 0x32, ~0x05);
+ SiS_SetRegOR(SISCR, 0x32, 0x02);
+ SiS_SetRegAND(SISCR, 0x32, ~0x05);
} else if (temp1 == 0x01) {
printk(KERN_INFO "%s CVBS output\n", stdstr);
ivideo->vbflags |= TV_AVIDEO;
- orSISIDXREG(SISCR, 0x32, 0x01);
- andSISIDXREG(SISCR, 0x32, ~0x06);
+ SiS_SetRegOR(SISCR, 0x32, 0x01);
+ SiS_SetRegAND(SISCR, 0x32, ~0x06);
} else {
SiS_SetCH70xxANDOR(&ivideo->SiS_Pr, 0x0e, 0x01, 0xF8);
- andSISIDXREG(SISCR, 0x32, ~0x07);
+ SiS_SetRegAND(SISCR, 0x32, ~0x07);
}
} else if(temp1 == 0) {
SiS_SetCH70xxANDOR(&ivideo->SiS_Pr, 0x0e, 0x01, 0xF8);
- andSISIDXREG(SISCR, 0x32, ~0x07);
+ SiS_SetRegAND(SISCR, 0x32, ~0x07);
}
/* Set general purpose IO for Chrontel communication */
SiS_SetChrontelGPIO(&ivideo->SiS_Pr, 0x00);
case 0x01:
printk(KERN_INFO "%s CVBS output\n", stdstr);
ivideo->vbflags |= TV_AVIDEO;
- orSISIDXREG(SISCR, 0x32, 0x01);
- andSISIDXREG(SISCR, 0x32, ~0x06);
+ SiS_SetRegOR(SISCR, 0x32, 0x01);
+ SiS_SetRegAND(SISCR, 0x32, ~0x06);
break;
case 0x02:
printk(KERN_INFO "%s SVIDEO output\n", stdstr);
ivideo->vbflags |= TV_SVIDEO;
- orSISIDXREG(SISCR, 0x32, 0x02);
- andSISIDXREG(SISCR, 0x32, ~0x05);
+ SiS_SetRegOR(SISCR, 0x32, 0x02);
+ SiS_SetRegAND(SISCR, 0x32, ~0x05);
break;
case 0x04:
printk(KERN_INFO "%s SCART output\n", stdstr);
- orSISIDXREG(SISCR, 0x32, 0x04);
- andSISIDXREG(SISCR, 0x32, ~0x03);
+ SiS_SetRegOR(SISCR, 0x32, 0x04);
+ SiS_SetRegAND(SISCR, 0x32, ~0x03);
break;
default:
- andSISIDXREG(SISCR, 0x32, ~0x07);
+ SiS_SetRegAND(SISCR, 0x32, ~0x07);
}
#endif
}
if(ivideo->chip == XGI_20)
return;
- inSISIDXREG(SISPART4, 0x00, vb_chipid);
+ vb_chipid = SiS_GetReg(SISPART4, 0x00);
switch(vb_chipid) {
case 0x01:
- inSISIDXREG(SISPART4, 0x01, reg);
+ reg = SiS_GetReg(SISPART4, 0x01);
if(reg < 0xb0) {
ivideo->vbflags |= VB_301; /* Deprecated */
ivideo->vbflags2 |= VB2_301;
} else if(reg < 0xc0) {
ivideo->vbflags |= VB_301B; /* Deprecated */
ivideo->vbflags2 |= VB2_301B;
- inSISIDXREG(SISPART4,0x23,reg);
+ reg = SiS_GetReg(SISPART4, 0x23);
if(!(reg & 0x02)) {
ivideo->vbflags |= VB_30xBDH; /* Deprecated */
ivideo->vbflags2 |= VB2_30xBDH;
ivideo->vbflags2 |= VB2_301LV;
printk(KERN_INFO "%s SiS301LV %s\n", stdstr, bridgestr);
} else if(reg <= 0xe1) {
- inSISIDXREG(SISPART4,0x39,reg);
+ reg = SiS_GetReg(SISPART4, 0x39);
if(reg == 0xff) {
ivideo->vbflags |= VB_302LV; /* Deprecated */
ivideo->vbflags2 |= VB2_302LV;
}
if((!(ivideo->vbflags2 & VB2_VIDEOBRIDGE)) && (ivideo->chip != SIS_300)) {
- inSISIDXREG(SISCR, 0x37, reg);
+ reg = SiS_GetReg(SISCR, 0x37);
reg &= SIS_EXTERNAL_CHIP_MASK;
reg >>= 1;
if(ivideo->sisvga_engine == SIS_300_VGA) {
#endif
} else if(ivideo->chip >= SIS_661) {
#ifdef CONFIG_FB_SIS_315
- inSISIDXREG(SISCR, 0x38, reg);
+ reg = SiS_GetReg(SISCR, 0x38);
reg >>= 5;
switch(reg) {
case 0x02:
tqueue_pos = (ivideo->video_size - ivideo->cmdQueueSize) / (64 * 1024);
- inSISIDXREG(SISSR, IND_SIS_TURBOQUEUE_SET, tq_state);
+ tq_state = SiS_GetReg(SISSR, IND_SIS_TURBOQUEUE_SET);
tq_state |= 0xf0;
tq_state &= 0xfc;
tq_state |= (u8)(tqueue_pos >> 8);
- outSISIDXREG(SISSR, IND_SIS_TURBOQUEUE_SET, tq_state);
+ SiS_SetReg(SISSR, IND_SIS_TURBOQUEUE_SET, tq_state);
- outSISIDXREG(SISSR, IND_SIS_TURBOQUEUE_ADR, (u8)(tqueue_pos & 0xff));
+ SiS_SetReg(SISSR, IND_SIS_TURBOQUEUE_ADR, (u8)(tqueue_pos & 0xff));
ivideo->caps |= TURBO_QUEUE_CAP;
}
}
}
- outSISIDXREG(SISSR, IND_SIS_CMDQUEUE_THRESHOLD, COMMAND_QUEUE_THRESHOLD);
- outSISIDXREG(SISSR, IND_SIS_CMDQUEUE_SET, SIS_CMD_QUEUE_RESET);
+ SiS_SetReg(SISSR, IND_SIS_CMDQUEUE_THRESHOLD, COMMAND_QUEUE_THRESHOLD);
+ SiS_SetReg(SISSR, IND_SIS_CMDQUEUE_SET, SIS_CMD_QUEUE_RESET);
if((ivideo->chip >= XGI_40) && ivideo->modechanged) {
/* Must disable dual pipe on XGI_40. Can't do
MMIO_OUT32(ivideo->mmio_vbase, Q_WRITE_PTR, 0);
- outSISIDXREG(SISSR, IND_SIS_CMDQUEUE_SET, (temp | SIS_VRAM_CMDQUEUE_ENABLE));
+ SiS_SetReg(SISSR, IND_SIS_CMDQUEUE_SET, (temp | SIS_VRAM_CMDQUEUE_ENABLE));
tempq = MMIO_IN32(ivideo->mmio_vbase, Q_READ_PTR);
MMIO_OUT32(ivideo->mmio_vbase, Q_WRITE_PTR, tempq);
sisfb_syncaccel(ivideo);
- outSISIDXREG(SISSR, IND_SIS_CMDQUEUE_SET, SIS_CMD_QUEUE_RESET);
+ SiS_SetReg(SISSR, IND_SIS_CMDQUEUE_SET, SIS_CMD_QUEUE_RESET);
}
}
MMIO_OUT32(ivideo->mmio_vbase, MMIO_QUEUE_WRITEPORT, tempq);
temp |= (SIS_MMIO_CMD_ENABLE | SIS_CMD_AUTO_CORR);
- outSISIDXREG(SISSR, IND_SIS_CMDQUEUE_SET, temp);
+ SiS_SetReg(SISSR, IND_SIS_CMDQUEUE_SET, temp);
tempq = (u32)(ivideo->video_size - ivideo->cmdQueueSize);
MMIO_OUT32(ivideo->mmio_vbase, MMIO_QUEUE_PHYBASE, tempq);
u8 reg;
int i;
- inSISIDXREG(SISCR, 0x36, reg);
+ reg = SiS_GetReg(SISCR, 0x36);
reg &= 0x0f;
if(ivideo->sisvga_engine == SIS_300_VGA) {
ivideo->CRT2LCDType = sis300paneltype[reg];
if(ivideo->CRT2LCDType == LCD_UNKNOWN) {
/* For broken BIOSes: Assume 1024x768, RGB18 */
ivideo->CRT2LCDType = LCD_1024x768;
- setSISIDXREG(SISCR,0x36,0xf0,0x02);
- setSISIDXREG(SISCR,0x37,0xee,0x01);
+ SiS_SetRegANDOR(SISCR, 0x36, 0xf0, 0x02);
+ SiS_SetRegANDOR(SISCR, 0x37, 0xee, 0x01);
printk(KERN_DEBUG "sisfb: Invalid panel ID (%02x), assuming 1024x768, RGB18\n", reg);
}
if(ivideo->sisvga_engine == SIS_300_VGA) {
if(ivideo->vbflags2 & (VB2_LVDS | VB2_30xBDH)) {
int tmp;
- inSISIDXREG(SISCR,0x30,tmp);
+ tmp = SiS_GetReg(SISCR, 0x30);
if(tmp & 0x20) {
/* Currently on LCD? If yes, read current pdc */
- inSISIDXREG(SISPART1,0x13,ivideo->detectedpdc);
+ ivideo->detectedpdc = SiS_GetReg(SISPART1, 0x13);
ivideo->detectedpdc &= 0x3c;
if(ivideo->SiS_Pr.PDC == -1) {
/* Let option override detection */
/* Try to find about LCDA */
if(ivideo->vbflags2 & VB2_SISLCDABRIDGE) {
int tmp;
- inSISIDXREG(SISPART1,0x13,tmp);
+ tmp = SiS_GetReg(SISPART1, 0x13);
if(tmp & 0x04) {
ivideo->SiS_Pr.SiS_UseLCDA = true;
ivideo->detectedlcda = 0x03;
/* Save PDC */
if(ivideo->vbflags2 & VB2_SISLVDSBRIDGE) {
int tmp;
- inSISIDXREG(SISCR,0x30,tmp);
+ tmp = SiS_GetReg(SISCR, 0x30);
if((tmp & 0x20) || (ivideo->detectedlcda != 0xff)) {
/* Currently on LCD? If yes, read current pdc */
u8 pdc;
- inSISIDXREG(SISPART1,0x2D,pdc);
+ pdc = SiS_GetReg(SISPART1, 0x2D);
ivideo->detectedpdc = (pdc & 0x0f) << 1;
ivideo->detectedpdca = (pdc & 0xf0) >> 3;
- inSISIDXREG(SISPART1,0x35,pdc);
+ pdc = SiS_GetReg(SISPART1, 0x35);
ivideo->detectedpdc |= ((pdc >> 7) & 0x01);
- inSISIDXREG(SISPART1,0x20,pdc);
+ pdc = SiS_GetReg(SISPART1, 0x20);
ivideo->detectedpdca |= ((pdc >> 6) & 0x01);
if(ivideo->newrom) {
/* New ROM invalidates other PDC resp. */
/* Save EMI */
if(ivideo->vbflags2 & VB2_SISEMIBRIDGE) {
- inSISIDXREG(SISPART4,0x30,ivideo->SiS_Pr.EMI_30);
- inSISIDXREG(SISPART4,0x31,ivideo->SiS_Pr.EMI_31);
- inSISIDXREG(SISPART4,0x32,ivideo->SiS_Pr.EMI_32);
- inSISIDXREG(SISPART4,0x33,ivideo->SiS_Pr.EMI_33);
+ ivideo->SiS_Pr.EMI_30 = SiS_GetReg(SISPART4, 0x30);
+ ivideo->SiS_Pr.EMI_31 = SiS_GetReg(SISPART4, 0x31);
+ ivideo->SiS_Pr.EMI_32 = SiS_GetReg(SISPART4, 0x32);
+ ivideo->SiS_Pr.EMI_33 = SiS_GetReg(SISPART4, 0x33);
ivideo->SiS_Pr.HaveEMI = true;
if((tmp & 0x20) || (ivideo->detectedlcda != 0xff)) {
ivideo->SiS_Pr.HaveEMILCD = true;
* ivideo->accel here, as this might have
* been changed before this is called.
*/
- inSISIDXREG(SISSR, IND_SIS_PCI_ADDRESS_SET, cr30);
- inSISIDXREG(SISSR, IND_SIS_MODULE_ENABLE, cr31);
+ cr30 = SiS_GetReg(SISSR, IND_SIS_PCI_ADDRESS_SET);
+ cr31 = SiS_GetReg(SISSR, IND_SIS_MODULE_ENABLE);
/* MMIO and 2D/3D engine enabled? */
if((cr30 & SIS_MEM_MAP_IO_ENABLE) && (cr31 & 0x42)) {
#ifdef CONFIG_FB_SIS_300
* enabled, and that the queue
* is not in the state of "reset"
*/
- inSISIDXREG(SISSR, 0x26, cr30);
+ cr30 = SiS_GetReg(SISSR, 0x26);
if((cr30 & 0xe0) && (!(cr30 & 0x01))) {
sisfb_syncaccel(ivideo);
}
ivideo->currentvbflags &= (VB_VIDEOBRIDGE | VB_DISPTYPE_DISP2);
- outSISIDXREG(SISSR, 0x05, 0x86);
+ SiS_SetReg(SISSR, 0x05, 0x86);
- inSISIDXREG(SISCR, 0x31, cr31);
+ cr31 = SiS_GetReg(SISCR, 0x31);
cr31 &= ~0x60;
cr31 |= 0x04;
#ifdef CONFIG_FB_SIS_315
if(ivideo->sisvga_engine == SIS_315_VGA) {
if(ivideo->chip >= SIS_661) {
- inSISIDXREG(SISCR, 0x38, cr38);
+ cr38 = SiS_GetReg(SISCR, 0x38);
cr38 &= ~0x07; /* Clear LCDA/DualEdge and YPbPr bits */
} else {
tvregnum = 0x38;
- inSISIDXREG(SISCR, tvregnum, cr38);
+ cr38 = SiS_GetReg(SISCR, tvregnum);
cr38 &= ~0x3b; /* Clear LCDA/DualEdge and YPbPr bits */
}
}
#ifdef CONFIG_FB_SIS_300
if(ivideo->sisvga_engine == SIS_300_VGA) {
tvregnum = 0x35;
- inSISIDXREG(SISCR, tvregnum, cr38);
+ cr38 = SiS_GetReg(SISCR, tvregnum);
}
#endif
cr31 |= (SIS_DRIVER_MODE | SIS_VB_OUTPUT_DISABLE);
}
- outSISIDXREG(SISCR, 0x30, cr30);
- outSISIDXREG(SISCR, 0x33, cr33);
+ SiS_SetReg(SISCR, 0x30, cr30);
+ SiS_SetReg(SISCR, 0x33, cr33);
if(ivideo->chip >= SIS_661) {
#ifdef CONFIG_FB_SIS_315
cr31 &= ~0x01; /* Clear PAL flag (now in CR35) */
- setSISIDXREG(SISCR, 0x35, ~0x10, cr35); /* Leave overscan bit alone */
+ SiS_SetRegANDOR(SISCR, 0x35, ~0x10, cr35); /* Leave overscan bit alone */
cr38 &= 0x07; /* Use only LCDA and HiVision/YPbPr bits */
- setSISIDXREG(SISCR, 0x38, 0xf8, cr38);
+ SiS_SetRegANDOR(SISCR, 0x38, 0xf8, cr38);
#endif
} else if(ivideo->chip != SIS_300) {
- outSISIDXREG(SISCR, tvregnum, cr38);
+ SiS_SetReg(SISCR, tvregnum, cr38);
}
- outSISIDXREG(SISCR, 0x31, cr31);
+ SiS_SetReg(SISCR, 0x31, cr31);
ivideo->SiS_Pr.SiS_UseOEM = ivideo->sisfb_useoem;
u8 tmpreg;
if(ivideo->chip >= SIS_661) {
- inSISIDXREG(SISSR,0x11,tmpreg);
+ tmpreg = SiS_GetReg(SISSR, 0x11);
if(tmpreg & 0x20) {
- inSISIDXREG(SISSR,0x3e,tmpreg);
+ tmpreg = SiS_GetReg(SISSR, 0x3e);
tmpreg = (tmpreg + 1) & 0xff;
- outSISIDXREG(SISSR,0x3e,tmpreg);
- inSISIDXREG(SISSR,0x11,tmpreg);
+ SiS_SetReg(SISSR, 0x3e, tmpreg);
+ tmpreg = SiS_GetReg(SISSR, 0x11);
}
if(tmpreg & 0xf0) {
- andSISIDXREG(SISSR,0x11,0x0f);
+ SiS_SetRegAND(SISSR, 0x11, 0x0f);
}
}
}
case 1:
x += val;
if(x < 0) x = 0;
- outSISIDXREG(SISSR,0x05,0x86);
+ SiS_SetReg(SISSR, 0x05, 0x86);
SiS_SetCH700x(&ivideo->SiS_Pr, 0x0a, (x & 0xff));
SiS_SetCH70xxANDOR(&ivideo->SiS_Pr, 0x08, ((x & 0x0100) >> 7), 0xFD);
break;
temp += (val * 2);
p2_43 = temp & 0xff;
p2_42 = (temp & 0xf00) >> 4;
- outSISIDXREG(SISPART2,0x1f,p2_1f);
- setSISIDXREG(SISPART2,0x20,0x0F,p2_20);
- setSISIDXREG(SISPART2,0x2b,0xF0,p2_2b);
- setSISIDXREG(SISPART2,0x42,0x0F,p2_42);
- outSISIDXREG(SISPART2,0x43,p2_43);
+ SiS_SetReg(SISPART2, 0x1f, p2_1f);
+ SiS_SetRegANDOR(SISPART2, 0x20, 0x0F, p2_20);
+ SiS_SetRegANDOR(SISPART2, 0x2b, 0xF0, p2_2b);
+ SiS_SetRegANDOR(SISPART2, 0x42, 0x0F, p2_42);
+ SiS_SetReg(SISPART2, 0x43, p2_43);
}
}
}
case 1:
y -= val;
if(y < 0) y = 0;
- outSISIDXREG(SISSR,0x05,0x86);
+ SiS_SetReg(SISSR, 0x05, 0x86);
SiS_SetCH700x(&ivideo->SiS_Pr, 0x0b, (y & 0xff));
SiS_SetCH70xxANDOR(&ivideo->SiS_Pr, 0x08, ((y & 0x0100) >> 8), 0xFE);
break;
p2_02 += 2;
}
}
- outSISIDXREG(SISPART2,0x01,p2_01);
- outSISIDXREG(SISPART2,0x02,p2_02);
+ SiS_SetReg(SISPART2, 0x01, p2_01);
+ SiS_SetReg(SISPART2, 0x02, p2_02);
}
}
}
u8 reg1;
#endif
- outSISIDXREG(SISSR, 0x05, 0x86);
+ SiS_SetReg(SISSR, 0x05, 0x86);
#ifdef CONFIG_FB_SIS_315
sisfb_fixup_SR11(ivideo);
crt1isoff = false;
reg = 0x80;
}
- setSISIDXREG(SISCR, 0x17, 0x7f, reg);
+ SiS_SetRegANDOR(SISCR, 0x17, 0x7f, reg);
}
#endif
#ifdef CONFIG_FB_SIS_315
reg = 0x00;
reg1 = 0x00;
}
- setSISIDXREG(SISCR, ivideo->SiS_Pr.SiS_MyCR63, ~0x40, reg);
- setSISIDXREG(SISSR, 0x1f, ~0xc0, reg1);
+ SiS_SetRegANDOR(SISCR, ivideo->SiS_Pr.SiS_MyCR63, ~0x40, reg);
+ SiS_SetRegANDOR(SISSR, 0x1f, 0x3f, reg1);
}
#endif
}
}
- andSISIDXREG(SISSR, IND_SIS_RAMDAC_CONTROL, ~0x04);
+ SiS_SetRegAND(SISSR, IND_SIS_RAMDAC_CONTROL, ~0x04);
if(ivideo->currentvbflags & CRT2_TV) {
if(ivideo->vbflags2 & VB2_SISBRIDGE) {
- inSISIDXREG(SISPART2,0x1f,ivideo->p2_1f);
- inSISIDXREG(SISPART2,0x20,ivideo->p2_20);
- inSISIDXREG(SISPART2,0x2b,ivideo->p2_2b);
- inSISIDXREG(SISPART2,0x42,ivideo->p2_42);
- inSISIDXREG(SISPART2,0x43,ivideo->p2_43);
- inSISIDXREG(SISPART2,0x01,ivideo->p2_01);
- inSISIDXREG(SISPART2,0x02,ivideo->p2_02);
+ ivideo->p2_1f = SiS_GetReg(SISPART2, 0x1f);
+ ivideo->p2_20 = SiS_GetReg(SISPART2, 0x20);
+ ivideo->p2_2b = SiS_GetReg(SISPART2, 0x2b);
+ ivideo->p2_42 = SiS_GetReg(SISPART2, 0x42);
+ ivideo->p2_43 = SiS_GetReg(SISPART2, 0x43);
+ ivideo->p2_01 = SiS_GetReg(SISPART2, 0x01);
+ ivideo->p2_02 = SiS_GetReg(SISPART2, 0x02);
} else if(ivideo->vbflags2 & VB2_CHRONTEL) {
if(ivideo->chronteltype == 1) {
ivideo->tvx = SiS_GetCH700x(&ivideo->SiS_Pr, 0x0a);
struct sis_video_info *ivideo = pci_get_drvdata(pdev);
void __iomem *rom_base;
unsigned char *myrombase = NULL;
- u32 temp;
size_t romsize;
/* First, try the official pci ROM functions (except
/* Otherwise do it the conventional way. */
#if defined(__i386__) || defined(__x86_64__)
+ {
+ u32 temp;
- for(temp = 0x000c0000; temp < 0x000f0000; temp += 0x00001000) {
+ for (temp = 0x000c0000; temp < 0x000f0000; temp += 0x00001000) {
- rom_base = ioremap(temp, 65536);
- if(!rom_base)
- continue;
+ rom_base = ioremap(temp, 65536);
+ if (!rom_base)
+ continue;
- if(!sisfb_check_rom(rom_base, ivideo)) {
- iounmap(rom_base);
- continue;
- }
+ if (!sisfb_check_rom(rom_base, ivideo)) {
+ iounmap(rom_base);
+ continue;
+ }
- if((myrombase = vmalloc(65536)))
- memcpy_fromio(myrombase, rom_base, 65536);
+ if ((myrombase = vmalloc(65536)))
+ memcpy_fromio(myrombase, rom_base, 65536);
- iounmap(rom_base);
- break;
+ iounmap(rom_base);
+ break;
- }
+ }
+ }
#endif
return myrombase;
unsigned char reg;
int i, j;
- andSISIDXREG(SISSR, 0x15, 0xFB);
- orSISIDXREG(SISSR, 0x15, 0x04);
- outSISIDXREG(SISSR, 0x13, 0x00);
- outSISIDXREG(SISSR, 0x14, 0xBF);
+ SiS_SetRegAND(SISSR, 0x15, 0xFB);
+ SiS_SetRegOR(SISSR, 0x15, 0x04);
+ SiS_SetReg(SISSR, 0x13, 0x00);
+ SiS_SetReg(SISSR, 0x14, 0xBF);
for(i = 0; i < 2; i++) {
temp = 0x1234;
writew(temp, FBAddress);
if(readw(FBAddress) == temp)
break;
- orSISIDXREG(SISSR, 0x3c, 0x01);
- inSISIDXREG(SISSR, 0x05, reg);
- inSISIDXREG(SISSR, 0x05, reg);
- andSISIDXREG(SISSR, 0x3c, 0xfe);
- inSISIDXREG(SISSR, 0x05, reg);
- inSISIDXREG(SISSR, 0x05, reg);
+ SiS_SetRegOR(SISSR, 0x3c, 0x01);
+ reg = SiS_GetReg(SISSR, 0x05);
+ reg = SiS_GetReg(SISSR, 0x05);
+ SiS_SetRegAND(SISSR, 0x3c, 0xfe);
+ reg = SiS_GetReg(SISSR, 0x05);
+ reg = SiS_GetReg(SISSR, 0x05);
temp++;
}
}
writel(0x89ABCDEFL, (FBAddress + 8));
writel(0xCDEF0123L, (FBAddress + 12));
- inSISIDXREG(SISSR, 0x3b, reg);
+ reg = SiS_GetReg(SISSR, 0x3b);
if(reg & 0x01) {
if(readl((FBAddress + 12)) == 0xCDEF0123L)
return 4; /* Channel A 128bit */
PhysicalAdrHalfPage = (PageCapacity / 2 + PhysicalAdrHigh) % PageCapacity;
PhysicalAdrOtherPage = PageCapacity * SiS_DRAMType[k][2] + PhysicalAdrHigh;
- andSISIDXREG(SISSR, 0x15, 0xFB); /* Test */
- orSISIDXREG(SISSR, 0x15, 0x04); /* Test */
+ SiS_SetRegAND(SISSR, 0x15, 0xFB); /* Test */
+ SiS_SetRegOR(SISSR, 0x15, 0x04); /* Test */
sr14 = (SiS_DRAMType[k][3] * buswidth) - 1;
if(buswidth == 4) sr14 |= 0x80;
else if(buswidth == 2) sr14 |= 0x40;
- outSISIDXREG(SISSR, 0x13, SiS_DRAMType[k][4]);
- outSISIDXREG(SISSR, 0x14, sr14);
+ SiS_SetReg(SISSR, 0x13, SiS_DRAMType[k][4]);
+ SiS_SetReg(SISSR, 0x14, sr14);
BankNumHigh <<= 16;
BankNumMid <<= 16;
if(!ivideo->SiS_Pr.UseROM)
bios = NULL;
- outSISIDXREG(SISSR, 0x05, 0x86);
+ SiS_SetReg(SISSR, 0x05, 0x86);
if(bios) {
if(bios[0x52] & 0x80) {
memtype = bios[0x52];
} else {
- inSISIDXREG(SISSR, 0x3a, memtype);
+ memtype = SiS_GetReg(SISSR, 0x3a);
}
memtype &= 0x07;
}
v6 = bios[rindex++];
}
}
- outSISIDXREG(SISSR, 0x28, v1);
- outSISIDXREG(SISSR, 0x29, v2);
- outSISIDXREG(SISSR, 0x2a, v3);
- outSISIDXREG(SISSR, 0x2e, v4);
- outSISIDXREG(SISSR, 0x2f, v5);
- outSISIDXREG(SISSR, 0x30, v6);
+ SiS_SetReg(SISSR, 0x28, v1);
+ SiS_SetReg(SISSR, 0x29, v2);
+ SiS_SetReg(SISSR, 0x2a, v3);
+ SiS_SetReg(SISSR, 0x2e, v4);
+ SiS_SetReg(SISSR, 0x2f, v5);
+ SiS_SetReg(SISSR, 0x30, v6);
v1 = 0x10;
if(bios)
v1 = bios[0xa4];
- outSISIDXREG(SISSR, 0x07, v1); /* DAC speed */
+ SiS_SetReg(SISSR, 0x07, v1); /* DAC speed */
- outSISIDXREG(SISSR, 0x11, 0x0f); /* DDC, power save */
+ SiS_SetReg(SISSR, 0x11, 0x0f); /* DDC, power save */
v1 = 0x01; v2 = 0x43; v3 = 0x1e; v4 = 0x2a;
v5 = 0x06; v6 = 0x00; v7 = 0x00; v8 = 0x00;
}
if(ivideo->revision_id >= 0x80)
v3 &= 0xfd;
- outSISIDXREG(SISSR, 0x15, v1); /* Ram type (assuming 0, BIOS 0xa5 step 8) */
- outSISIDXREG(SISSR, 0x16, v2);
- outSISIDXREG(SISSR, 0x17, v3);
- outSISIDXREG(SISSR, 0x18, v4);
- outSISIDXREG(SISSR, 0x19, v5);
- outSISIDXREG(SISSR, 0x1a, v6);
- outSISIDXREG(SISSR, 0x1b, v7);
- outSISIDXREG(SISSR, 0x1c, v8); /* ---- */
- andSISIDXREG(SISSR, 0x15 ,0xfb);
- orSISIDXREG(SISSR, 0x15, 0x04);
+ SiS_SetReg(SISSR, 0x15, v1); /* Ram type (assuming 0, BIOS 0xa5 step 8) */
+ SiS_SetReg(SISSR, 0x16, v2);
+ SiS_SetReg(SISSR, 0x17, v3);
+ SiS_SetReg(SISSR, 0x18, v4);
+ SiS_SetReg(SISSR, 0x19, v5);
+ SiS_SetReg(SISSR, 0x1a, v6);
+ SiS_SetReg(SISSR, 0x1b, v7);
+ SiS_SetReg(SISSR, 0x1c, v8); /* ---- */
+ SiS_SetRegAND(SISSR, 0x15, 0xfb);
+ SiS_SetRegOR(SISSR, 0x15, 0x04);
if(bios) {
if(bios[0x53] & 0x02) {
- orSISIDXREG(SISSR, 0x19, 0x20);
+ SiS_SetRegOR(SISSR, 0x19, 0x20);
}
}
v1 = 0x04; /* DAC pedestal (BIOS 0xe5) */
if(ivideo->revision_id >= 0x80)
v1 |= 0x01;
- outSISIDXREG(SISSR, 0x1f, v1);
- outSISIDXREG(SISSR, 0x20, 0xa4); /* linear & relocated io & disable a0000 */
+ SiS_SetReg(SISSR, 0x1f, v1);
+ SiS_SetReg(SISSR, 0x20, 0xa4); /* linear & relocated io & disable a0000 */
v1 = 0xf6; v2 = 0x0d; v3 = 0x00;
if(bios) {
v1 = bios[0xe8];
v2 = bios[0xe9];
v3 = bios[0xea];
}
- outSISIDXREG(SISSR, 0x23, v1);
- outSISIDXREG(SISSR, 0x24, v2);
- outSISIDXREG(SISSR, 0x25, v3);
- outSISIDXREG(SISSR, 0x21, 0x84);
- outSISIDXREG(SISSR, 0x22, 0x00);
- outSISIDXREG(SISCR, 0x37, 0x00);
- orSISIDXREG(SISPART1, 0x24, 0x01); /* unlock crt2 */
- outSISIDXREG(SISPART1, 0x00, 0x00);
+ SiS_SetReg(SISSR, 0x23, v1);
+ SiS_SetReg(SISSR, 0x24, v2);
+ SiS_SetReg(SISSR, 0x25, v3);
+ SiS_SetReg(SISSR, 0x21, 0x84);
+ SiS_SetReg(SISSR, 0x22, 0x00);
+ SiS_SetReg(SISCR, 0x37, 0x00);
+ SiS_SetRegOR(SISPART1, 0x24, 0x01); /* unlock crt2 */
+ SiS_SetReg(SISPART1, 0x00, 0x00);
v1 = 0x40; v2 = 0x11;
if(bios) {
v1 = bios[0xec];
v2 = bios[0xeb];
}
- outSISIDXREG(SISPART1, 0x02, v1);
+ SiS_SetReg(SISPART1, 0x02, v1);
if(ivideo->revision_id >= 0x80)
v2 &= ~0x01;
- inSISIDXREG(SISPART4, 0x00, reg);
+ reg = SiS_GetReg(SISPART4, 0x00);
if((reg == 1) || (reg == 2)) {
- outSISIDXREG(SISCR, 0x37, 0x02);
- outSISIDXREG(SISPART2, 0x00, 0x1c);
+ SiS_SetReg(SISCR, 0x37, 0x02);
+ SiS_SetReg(SISPART2, 0x00, 0x1c);
v4 = 0x00; v5 = 0x00; v6 = 0x10;
if(ivideo->SiS_Pr.UseROM) {
v4 = bios[0xf5];
v5 = bios[0xf6];
v6 = bios[0xf7];
}
- outSISIDXREG(SISPART4, 0x0d, v4);
- outSISIDXREG(SISPART4, 0x0e, v5);
- outSISIDXREG(SISPART4, 0x10, v6);
- outSISIDXREG(SISPART4, 0x0f, 0x3f);
- inSISIDXREG(SISPART4, 0x01, reg);
+ SiS_SetReg(SISPART4, 0x0d, v4);
+ SiS_SetReg(SISPART4, 0x0e, v5);
+ SiS_SetReg(SISPART4, 0x10, v6);
+ SiS_SetReg(SISPART4, 0x0f, 0x3f);
+ reg = SiS_GetReg(SISPART4, 0x01);
if(reg >= 0xb0) {
- inSISIDXREG(SISPART4, 0x23, reg);
+ reg = SiS_GetReg(SISPART4, 0x23);
reg &= 0x20;
reg <<= 1;
- outSISIDXREG(SISPART4, 0x23, reg);
+ SiS_SetReg(SISPART4, 0x23, reg);
}
} else {
v2 &= ~0x10;
}
- outSISIDXREG(SISSR, 0x32, v2);
+ SiS_SetReg(SISSR, 0x32, v2);
- andSISIDXREG(SISPART1, 0x24, 0xfe); /* Lock CRT2 */
+ SiS_SetRegAND(SISPART1, 0x24, 0xfe); /* Lock CRT2 */
- inSISIDXREG(SISSR, 0x16, reg);
+ reg = SiS_GetReg(SISSR, 0x16);
reg &= 0xc3;
- outSISIDXREG(SISCR, 0x35, reg);
- outSISIDXREG(SISCR, 0x83, 0x00);
+ SiS_SetReg(SISCR, 0x35, reg);
+ SiS_SetReg(SISCR, 0x83, 0x00);
#if !defined(__i386__) && !defined(__x86_64__)
if(sisfb_videoram) {
- outSISIDXREG(SISSR, 0x13, 0x28); /* ? */
+ SiS_SetReg(SISSR, 0x13, 0x28); /* ? */
reg = ((sisfb_videoram >> 10) - 1) | 0x40;
- outSISIDXREG(SISSR, 0x14, reg);
+ SiS_SetReg(SISSR, 0x14, reg);
} else {
#endif
/* Need to map max FB size for finding out about RAM size */
} else {
printk(KERN_DEBUG
"sisfb: Failed to map memory for size detection, assuming 8MB\n");
- outSISIDXREG(SISSR, 0x13, 0x28); /* ? */
- outSISIDXREG(SISSR, 0x14, 0x47); /* 8MB, 64bit default */
+ SiS_SetReg(SISSR, 0x13, 0x28); /* ? */
+ SiS_SetReg(SISSR, 0x14, 0x47); /* 8MB, 64bit default */
}
#if !defined(__i386__) && !defined(__x86_64__)
}
v1 = bios[0xe6];
v2 = bios[0xe7];
} else {
- inSISIDXREG(SISSR, 0x3a, reg);
+ reg = SiS_GetReg(SISSR, 0x3a);
if((reg & 0x30) == 0x30) {
v1 = 0x04; /* PCI */
v2 = 0x92;
v2 = 0xb2;
}
}
- outSISIDXREG(SISSR, 0x21, v1);
- outSISIDXREG(SISSR, 0x22, v2);
+ SiS_SetReg(SISSR, 0x21, v1);
+ SiS_SetReg(SISSR, 0x22, v2);
/* Sense CRT1 */
sisfb_sense_crt1(ivideo);
ivideo->SiS_Pr.VideoMemorySize = 8 << 20;
SiSSetMode(&ivideo->SiS_Pr, 0x2e | 0x80);
- outSISIDXREG(SISSR, 0x05, 0x86);
+ SiS_SetReg(SISSR, 0x05, 0x86);
/* Display off */
- orSISIDXREG(SISSR, 0x01, 0x20);
+ SiS_SetRegOR(SISSR, 0x01, 0x20);
/* Save mode number in CR34 */
- outSISIDXREG(SISCR, 0x34, 0x2e);
+ SiS_SetReg(SISCR, 0x34, 0x2e);
/* Let everyone know what the current mode is */
ivideo->modeprechange = 0x2e;
u8 reg;
for(i = 0; i <= (delay * 10 * 36); i++) {
- inSISIDXREG(SISSR, 0x05, reg);
+ reg = SiS_GetReg(SISSR, 0x05);
reg++;
}
}
* - if running on non-x86, there usually is no VGA window
* at a0000.
*/
- orSISIDXREG(SISSR, 0x20, (0x80 | 0x04));
+ SiS_SetRegOR(SISSR, 0x20, (0x80 | 0x04));
/* Need to map max FB size for finding out about RAM size */
mapsize = ivideo->video_size;
if(!ivideo->video_vbase) {
printk(KERN_ERR "sisfb: Unable to detect RAM size. Setting default.\n");
- outSISIDXREG(SISSR, 0x13, 0x35);
- outSISIDXREG(SISSR, 0x14, 0x41);
+ SiS_SetReg(SISSR, 0x13, 0x35);
+ SiS_SetReg(SISSR, 0x14, 0x41);
/* TODO */
return;
}
/* Non-interleaving */
- outSISIDXREG(SISSR, 0x15, 0x00);
+ SiS_SetReg(SISSR, 0x15, 0x00);
/* No tiling */
- outSISIDXREG(SISSR, 0x1c, 0x00);
+ SiS_SetReg(SISSR, 0x1c, 0x00);
if(ivideo->chip == XGI_20) {
channelab = 1;
- inSISIDXREG(SISCR, 0x97, reg);
+ reg = SiS_GetReg(SISCR, 0x97);
if(!(reg & 0x01)) { /* Single 32/16 */
buswidth = 32;
- outSISIDXREG(SISSR, 0x13, 0xb1);
- outSISIDXREG(SISSR, 0x14, 0x52);
+ SiS_SetReg(SISSR, 0x13, 0xb1);
+ SiS_SetReg(SISSR, 0x14, 0x52);
sisfb_post_xgi_delay(ivideo, 1);
sr14 = 0x02;
if(sisfb_post_xgi_rwtest(ivideo, 23, 24, mapsize))
goto bail_out;
- outSISIDXREG(SISSR, 0x13, 0x31);
- outSISIDXREG(SISSR, 0x14, 0x42);
+ SiS_SetReg(SISSR, 0x13, 0x31);
+ SiS_SetReg(SISSR, 0x14, 0x42);
sisfb_post_xgi_delay(ivideo, 1);
if(sisfb_post_xgi_rwtest(ivideo, 23, 23, mapsize))
goto bail_out;
buswidth = 16;
- outSISIDXREG(SISSR, 0x13, 0xb1);
- outSISIDXREG(SISSR, 0x14, 0x41);
+ SiS_SetReg(SISSR, 0x13, 0xb1);
+ SiS_SetReg(SISSR, 0x14, 0x41);
sisfb_post_xgi_delay(ivideo, 1);
sr14 = 0x01;
if(sisfb_post_xgi_rwtest(ivideo, 22, 23, mapsize))
goto bail_out;
else
- outSISIDXREG(SISSR, 0x13, 0x31);
+ SiS_SetReg(SISSR, 0x13, 0x31);
} else { /* Dual 16/8 */
buswidth = 16;
- outSISIDXREG(SISSR, 0x13, 0xb1);
- outSISIDXREG(SISSR, 0x14, 0x41);
+ SiS_SetReg(SISSR, 0x13, 0xb1);
+ SiS_SetReg(SISSR, 0x14, 0x41);
sisfb_post_xgi_delay(ivideo, 1);
sr14 = 0x01;
if(sisfb_post_xgi_rwtest(ivideo, 22, 23, mapsize))
goto bail_out;
- outSISIDXREG(SISSR, 0x13, 0x31);
- outSISIDXREG(SISSR, 0x14, 0x31);
+ SiS_SetReg(SISSR, 0x13, 0x31);
+ SiS_SetReg(SISSR, 0x14, 0x31);
sisfb_post_xgi_delay(ivideo, 1);
if(sisfb_post_xgi_rwtest(ivideo, 22, 22, mapsize))
goto bail_out;
buswidth = 8;
- outSISIDXREG(SISSR, 0x13, 0xb1);
- outSISIDXREG(SISSR, 0x14, 0x30);
+ SiS_SetReg(SISSR, 0x13, 0xb1);
+ SiS_SetReg(SISSR, 0x14, 0x30);
sisfb_post_xgi_delay(ivideo, 1);
sr14 = 0x00;
if(sisfb_post_xgi_rwtest(ivideo, 21, 22, mapsize))
goto bail_out;
else
- outSISIDXREG(SISSR, 0x13, 0x31);
+ SiS_SetReg(SISSR, 0x13, 0x31);
}
} else { /* XGI_40 */
- inSISIDXREG(SISCR, 0x97, reg);
+ reg = SiS_GetReg(SISCR, 0x97);
if(!(reg & 0x10)) {
- inSISIDXREG(SISSR, 0x39, reg);
+ reg = SiS_GetReg(SISSR, 0x39);
reg >>= 1;
}
buswidth = 32;
if(ivideo->revision_id == 2) {
channelab = 2;
- outSISIDXREG(SISSR, 0x13, 0xa1);
- outSISIDXREG(SISSR, 0x14, 0x44);
+ SiS_SetReg(SISSR, 0x13, 0xa1);
+ SiS_SetReg(SISSR, 0x14, 0x44);
sr14 = 0x04;
sisfb_post_xgi_delay(ivideo, 1);
if(sisfb_post_xgi_rwtest(ivideo, 23, 24, mapsize))
goto bail_out;
- outSISIDXREG(SISSR, 0x13, 0x21);
- outSISIDXREG(SISSR, 0x14, 0x34);
+ SiS_SetReg(SISSR, 0x13, 0x21);
+ SiS_SetReg(SISSR, 0x14, 0x34);
if(sisfb_post_xgi_rwtest(ivideo, 22, 23, mapsize))
goto bail_out;
channelab = 1;
- outSISIDXREG(SISSR, 0x13, 0xa1);
- outSISIDXREG(SISSR, 0x14, 0x40);
+ SiS_SetReg(SISSR, 0x13, 0xa1);
+ SiS_SetReg(SISSR, 0x14, 0x40);
sr14 = 0x00;
if(sisfb_post_xgi_rwtest(ivideo, 22, 23, mapsize))
goto bail_out;
- outSISIDXREG(SISSR, 0x13, 0x21);
- outSISIDXREG(SISSR, 0x14, 0x30);
+ SiS_SetReg(SISSR, 0x13, 0x21);
+ SiS_SetReg(SISSR, 0x14, 0x30);
} else {
channelab = 3;
- outSISIDXREG(SISSR, 0x13, 0xa1);
- outSISIDXREG(SISSR, 0x14, 0x4c);
+ SiS_SetReg(SISSR, 0x13, 0xa1);
+ SiS_SetReg(SISSR, 0x14, 0x4c);
sr14 = 0x0c;
sisfb_post_xgi_delay(ivideo, 1);
if(sisfb_post_xgi_rwtest(ivideo, 23, 25, mapsize))
goto bail_out;
channelab = 2;
- outSISIDXREG(SISSR, 0x14, 0x48);
+ SiS_SetReg(SISSR, 0x14, 0x48);
sisfb_post_xgi_delay(ivideo, 1);
sr14 = 0x08;
if(sisfb_post_xgi_rwtest(ivideo, 23, 24, mapsize))
goto bail_out;
- outSISIDXREG(SISSR, 0x13, 0x21);
- outSISIDXREG(SISSR, 0x14, 0x3c);
+ SiS_SetReg(SISSR, 0x13, 0x21);
+ SiS_SetReg(SISSR, 0x14, 0x3c);
sr14 = 0x0c;
if(sisfb_post_xgi_rwtest(ivideo, 23, 24, mapsize)) {
channelab = 3;
} else {
channelab = 2;
- outSISIDXREG(SISSR, 0x14, 0x38);
+ SiS_SetReg(SISSR, 0x14, 0x38);
sr14 = 0x08;
}
}
buswidth = 64;
if(ivideo->revision_id == 2) {
channelab = 1;
- outSISIDXREG(SISSR, 0x13, 0xa1);
- outSISIDXREG(SISSR, 0x14, 0x52);
+ SiS_SetReg(SISSR, 0x13, 0xa1);
+ SiS_SetReg(SISSR, 0x14, 0x52);
sisfb_post_xgi_delay(ivideo, 1);
sr14 = 0x02;
if(sisfb_post_xgi_rwtest(ivideo, 23, 24, mapsize))
goto bail_out;
- outSISIDXREG(SISSR, 0x13, 0x21);
- outSISIDXREG(SISSR, 0x14, 0x42);
+ SiS_SetReg(SISSR, 0x13, 0x21);
+ SiS_SetReg(SISSR, 0x14, 0x42);
} else {
channelab = 2;
- outSISIDXREG(SISSR, 0x13, 0xa1);
- outSISIDXREG(SISSR, 0x14, 0x5a);
+ SiS_SetReg(SISSR, 0x13, 0xa1);
+ SiS_SetReg(SISSR, 0x14, 0x5a);
sisfb_post_xgi_delay(ivideo, 1);
sr14 = 0x0a;
if(sisfb_post_xgi_rwtest(ivideo, 24, 25, mapsize))
goto bail_out;
- outSISIDXREG(SISSR, 0x13, 0x21);
- outSISIDXREG(SISSR, 0x14, 0x4a);
+ SiS_SetReg(SISSR, 0x13, 0x21);
+ SiS_SetReg(SISSR, 0x14, 0x4a);
}
sisfb_post_xgi_delay(ivideo, 1);
}
bail_out:
- setSISIDXREG(SISSR, 0x14, 0xf0, sr14);
+ SiS_SetRegANDOR(SISSR, 0x14, 0xf0, sr14);
sisfb_post_xgi_delay(ivideo, 1);
j = (ivideo->chip == XGI_20) ? 5 : 9;
reg = (ivideo->chip == XGI_20) ?
dramsr13[(i * 5) + 4] : dramsr13_4[(i * 5) + 4];
- setSISIDXREG(SISSR, 0x13, 0x80, reg);
+ SiS_SetRegANDOR(SISSR, 0x13, 0x80, reg);
sisfb_post_xgi_delay(ivideo, 50);
ranksize = (ivideo->chip == XGI_20) ?
dramsr13[(i * 5) + 3] : dramsr13_4[(i * 5) + 3];
- inSISIDXREG(SISSR, 0x13, reg);
+ reg = SiS_GetReg(SISSR, 0x13);
if(reg & 0x80) ranksize <<= 1;
if(ivideo->chip == XGI_20) {
if(!reg) continue;
- setSISIDXREG(SISSR, 0x14, 0x0f, (reg & 0xf0));
+ SiS_SetRegANDOR(SISSR, 0x14, 0x0f, (reg & 0xf0));
sisfb_post_xgi_delay(ivideo, 1);
if(sisfb_post_xgi_rwtest(ivideo, j, ((reg >> 4) + channelab - 2 + 20), mapsize))
v2 = ivideo->bios_abase[0x90 + index + 1];
v3 = ivideo->bios_abase[0x90 + index + 2];
}
- outSISIDXREG(SISSR, 0x28, v1);
- outSISIDXREG(SISSR, 0x29, v2);
- outSISIDXREG(SISSR, 0x2a, v3);
+ SiS_SetReg(SISSR, 0x28, v1);
+ SiS_SetReg(SISSR, 0x29, v2);
+ SiS_SetReg(SISSR, 0x2a, v3);
sisfb_post_xgi_delay(ivideo, 0x43);
sisfb_post_xgi_delay(ivideo, 0x43);
sisfb_post_xgi_delay(ivideo, 0x43);
v2 = ivideo->bios_abase[0xb8 + index + 1];
v3 = ivideo->bios_abase[0xb8 + index + 2];
}
- outSISIDXREG(SISSR, 0x2e, v1);
- outSISIDXREG(SISSR, 0x2f, v2);
- outSISIDXREG(SISSR, 0x30, v3);
+ SiS_SetReg(SISSR, 0x2e, v1);
+ SiS_SetReg(SISSR, 0x2f, v2);
+ SiS_SetReg(SISSR, 0x30, v3);
sisfb_post_xgi_delay(ivideo, 0x43);
sisfb_post_xgi_delay(ivideo, 0x43);
sisfb_post_xgi_delay(ivideo, 0x43);
};
/* VGA enable */
- reg = inSISREG(SISVGAENABLE) | 0x01;
- outSISREG(SISVGAENABLE, reg);
+ reg = SiS_GetRegByte(SISVGAENABLE) | 0x01;
+ SiS_SetRegByte(SISVGAENABLE, reg);
/* Misc */
- reg = inSISREG(SISMISCR) | 0x01;
- outSISREG(SISMISCW, reg);
+ reg = SiS_GetRegByte(SISMISCR) | 0x01;
+ SiS_SetRegByte(SISMISCW, reg);
/* Unlock SR */
- outSISIDXREG(SISSR, 0x05, 0x86);
- inSISIDXREG(SISSR, 0x05, reg);
+ SiS_SetReg(SISSR, 0x05, 0x86);
+ reg = SiS_GetReg(SISSR, 0x05);
if(reg != 0xa1)
return 0;
/* Clear some regs */
for(i = 0; i < 0x22; i++) {
if(0x06 + i == 0x20) continue;
- outSISIDXREG(SISSR, 0x06 + i, 0x00);
+ SiS_SetReg(SISSR, 0x06 + i, 0x00);
}
for(i = 0; i < 0x0b; i++) {
- outSISIDXREG(SISSR, 0x31 + i, 0x00);
+ SiS_SetReg(SISSR, 0x31 + i, 0x00);
}
for(i = 0; i < 0x10; i++) {
- outSISIDXREG(SISCR, 0x30 + i, 0x00);
+ SiS_SetReg(SISCR, 0x30 + i, 0x00);
}
ptr = cs78;
ptr = (const u8 *)&bios[0x78];
}
for(i = 0; i < 3; i++) {
- outSISIDXREG(SISSR, 0x23 + i, ptr[i]);
+ SiS_SetReg(SISSR, 0x23 + i, ptr[i]);
}
ptr = cs76;
ptr = (const u8 *)&bios[0x76];
}
for(i = 0; i < 2; i++) {
- outSISIDXREG(SISSR, 0x21 + i, ptr[i]);
+ SiS_SetReg(SISSR, 0x21 + i, ptr[i]);
}
v1 = 0x18; v2 = 0x00;
v1 = bios[0x74];
v2 = bios[0x75];
}
- outSISIDXREG(SISSR, 0x07, v1);
- outSISIDXREG(SISSR, 0x11, 0x0f);
- outSISIDXREG(SISSR, 0x1f, v2);
+ SiS_SetReg(SISSR, 0x07, v1);
+ SiS_SetReg(SISSR, 0x11, 0x0f);
+ SiS_SetReg(SISSR, 0x1f, v2);
/* PCI linear mode, RelIO enabled, A0000 decoding disabled */
- outSISIDXREG(SISSR, 0x20, 0x80 | 0x20 | 0x04);
- outSISIDXREG(SISSR, 0x27, 0x74);
+ SiS_SetReg(SISSR, 0x20, 0x80 | 0x20 | 0x04);
+ SiS_SetReg(SISSR, 0x27, 0x74);
ptr = cs7b;
if(ivideo->haveXGIROM) {
ptr = (const u8 *)&bios[0x7b];
}
for(i = 0; i < 3; i++) {
- outSISIDXREG(SISSR, 0x31 + i, ptr[i]);
+ SiS_SetReg(SISSR, 0x31 + i, ptr[i]);
}
if(ivideo->chip == XGI_40) {
if(ivideo->revision_id == 2) {
- setSISIDXREG(SISSR, 0x3b, 0x3f, 0xc0);
+ SiS_SetRegANDOR(SISSR, 0x3b, 0x3f, 0xc0);
}
- outSISIDXREG(SISCR, 0x7d, 0xfe);
- outSISIDXREG(SISCR, 0x7e, 0x0f);
+ SiS_SetReg(SISCR, 0x7d, 0xfe);
+ SiS_SetReg(SISCR, 0x7e, 0x0f);
}
if(ivideo->revision_id == 0) { /* 40 *and* 20? */
- andSISIDXREG(SISCR, 0x58, 0xd7);
- inSISIDXREG(SISCR, 0xcb, reg);
+ SiS_SetRegAND(SISCR, 0x58, 0xd7);
+ reg = SiS_GetReg(SISCR, 0xcb);
if(reg & 0x20) {
- setSISIDXREG(SISCR, 0x58, 0xd7, (reg & 0x10) ? 0x08 : 0x20); /* =0x28 Z7 ? */
+ SiS_SetRegANDOR(SISCR, 0x58, 0xd7, (reg & 0x10) ? 0x08 : 0x20); /* =0x28 Z7 ? */
}
}
reg = (ivideo->chip == XGI_40) ? 0x20 : 0x00;
- setSISIDXREG(SISCR, 0x38, 0x1f, reg);
+ SiS_SetRegANDOR(SISCR, 0x38, 0x1f, reg);
if(ivideo->chip == XGI_20) {
- outSISIDXREG(SISSR, 0x36, 0x70);
+ SiS_SetReg(SISSR, 0x36, 0x70);
} else {
- outSISIDXREG(SISVID, 0x00, 0x86);
- outSISIDXREG(SISVID, 0x32, 0x00);
- outSISIDXREG(SISVID, 0x30, 0x00);
- outSISIDXREG(SISVID, 0x32, 0x01);
- outSISIDXREG(SISVID, 0x30, 0x00);
- andSISIDXREG(SISVID, 0x2f, 0xdf);
- andSISIDXREG(SISCAP, 0x00, 0x3f);
-
- outSISIDXREG(SISPART1, 0x2f, 0x01);
- outSISIDXREG(SISPART1, 0x00, 0x00);
- outSISIDXREG(SISPART1, 0x02, bios[0x7e]);
- outSISIDXREG(SISPART1, 0x2e, 0x08);
- andSISIDXREG(SISPART1, 0x35, 0x7f);
- andSISIDXREG(SISPART1, 0x50, 0xfe);
-
- inSISIDXREG(SISPART4, 0x00, reg);
+ SiS_SetReg(SISVID, 0x00, 0x86);
+ SiS_SetReg(SISVID, 0x32, 0x00);
+ SiS_SetReg(SISVID, 0x30, 0x00);
+ SiS_SetReg(SISVID, 0x32, 0x01);
+ SiS_SetReg(SISVID, 0x30, 0x00);
+ SiS_SetRegAND(SISVID, 0x2f, 0xdf);
+ SiS_SetRegAND(SISCAP, 0x00, 0x3f);
+
+ SiS_SetReg(SISPART1, 0x2f, 0x01);
+ SiS_SetReg(SISPART1, 0x00, 0x00);
+ SiS_SetReg(SISPART1, 0x02, bios[0x7e]);
+ SiS_SetReg(SISPART1, 0x2e, 0x08);
+ SiS_SetRegAND(SISPART1, 0x35, 0x7f);
+ SiS_SetRegAND(SISPART1, 0x50, 0xfe);
+
+ reg = SiS_GetReg(SISPART4, 0x00);
if(reg == 1 || reg == 2) {
- outSISIDXREG(SISPART2, 0x00, 0x1c);
- outSISIDXREG(SISPART4, 0x0d, bios[0x7f]);
- outSISIDXREG(SISPART4, 0x0e, bios[0x80]);
- outSISIDXREG(SISPART4, 0x10, bios[0x81]);
- andSISIDXREG(SISPART4, 0x0f, 0x3f);
+ SiS_SetReg(SISPART2, 0x00, 0x1c);
+ SiS_SetReg(SISPART4, 0x0d, bios[0x7f]);
+ SiS_SetReg(SISPART4, 0x0e, bios[0x80]);
+ SiS_SetReg(SISPART4, 0x10, bios[0x81]);
+ SiS_SetRegAND(SISPART4, 0x0f, 0x3f);
- inSISIDXREG(SISPART4, 0x01, reg);
+ reg = SiS_GetReg(SISPART4, 0x01);
if((reg & 0xf0) >= 0xb0) {
- inSISIDXREG(SISPART4, 0x23, reg);
+ reg = SiS_GetReg(SISPART4, 0x23);
if(reg & 0x20) reg |= 0x40;
- outSISIDXREG(SISPART4, 0x23, reg);
+ SiS_SetReg(SISPART4, 0x23, reg);
reg = (reg & 0x20) ? 0x02 : 0x00;
- setSISIDXREG(SISPART1, 0x1e, 0xfd, reg);
+ SiS_SetRegANDOR(SISPART1, 0x1e, 0xfd, reg);
}
}
v1 = bios[0x77];
- inSISIDXREG(SISSR, 0x3b, reg);
+ reg = SiS_GetReg(SISSR, 0x3b);
if(reg & 0x02) {
- inSISIDXREG(SISSR, 0x3a, reg);
+ reg = SiS_GetReg(SISSR, 0x3a);
v2 = (reg & 0x30) >> 3;
if(!(v2 & 0x04)) v2 ^= 0x02;
- inSISIDXREG(SISSR, 0x39, reg);
+ reg = SiS_GetReg(SISSR, 0x39);
if(reg & 0x80) v2 |= 0x80;
v2 |= 0x01;
v2 |= 0x08;
}
}
- setSISIDXREG(SISCR, 0x5f, 0xf0, v2);
+ SiS_SetRegANDOR(SISCR, 0x5f, 0xf0, v2);
}
- outSISIDXREG(SISSR, 0x22, v1);
+ SiS_SetReg(SISSR, 0x22, v1);
if(ivideo->revision_id == 2) {
- inSISIDXREG(SISSR, 0x3b, v1);
- inSISIDXREG(SISSR, 0x3a, v2);
+ v1 = SiS_GetReg(SISSR, 0x3b);
+ v2 = SiS_GetReg(SISSR, 0x3a);
regd = bios[0x90 + 3] | (bios[0x90 + 4] << 8);
if( (!(v1 & 0x02)) && (v2 & 0x30) && (regd < 0xcf) )
- setSISIDXREG(SISCR, 0x5f, 0xf1, 0x01);
+ SiS_SetRegANDOR(SISCR, 0x5f, 0xf1, 0x01);
if((mypdev = pci_get_device(0x10de, 0x01e0, NULL))) {
/* TODO: set CR5f &0xf1 | 0x01 for version 6570
* of nforce 2 ROM
*/
if(0)
- setSISIDXREG(SISCR, 0x5f, 0xf1, 0x01);
+ SiS_SetRegANDOR(SISCR, 0x5f, 0xf1, 0x01);
pci_dev_put(mypdev);
}
}
v1 = 0x30;
- inSISIDXREG(SISSR, 0x3b, reg);
- inSISIDXREG(SISCR, 0x5f, v2);
+ reg = SiS_GetReg(SISSR, 0x3b);
+ v2 = SiS_GetReg(SISCR, 0x5f);
if((!(reg & 0x02)) && (v2 & 0x0e))
v1 |= 0x08;
- outSISIDXREG(SISSR, 0x27, v1);
+ SiS_SetReg(SISSR, 0x27, v1);
if(bios[0x64] & 0x01) {
- setSISIDXREG(SISCR, 0x5f, 0xf0, bios[0x64]);
+ SiS_SetRegANDOR(SISCR, 0x5f, 0xf0, bios[0x64]);
}
v1 = bios[0x4f7];
regd = (regd >> 20) & 0x0f;
if(regd == 1) {
v1 &= 0xfc;
- orSISIDXREG(SISCR, 0x5f, 0x08);
- }
- outSISIDXREG(SISCR, 0x48, v1);
-
- setSISIDXREG(SISCR, 0x47, 0x04, bios[0x4f6] & 0xfb);
- setSISIDXREG(SISCR, 0x49, 0xf0, bios[0x4f8] & 0x0f);
- setSISIDXREG(SISCR, 0x4a, 0x60, bios[0x4f9] & 0x9f);
- setSISIDXREG(SISCR, 0x4b, 0x08, bios[0x4fa] & 0xf7);
- setSISIDXREG(SISCR, 0x4c, 0x80, bios[0x4fb] & 0x7f);
- outSISIDXREG(SISCR, 0x70, bios[0x4fc]);
- setSISIDXREG(SISCR, 0x71, 0xf0, bios[0x4fd] & 0x0f);
- outSISIDXREG(SISCR, 0x74, 0xd0);
- setSISIDXREG(SISCR, 0x74, 0xcf, bios[0x4fe] & 0x30);
- setSISIDXREG(SISCR, 0x75, 0xe0, bios[0x4ff] & 0x1f);
- setSISIDXREG(SISCR, 0x76, 0xe0, bios[0x500] & 0x1f);
+ SiS_SetRegOR(SISCR, 0x5f, 0x08);
+ }
+ SiS_SetReg(SISCR, 0x48, v1);
+
+ SiS_SetRegANDOR(SISCR, 0x47, 0x04, bios[0x4f6] & 0xfb);
+ SiS_SetRegANDOR(SISCR, 0x49, 0xf0, bios[0x4f8] & 0x0f);
+ SiS_SetRegANDOR(SISCR, 0x4a, 0x60, bios[0x4f9] & 0x9f);
+ SiS_SetRegANDOR(SISCR, 0x4b, 0x08, bios[0x4fa] & 0xf7);
+ SiS_SetRegANDOR(SISCR, 0x4c, 0x80, bios[0x4fb] & 0x7f);
+ SiS_SetReg(SISCR, 0x70, bios[0x4fc]);
+ SiS_SetRegANDOR(SISCR, 0x71, 0xf0, bios[0x4fd] & 0x0f);
+ SiS_SetReg(SISCR, 0x74, 0xd0);
+ SiS_SetRegANDOR(SISCR, 0x74, 0xcf, bios[0x4fe] & 0x30);
+ SiS_SetRegANDOR(SISCR, 0x75, 0xe0, bios[0x4ff] & 0x1f);
+ SiS_SetRegANDOR(SISCR, 0x76, 0xe0, bios[0x500] & 0x1f);
v1 = bios[0x501];
if((mypdev = pci_get_device(0x8086, 0x2530, NULL))) {
v1 = 0xf0;
pci_dev_put(mypdev);
}
- outSISIDXREG(SISCR, 0x77, v1);
+ SiS_SetReg(SISCR, 0x77, v1);
}
/* RAM type */
if(ivideo->haveXGIROM) {
v1 = bios[0x140 + regb];
}
- outSISIDXREG(SISCR, 0x6d, v1);
+ SiS_SetReg(SISCR, 0x6d, v1);
ptr = cs128;
if(ivideo->haveXGIROM) {
ptr = (const u8 *)&bios[0x128];
}
for(i = 0, j = 0; i < 3; i++, j += 8) {
- outSISIDXREG(SISCR, 0x68 + i, ptr[j + regb]);
+ SiS_SetReg(SISCR, 0x68 + i, ptr[j + regb]);
}
ptr = cs31a;
if(regd & 0x01) reg |= 0x04;
if(regd & 0x02) reg |= 0x08;
regd >>= 2;
- outSISIDXREG(SISCR, rega, reg);
- inSISIDXREG(SISCR, rega, reg);
- inSISIDXREG(SISCR, rega, reg);
+ SiS_SetReg(SISCR, rega, reg);
+ reg = SiS_GetReg(SISCR, rega);
+ reg = SiS_GetReg(SISCR, rega);
reg += 0x10;
}
}
- andSISIDXREG(SISCR, 0x6e, 0xfc);
+ SiS_SetRegAND(SISCR, 0x6e, 0xfc);
ptr = NULL;
if(ivideo->haveXGIROM) {
ptr = (const u8 *)&bios[index];
}
for(i = 0; i < 4; i++) {
- setSISIDXREG(SISCR, 0x6e, 0xfc, i);
+ SiS_SetRegANDOR(SISCR, 0x6e, 0xfc, i);
reg = 0x00;
for(j = 0; j < 2; j++) {
regd = 0;
if(regd & 0x01) reg |= 0x01;
if(regd & 0x02) reg |= 0x02;
regd >>= 2;
- outSISIDXREG(SISCR, 0x6f, reg);
- inSISIDXREG(SISCR, 0x6f, reg);
- inSISIDXREG(SISCR, 0x6f, reg);
+ SiS_SetReg(SISCR, 0x6f, reg);
+ reg = SiS_GetReg(SISCR, 0x6f);
+ reg = SiS_GetReg(SISCR, 0x6f);
reg += 0x08;
}
}
ptr = (const u8 *)&bios[0x148];
}
for(i = 0, j = 0; i < 2; i++, j += 8) {
- outSISIDXREG(SISCR, 0x80 + i, ptr[j + regb]);
+ SiS_SetReg(SISCR, 0x80 + i, ptr[j + regb]);
}
- andSISIDXREG(SISCR, 0x89, 0x8f);
+ SiS_SetRegAND(SISCR, 0x89, 0x8f);
ptr = cs45a;
if(ivideo->haveXGIROM) {
if(regd & 0x01) reg |= 0x01;
if(regd & 0x02) reg |= 0x02;
regd >>= 2;
- outSISIDXREG(SISCR, 0x89, reg);
- inSISIDXREG(SISCR, 0x89, reg);
- inSISIDXREG(SISCR, 0x89, reg);
+ SiS_SetReg(SISCR, 0x89, reg);
+ reg = SiS_GetReg(SISCR, 0x89);
+ reg = SiS_GetReg(SISCR, 0x89);
reg += 0x10;
}
v3 = bios[0x120 + regb];
v4 = bios[0x1ca];
}
- outSISIDXREG(SISCR, 0x45, v1 & 0x0f);
- outSISIDXREG(SISCR, 0x99, (v1 >> 4) & 0x07);
- orSISIDXREG(SISCR, 0x40, v1 & 0x80);
- outSISIDXREG(SISCR, 0x41, v2);
+ SiS_SetReg(SISCR, 0x45, v1 & 0x0f);
+ SiS_SetReg(SISCR, 0x99, (v1 >> 4) & 0x07);
+ SiS_SetRegOR(SISCR, 0x40, v1 & 0x80);
+ SiS_SetReg(SISCR, 0x41, v2);
ptr = cs170;
if(ivideo->haveXGIROM) {
ptr = (const u8 *)&bios[0x170];
}
for(i = 0, j = 0; i < 7; i++, j += 8) {
- outSISIDXREG(SISCR, 0x90 + i, ptr[j + regb]);
+ SiS_SetReg(SISCR, 0x90 + i, ptr[j + regb]);
}
- outSISIDXREG(SISCR, 0x59, v3);
+ SiS_SetReg(SISCR, 0x59, v3);
ptr = cs1a8;
if(ivideo->haveXGIROM) {
ptr = (const u8 *)&bios[0x1a8];
}
for(i = 0, j = 0; i < 3; i++, j += 8) {
- outSISIDXREG(SISCR, 0xc3 + i, ptr[j + regb]);
+ SiS_SetReg(SISCR, 0xc3 + i, ptr[j + regb]);
}
ptr = cs100;
ptr = (const u8 *)&bios[0x100];
}
for(i = 0, j = 0; i < 2; i++, j += 8) {
- outSISIDXREG(SISCR, 0x8a + i, ptr[j + regb]);
+ SiS_SetReg(SISCR, 0x8a + i, ptr[j + regb]);
}
- outSISIDXREG(SISCR, 0xcf, v4);
+ SiS_SetReg(SISCR, 0xcf, v4);
- outSISIDXREG(SISCR, 0x83, 0x09);
- outSISIDXREG(SISCR, 0x87, 0x00);
+ SiS_SetReg(SISCR, 0x83, 0x09);
+ SiS_SetReg(SISCR, 0x87, 0x00);
if(ivideo->chip == XGI_40) {
if( (ivideo->revision_id == 1) ||
(ivideo->revision_id == 2) ) {
- outSISIDXREG(SISCR, 0x8c, 0x87);
+ SiS_SetReg(SISCR, 0x8c, 0x87);
}
}
- outSISIDXREG(SISSR, 0x17, 0x00);
- outSISIDXREG(SISSR, 0x1a, 0x87);
+ SiS_SetReg(SISSR, 0x17, 0x00);
+ SiS_SetReg(SISSR, 0x1a, 0x87);
if(ivideo->chip == XGI_20) {
- outSISIDXREG(SISSR, 0x15, 0x00);
- outSISIDXREG(SISSR, 0x1c, 0x00);
+ SiS_SetReg(SISSR, 0x15, 0x00);
+ SiS_SetReg(SISSR, 0x1c, 0x00);
}
ramtype = 0x00; v1 = 0x10;
}
if(!(ramtype & 0x80)) {
if(ivideo->chip == XGI_20) {
- outSISIDXREG(SISCR, 0x97, v1);
- inSISIDXREG(SISCR, 0x97, reg);
+ SiS_SetReg(SISCR, 0x97, v1);
+ reg = SiS_GetReg(SISCR, 0x97);
if(reg & 0x10) {
ramtype = (reg & 0x01) << 1;
}
} else {
- inSISIDXREG(SISSR, 0x39, reg);
+ reg = SiS_GetReg(SISSR, 0x39);
ramtype = reg & 0x02;
if(!(ramtype)) {
- inSISIDXREG(SISSR, 0x3a, reg);
+ reg = SiS_GetReg(SISSR, 0x3a);
ramtype = (reg >> 1) & 0x01;
}
}
v2 = bios[regb + 0x160];
v3 = bios[regb + 0x168];
}
- outSISIDXREG(SISCR, 0x82, v1);
- outSISIDXREG(SISCR, 0x85, v2);
- outSISIDXREG(SISCR, 0x86, v3);
+ SiS_SetReg(SISCR, 0x82, v1);
+ SiS_SetReg(SISCR, 0x85, v2);
+ SiS_SetReg(SISCR, 0x86, v3);
} else {
- outSISIDXREG(SISCR, 0x82, 0x88);
- outSISIDXREG(SISCR, 0x86, 0x00);
- inSISIDXREG(SISCR, 0x86, reg);
- outSISIDXREG(SISCR, 0x86, 0x88);
- inSISIDXREG(SISCR, 0x86, reg);
- outSISIDXREG(SISCR, 0x86, bios[regb + 0x168]);
- outSISIDXREG(SISCR, 0x82, 0x77);
- outSISIDXREG(SISCR, 0x85, 0x00);
- inSISIDXREG(SISCR, 0x85, reg);
- outSISIDXREG(SISCR, 0x85, 0x88);
- inSISIDXREG(SISCR, 0x85, reg);
- outSISIDXREG(SISCR, 0x85, bios[regb + 0x160]);
- outSISIDXREG(SISCR, 0x82, bios[regb + 0x158]);
+ SiS_SetReg(SISCR, 0x82, 0x88);
+ SiS_SetReg(SISCR, 0x86, 0x00);
+ reg = SiS_GetReg(SISCR, 0x86);
+ SiS_SetReg(SISCR, 0x86, 0x88);
+ reg = SiS_GetReg(SISCR, 0x86);
+ SiS_SetReg(SISCR, 0x86, bios[regb + 0x168]);
+ SiS_SetReg(SISCR, 0x82, 0x77);
+ SiS_SetReg(SISCR, 0x85, 0x00);
+ reg = SiS_GetReg(SISCR, 0x85);
+ SiS_SetReg(SISCR, 0x85, 0x88);
+ reg = SiS_GetReg(SISCR, 0x85);
+ SiS_SetReg(SISCR, 0x85, bios[regb + 0x160]);
+ SiS_SetReg(SISCR, 0x82, bios[regb + 0x158]);
}
if(ivideo->chip == XGI_40) {
- outSISIDXREG(SISCR, 0x97, 0x00);
+ SiS_SetReg(SISCR, 0x97, 0x00);
}
- outSISIDXREG(SISCR, 0x98, 0x01);
- outSISIDXREG(SISCR, 0x9a, 0x02);
+ SiS_SetReg(SISCR, 0x98, 0x01);
+ SiS_SetReg(SISCR, 0x9a, 0x02);
- outSISIDXREG(SISSR, 0x18, 0x01);
+ SiS_SetReg(SISSR, 0x18, 0x01);
if((ivideo->chip == XGI_20) ||
(ivideo->revision_id == 2)) {
- outSISIDXREG(SISSR, 0x19, 0x40);
+ SiS_SetReg(SISSR, 0x19, 0x40);
} else {
- outSISIDXREG(SISSR, 0x19, 0x20);
+ SiS_SetReg(SISSR, 0x19, 0x20);
}
- outSISIDXREG(SISSR, 0x16, 0x00);
- outSISIDXREG(SISSR, 0x16, 0x80);
+ SiS_SetReg(SISSR, 0x16, 0x00);
+ SiS_SetReg(SISSR, 0x16, 0x80);
if((ivideo->chip == XGI_20) || (bios[0x1cb] != 0x0c)) {
sisfb_post_xgi_delay(ivideo, 0x43);
sisfb_post_xgi_delay(ivideo, 0x43);
sisfb_post_xgi_delay(ivideo, 0x43);
- outSISIDXREG(SISSR, 0x18, 0x00);
+ SiS_SetReg(SISSR, 0x18, 0x00);
if((ivideo->chip == XGI_20) ||
(ivideo->revision_id == 2)) {
- outSISIDXREG(SISSR, 0x19, 0x40);
+ SiS_SetReg(SISSR, 0x19, 0x40);
} else {
- outSISIDXREG(SISSR, 0x19, 0x20);
+ SiS_SetReg(SISSR, 0x19, 0x20);
}
} else if((ivideo->chip == XGI_40) && (bios[0x1cb] == 0x0c)) {
- /* outSISIDXREG(SISSR, 0x16, 0x0c); */ /* ? */
+ /* SiS_SetReg(SISSR, 0x16, 0x0c); */ /* ? */
}
- outSISIDXREG(SISSR, 0x16, 0x00);
- outSISIDXREG(SISSR, 0x16, 0x80);
+ SiS_SetReg(SISSR, 0x16, 0x00);
+ SiS_SetReg(SISSR, 0x16, 0x80);
sisfb_post_xgi_delay(ivideo, 4);
v1 = 0x31; v2 = 0x03; v3 = 0x83; v4 = 0x03; v5 = 0x83;
if(ivideo->haveXGIROM) {
v4 = bios[index + 2];
v5 = bios[index + 3];
}
- outSISIDXREG(SISSR, 0x18, v1);
- outSISIDXREG(SISSR, 0x19, ((ivideo->chip == XGI_20) ? 0x02 : 0x01));
- outSISIDXREG(SISSR, 0x16, v2);
- outSISIDXREG(SISSR, 0x16, v3);
+ SiS_SetReg(SISSR, 0x18, v1);
+ SiS_SetReg(SISSR, 0x19, ((ivideo->chip == XGI_20) ? 0x02 : 0x01));
+ SiS_SetReg(SISSR, 0x16, v2);
+ SiS_SetReg(SISSR, 0x16, v3);
sisfb_post_xgi_delay(ivideo, 0x43);
- outSISIDXREG(SISSR, 0x1b, 0x03);
+ SiS_SetReg(SISSR, 0x1b, 0x03);
sisfb_post_xgi_delay(ivideo, 0x22);
- outSISIDXREG(SISSR, 0x18, v1);
- outSISIDXREG(SISSR, 0x19, 0x00);
- outSISIDXREG(SISSR, 0x16, v4);
- outSISIDXREG(SISSR, 0x16, v5);
- outSISIDXREG(SISSR, 0x1b, 0x00);
+ SiS_SetReg(SISSR, 0x18, v1);
+ SiS_SetReg(SISSR, 0x19, 0x00);
+ SiS_SetReg(SISSR, 0x16, v4);
+ SiS_SetReg(SISSR, 0x16, v5);
+ SiS_SetReg(SISSR, 0x1b, 0x00);
break;
case 1:
- outSISIDXREG(SISCR, 0x82, 0x77);
- outSISIDXREG(SISCR, 0x86, 0x00);
- inSISIDXREG(SISCR, 0x86, reg);
- outSISIDXREG(SISCR, 0x86, 0x88);
- inSISIDXREG(SISCR, 0x86, reg);
+ SiS_SetReg(SISCR, 0x82, 0x77);
+ SiS_SetReg(SISCR, 0x86, 0x00);
+ reg = SiS_GetReg(SISCR, 0x86);
+ SiS_SetReg(SISCR, 0x86, 0x88);
+ reg = SiS_GetReg(SISCR, 0x86);
v1 = cs168[regb]; v2 = cs160[regb]; v3 = cs158[regb];
if(ivideo->haveXGIROM) {
v1 = bios[regb + 0x168];
v2 = bios[regb + 0x160];
v3 = bios[regb + 0x158];
}
- outSISIDXREG(SISCR, 0x86, v1);
- outSISIDXREG(SISCR, 0x82, 0x77);
- outSISIDXREG(SISCR, 0x85, 0x00);
- inSISIDXREG(SISCR, 0x85, reg);
- outSISIDXREG(SISCR, 0x85, 0x88);
- inSISIDXREG(SISCR, 0x85, reg);
- outSISIDXREG(SISCR, 0x85, v2);
- outSISIDXREG(SISCR, 0x82, v3);
- outSISIDXREG(SISCR, 0x98, 0x01);
- outSISIDXREG(SISCR, 0x9a, 0x02);
-
- outSISIDXREG(SISSR, 0x28, 0x64);
- outSISIDXREG(SISSR, 0x29, 0x63);
+ SiS_SetReg(SISCR, 0x86, v1);
+ SiS_SetReg(SISCR, 0x82, 0x77);
+ SiS_SetReg(SISCR, 0x85, 0x00);
+ reg = SiS_GetReg(SISCR, 0x85);
+ SiS_SetReg(SISCR, 0x85, 0x88);
+ reg = SiS_GetReg(SISCR, 0x85);
+ SiS_SetReg(SISCR, 0x85, v2);
+ SiS_SetReg(SISCR, 0x82, v3);
+ SiS_SetReg(SISCR, 0x98, 0x01);
+ SiS_SetReg(SISCR, 0x9a, 0x02);
+
+ SiS_SetReg(SISSR, 0x28, 0x64);
+ SiS_SetReg(SISSR, 0x29, 0x63);
sisfb_post_xgi_delay(ivideo, 15);
- outSISIDXREG(SISSR, 0x18, 0x00);
- outSISIDXREG(SISSR, 0x19, 0x20);
- outSISIDXREG(SISSR, 0x16, 0x00);
- outSISIDXREG(SISSR, 0x16, 0x80);
- outSISIDXREG(SISSR, 0x18, 0xc5);
- outSISIDXREG(SISSR, 0x19, 0x23);
- outSISIDXREG(SISSR, 0x16, 0x00);
- outSISIDXREG(SISSR, 0x16, 0x80);
+ SiS_SetReg(SISSR, 0x18, 0x00);
+ SiS_SetReg(SISSR, 0x19, 0x20);
+ SiS_SetReg(SISSR, 0x16, 0x00);
+ SiS_SetReg(SISSR, 0x16, 0x80);
+ SiS_SetReg(SISSR, 0x18, 0xc5);
+ SiS_SetReg(SISSR, 0x19, 0x23);
+ SiS_SetReg(SISSR, 0x16, 0x00);
+ SiS_SetReg(SISSR, 0x16, 0x80);
sisfb_post_xgi_delay(ivideo, 1);
- outSISIDXREG(SISCR, 0x97,0x11);
+ SiS_SetReg(SISCR, 0x97, 0x11);
sisfb_post_xgi_setclocks(ivideo, regb);
sisfb_post_xgi_delay(ivideo, 0x46);
- outSISIDXREG(SISSR, 0x18, 0xc5);
- outSISIDXREG(SISSR, 0x19, 0x23);
- outSISIDXREG(SISSR, 0x16, 0x00);
- outSISIDXREG(SISSR, 0x16, 0x80);
+ SiS_SetReg(SISSR, 0x18, 0xc5);
+ SiS_SetReg(SISSR, 0x19, 0x23);
+ SiS_SetReg(SISSR, 0x16, 0x00);
+ SiS_SetReg(SISSR, 0x16, 0x80);
sisfb_post_xgi_delay(ivideo, 1);
- outSISIDXREG(SISSR, 0x1b, 0x04);
+ SiS_SetReg(SISSR, 0x1b, 0x04);
sisfb_post_xgi_delay(ivideo, 1);
- outSISIDXREG(SISSR, 0x1b, 0x00);
+ SiS_SetReg(SISSR, 0x1b, 0x00);
sisfb_post_xgi_delay(ivideo, 1);
v1 = 0x31;
if(ivideo->haveXGIROM) {
v1 = bios[0xf0];
}
- outSISIDXREG(SISSR, 0x18, v1);
- outSISIDXREG(SISSR, 0x19, 0x06);
- outSISIDXREG(SISSR, 0x16, 0x04);
- outSISIDXREG(SISSR, 0x16, 0x84);
+ SiS_SetReg(SISSR, 0x18, v1);
+ SiS_SetReg(SISSR, 0x19, 0x06);
+ SiS_SetReg(SISSR, 0x16, 0x04);
+ SiS_SetReg(SISSR, 0x16, 0x84);
sisfb_post_xgi_delay(ivideo, 1);
break;
default:
if((ivideo->chip == XGI_40) &&
((ivideo->revision_id == 1) ||
(ivideo->revision_id == 2))) {
- outSISIDXREG(SISCR, 0x82, bios[regb + 0x158]);
- outSISIDXREG(SISCR, 0x85, bios[regb + 0x160]);
- outSISIDXREG(SISCR, 0x86, bios[regb + 0x168]);
+ SiS_SetReg(SISCR, 0x82, bios[regb + 0x158]);
+ SiS_SetReg(SISCR, 0x85, bios[regb + 0x160]);
+ SiS_SetReg(SISCR, 0x86, bios[regb + 0x168]);
} else {
- outSISIDXREG(SISCR, 0x82, 0x88);
- outSISIDXREG(SISCR, 0x86, 0x00);
- inSISIDXREG(SISCR, 0x86, reg);
- outSISIDXREG(SISCR, 0x86, 0x88);
- outSISIDXREG(SISCR, 0x82, 0x77);
- outSISIDXREG(SISCR, 0x85, 0x00);
- inSISIDXREG(SISCR, 0x85, reg);
- outSISIDXREG(SISCR, 0x85, 0x88);
- inSISIDXREG(SISCR, 0x85, reg);
+ SiS_SetReg(SISCR, 0x82, 0x88);
+ SiS_SetReg(SISCR, 0x86, 0x00);
+ reg = SiS_GetReg(SISCR, 0x86);
+ SiS_SetReg(SISCR, 0x86, 0x88);
+ SiS_SetReg(SISCR, 0x82, 0x77);
+ SiS_SetReg(SISCR, 0x85, 0x00);
+ reg = SiS_GetReg(SISCR, 0x85);
+ SiS_SetReg(SISCR, 0x85, 0x88);
+ reg = SiS_GetReg(SISCR, 0x85);
v1 = cs160[regb]; v2 = cs158[regb];
if(ivideo->haveXGIROM) {
v1 = bios[regb + 0x160];
v2 = bios[regb + 0x158];
}
- outSISIDXREG(SISCR, 0x85, v1);
- outSISIDXREG(SISCR, 0x82, v2);
+ SiS_SetReg(SISCR, 0x85, v1);
+ SiS_SetReg(SISCR, 0x82, v2);
}
if(ivideo->chip == XGI_40) {
- outSISIDXREG(SISCR, 0x97, 0x11);
+ SiS_SetReg(SISCR, 0x97, 0x11);
}
if((ivideo->chip == XGI_40) && (ivideo->revision_id == 2)) {
- outSISIDXREG(SISCR, 0x98, 0x01);
+ SiS_SetReg(SISCR, 0x98, 0x01);
} else {
- outSISIDXREG(SISCR, 0x98, 0x03);
+ SiS_SetReg(SISCR, 0x98, 0x03);
}
- outSISIDXREG(SISCR, 0x9a, 0x02);
+ SiS_SetReg(SISCR, 0x9a, 0x02);
if(ivideo->chip == XGI_40) {
- outSISIDXREG(SISSR, 0x18, 0x01);
+ SiS_SetReg(SISSR, 0x18, 0x01);
} else {
- outSISIDXREG(SISSR, 0x18, 0x00);
+ SiS_SetReg(SISSR, 0x18, 0x00);
}
- outSISIDXREG(SISSR, 0x19, 0x40);
- outSISIDXREG(SISSR, 0x16, 0x00);
- outSISIDXREG(SISSR, 0x16, 0x80);
+ SiS_SetReg(SISSR, 0x19, 0x40);
+ SiS_SetReg(SISSR, 0x16, 0x00);
+ SiS_SetReg(SISSR, 0x16, 0x80);
if((ivideo->chip == XGI_40) && (bios[0x1cb] != 0x0c)) {
sisfb_post_xgi_delay(ivideo, 0x43);
sisfb_post_xgi_delay(ivideo, 0x43);
sisfb_post_xgi_delay(ivideo, 0x43);
- outSISIDXREG(SISSR, 0x18, 0x00);
- outSISIDXREG(SISSR, 0x19, 0x40);
- outSISIDXREG(SISSR, 0x16, 0x00);
- outSISIDXREG(SISSR, 0x16, 0x80);
+ SiS_SetReg(SISSR, 0x18, 0x00);
+ SiS_SetReg(SISSR, 0x19, 0x40);
+ SiS_SetReg(SISSR, 0x16, 0x00);
+ SiS_SetReg(SISSR, 0x16, 0x80);
}
sisfb_post_xgi_delay(ivideo, 4);
&
git.openpandora.org / pandora-kernel.git / commitdiff