Merge git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
authorLinus Torvalds <torvalds@g5.osdl.org>
Wed, 4 Oct 2006 15:16:37 +0000 (08:16 -0700)
committerLinus Torvalds <torvalds@g5.osdl.org>
Wed, 4 Oct 2006 15:16:37 +0000 (08:16 -0700)
* git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: (25 commits)
  [POWERPC] Add support for the mpc832x mds board
  [POWERPC] Add initial support for the e300c2 core
  [POWERPC] Add MPC8360EMDS default dts file
  [POWERPC] Add MPC8360EMDS board support
  [POWERPC] Add QUICC Engine (QE) infrastructure
  [POWERPC] Add QE device tree node definition
  [POWERPC] Don't try to just continue if xmon has no input device
  [POWERPC] Fix a printk in pseries_mpic_init_IRQ
  [POWERPC] Get default baud rate in udbg_scc
  [POWERPC] Fix zImage.coff on oldworld PowerMac
  [POWERPC] Fix xmon=off and cleanup xmon initialisation
  [POWERPC] Cleanup include/asm-powerpc/xmon.h
  [POWERPC] Update swim3 printk after blkdev.h change
  [POWERPC] Cell interrupt rework
  POWERPC: mpc82xx merge: board-specific/platform stuff(resend)
  POWERPC: 8272ads merge to powerpc: common stuff
  POWERPC: Added devicetree for mpc8272ads board
  [POWERPC] iSeries has no legacy I/O
  [POWERPC] implement BEGIN/END_FW_FTR_SECTION
  [POWERPC] iSeries does not need pcibios_fixup_resources
  ...

62 files changed:
Documentation/powerpc/booting-without-of.txt
arch/powerpc/Kconfig
arch/powerpc/boot/dts/mpc8272ads.dts [new file with mode: 0644]
arch/powerpc/boot/dts/mpc8360emds.dts [new file with mode: 0644]
arch/powerpc/boot/zImage.coff.lds.S
arch/powerpc/configs/mpc8360emds_defconfig [new file with mode: 0644]
arch/powerpc/kernel/cputable.c
arch/powerpc/kernel/entry_64.S
arch/powerpc/kernel/head_64.S
arch/powerpc/kernel/misc_64.S
arch/powerpc/kernel/pci_64.c
arch/powerpc/kernel/setup-common.c
arch/powerpc/kernel/setup_32.c
arch/powerpc/kernel/setup_64.c
arch/powerpc/kernel/vmlinux.lds.S
arch/powerpc/mm/pgtable_64.c
arch/powerpc/mm/slb_low.S
arch/powerpc/platforms/82xx/Kconfig [new file with mode: 0644]
arch/powerpc/platforms/82xx/Makefile [new file with mode: 0644]
arch/powerpc/platforms/82xx/m82xx_pci.h [new file with mode: 0644]
arch/powerpc/platforms/82xx/mpc82xx.c [new file with mode: 0644]
arch/powerpc/platforms/82xx/mpc82xx_ads.c [new file with mode: 0644]
arch/powerpc/platforms/82xx/pq2ads.h [new file with mode: 0644]
arch/powerpc/platforms/83xx/Kconfig
arch/powerpc/platforms/83xx/mpc832x_mds.c [new file with mode: 0644]
arch/powerpc/platforms/83xx/mpc832x_mds.h [new file with mode: 0644]
arch/powerpc/platforms/83xx/mpc8360e_pb.c [new file with mode: 0644]
arch/powerpc/platforms/cell/interrupt.c
arch/powerpc/platforms/cell/interrupt.h
arch/powerpc/platforms/cell/spider-pic.c
arch/powerpc/platforms/cell/spu_base.c
arch/powerpc/platforms/iseries/pci.c
arch/powerpc/platforms/iseries/setup.c
arch/powerpc/platforms/powermac/udbg_scc.c
arch/powerpc/platforms/pseries/setup.c
arch/powerpc/sysdev/Makefile
arch/powerpc/sysdev/cpm2_pic.c
arch/powerpc/sysdev/cpm2_pic.h
arch/powerpc/sysdev/fsl_soc.c
arch/powerpc/sysdev/qe_lib/Kconfig [new file with mode: 0644]
arch/powerpc/sysdev/qe_lib/Makefile [new file with mode: 0644]
arch/powerpc/sysdev/qe_lib/qe.c [new file with mode: 0644]
arch/powerpc/sysdev/qe_lib/qe_ic.c [new file with mode: 0644]
arch/powerpc/sysdev/qe_lib/qe_ic.h [new file with mode: 0644]
arch/powerpc/sysdev/qe_lib/qe_io.c [new file with mode: 0644]
arch/powerpc/sysdev/qe_lib/ucc.c [new file with mode: 0644]
arch/powerpc/sysdev/qe_lib/ucc_fast.c [new file with mode: 0644]
arch/powerpc/sysdev/qe_lib/ucc_slow.c [new file with mode: 0644]
arch/powerpc/xmon/xmon.c
drivers/block/swim3.c
drivers/char/hvc_iseries.c
drivers/char/hvc_vio.c
include/asm-powerpc/firmware.h
include/asm-powerpc/immap_qe.h [new file with mode: 0644]
include/asm-powerpc/qe.h [new file with mode: 0644]
include/asm-powerpc/qe_ic.h [new file with mode: 0644]
include/asm-powerpc/system.h
include/asm-powerpc/ucc.h [new file with mode: 0644]
include/asm-powerpc/ucc_fast.h [new file with mode: 0644]
include/asm-powerpc/ucc_slow.h [new file with mode: 0644]
include/asm-powerpc/xmon.h
include/linux/fsl_devices.h

index 1ccc8a5..27b457c 100644 (file)
@@ -1440,6 +1440,258 @@ platforms are moved over to use the flattened-device-tree model.
                descriptor-types-mask = <012b0ebf>;
        };
 
+   h) Board Control and Status (BCSR)
+
+   Required properties:
+
+    - device_type : Should be "board-control"
+    - reg : Offset and length of the register set for the device
+
+    Example:
+
+       bcsr@f8000000 {
+               device_type = "board-control";
+               reg = <f8000000 8000>;
+       };
+
+   i) Freescale QUICC Engine module (QE)
+   This represents qe module that is installed on PowerQUICC II Pro.
+   Hopefully it will merge backward compatibility with CPM/CPM2.
+   Basically, it is a bus of devices, that could act more or less
+   as a complete entity (UCC, USB etc ). All of them should be siblings on
+   the "root" qe node, using the common properties from there.
+   The description below applies to the the qe of MPC8360 and
+   more nodes and properties would be extended in the future.
+
+   i) Root QE device
+
+   Required properties:
+   - device_type : should be "qe";
+   - model : precise model of the QE, Can be "QE", "CPM", or "CPM2"
+   - reg : offset and length of the device registers.
+   - bus-frequency : the clock frequency for QUICC Engine.
+
+   Recommended properties
+   - brg-frequency : the internal clock source frequency for baud-rate
+     generators in Hz.
+
+   Example:
+       qe@e0100000 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               #interrupt-cells = <2>;
+               device_type = "qe";
+               model = "QE";
+               ranges = <0 e0100000 00100000>;
+               reg = <e0100000 480>;
+               brg-frequency = <0>;
+               bus-frequency = <179A7B00>;
+       }
+
+
+   ii) SPI (Serial Peripheral Interface)
+
+   Required properties:
+   - device_type : should be "spi".
+   - compatible : should be "fsl_spi".
+   - mode : the spi operation mode, it can be "cpu" or "qe".
+   - reg : Offset and length of the register set for the device
+   - interrupts : <a b> where a is the interrupt number and b is a
+     field that represents an encoding of the sense and level
+     information for the interrupt.  This should be encoded based on
+     the information in section 2) depending on the type of interrupt
+     controller you have.
+   - interrupt-parent : the phandle for the interrupt controller that
+     services interrupts for this device.
+
+   Example:
+       spi@4c0 {
+               device_type = "spi";
+               compatible = "fsl_spi";
+               reg = <4c0 40>;
+               interrupts = <82 0>;
+               interrupt-parent = <700>;
+               mode = "cpu";
+       };
+
+
+   iii) USB (Universal Serial Bus Controller)
+
+   Required properties:
+   - device_type : should be "usb".
+   - compatible : could be "qe_udc" or "fhci-hcd".
+   - mode : the could be "host" or "slave".
+   - reg : Offset and length of the register set for the device
+   - interrupts : <a b> where a is the interrupt number and b is a
+     field that represents an encoding of the sense and level
+     information for the interrupt.  This should be encoded based on
+     the information in section 2) depending on the type of interrupt
+     controller you have.
+   - interrupt-parent : the phandle for the interrupt controller that
+     services interrupts for this device.
+
+   Example(slave):
+       usb@6c0 {
+               device_type = "usb";
+               compatible = "qe_udc";
+               reg = <6c0 40>;
+               interrupts = <8b 0>;
+               interrupt-parent = <700>;
+               mode = "slave";
+       };
+
+
+   iv) UCC (Unified Communications Controllers)
+
+   Required properties:
+   - device_type : should be "network", "hldc", "uart", "transparent"
+    "bisync" or "atm".
+   - compatible : could be "ucc_geth" or "fsl_atm" and so on.
+   - model : should be "UCC".
+   - device-id : the ucc number(1-8), corresponding to UCCx in UM.
+   - reg : Offset and length of the register set for the device
+   - interrupts : <a b> where a is the interrupt number and b is a
+     field that represents an encoding of the sense and level
+     information for the interrupt.  This should be encoded based on
+     the information in section 2) depending on the type of interrupt
+     controller you have.
+   - interrupt-parent : the phandle for the interrupt controller that
+     services interrupts for this device.
+   - pio-handle : The phandle for the Parallel I/O port configuration.
+   - rx-clock : represents the UCC receive clock source.
+     0x00 : clock source is disabled;
+     0x1~0x10 : clock source is BRG1~BRG16 respectively;
+     0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
+   - tx-clock: represents the UCC transmit clock source;
+     0x00 : clock source is disabled;
+     0x1~0x10 : clock source is BRG1~BRG16 respectively;
+     0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
+
+   Required properties for network device_type:
+   - mac-address : list of bytes representing the ethernet address.
+   - phy-handle : The phandle for the PHY connected to this controller.
+
+   Example:
+       ucc@2000 {
+               device_type = "network";
+               compatible = "ucc_geth";
+               model = "UCC";
+               device-id = <1>;
+               reg = <2000 200>;
+               interrupts = <a0 0>;
+               interrupt-parent = <700>;
+               mac-address = [ 00 04 9f 00 23 23 ];
+               rx-clock = "none";
+               tx-clock = "clk9";
+               phy-handle = <212000>;
+               pio-handle = <140001>;
+       };
+
+
+   v) Parallel I/O Ports
+
+   This node configures Parallel I/O ports for CPUs with QE support.
+   The node should reside in the "soc" node of the tree.  For each
+   device that using parallel I/O ports, a child node should be created.
+   See the definition of the Pin configuration nodes below for more
+   information.
+
+   Required properties:
+   - device_type : should be "par_io".
+   - reg : offset to the register set and its length.
+   - num-ports : number of Parallel I/O ports
+
+   Example:
+       par_io@1400 {
+               reg = <1400 100>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               device_type = "par_io";
+               num-ports = <7>;
+               ucc_pin@01 {
+                       ......
+               };
+
+
+   vi) Pin configuration nodes
+
+   Required properties:
+   - linux,phandle : phandle of this node; likely referenced by a QE
+     device.
+   - pio-map : array of pin configurations.  Each pin is defined by 6
+     integers.  The six numbers are respectively: port, pin, dir,
+     open_drain, assignment, has_irq.
+     - port : port number of the pin; 0-6 represent port A-G in UM.
+     - pin : pin number in the port.
+     - dir : direction of the pin, should encode as follows:
+
+       0 = The pin is disabled
+       1 = The pin is an output
+       2 = The pin is an input
+       3 = The pin is I/O
+
+     - open_drain : indicates the pin is normal or wired-OR:
+
+       0 = The pin is actively driven as an output
+       1 = The pin is an open-drain driver. As an output, the pin is
+           driven active-low, otherwise it is three-stated.
+
+     - assignment : function number of the pin according to the Pin Assignment
+       tables in User Manual.  Each pin can have up to 4 possible functions in
+       QE and two options for CPM.
+     - has_irq : indicates if the pin is used as source of exteral
+       interrupts.
+
+   Example:
+       ucc_pin@01 {
+               linux,phandle = <140001>;
+               pio-map = <
+               /* port  pin  dir  open_drain  assignment  has_irq */
+                       0  3  1  0  1  0        /* TxD0 */
+                       0  4  1  0  1  0        /* TxD1 */
+                       0  5  1  0  1  0        /* TxD2 */
+                       0  6  1  0  1  0        /* TxD3 */
+                       1  6  1  0  3  0        /* TxD4 */
+                       1  7  1  0  1  0        /* TxD5 */
+                       1  9  1  0  2  0        /* TxD6 */
+                       1  a  1  0  2  0        /* TxD7 */
+                       0  9  2  0  1  0        /* RxD0 */
+                       0  a  2  0  1  0        /* RxD1 */
+                       0  b  2  0  1  0        /* RxD2 */
+                       0  c  2  0  1  0        /* RxD3 */
+                       0  d  2  0  1  0        /* RxD4 */
+                       1  1  2  0  2  0        /* RxD5 */
+                       1  0  2  0  2  0        /* RxD6 */
+                       1  4  2  0  2  0        /* RxD7 */
+                       0  7  1  0  1  0        /* TX_EN */
+                       0  8  1  0  1  0        /* TX_ER */
+                       0  f  2  0  1  0        /* RX_DV */
+                       0  10 2  0  1  0        /* RX_ER */
+                       0  0  2  0  1  0        /* RX_CLK */
+                       2  9  1  0  3  0        /* GTX_CLK - CLK10 */
+                       2  8  2  0  1  0>;      /* GTX125 - CLK9 */
+       };
+
+   vii) Multi-User RAM (MURAM)
+
+   Required properties:
+   - device_type : should be "muram".
+   - mode : the could be "host" or "slave".
+   - ranges : Should be defined as specified in 1) to describe the
+      translation of MURAM addresses.
+   - data-only : sub-node which defines the address area under MURAM
+      bus that can be allocated as data/parameter
+
+   Example:
+
+       muram@10000 {
+               device_type = "muram";
+               ranges = <0 00010000 0000c000>;
+
+               data-only@0{
+                       reg = <0 c000>;
+               };
+       };
 
    More devices will be defined as this spec matures.
 
index 96ef656..8b69104 100644 (file)
@@ -338,10 +338,6 @@ config PPC_MULTIPLATFORM
          RS/6000 machine, an Apple machine, or a PReP, CHRP,
          Maple or Cell-based machine.
 
-config PPC_ISERIES
-       bool "IBM Legacy iSeries"
-       depends on PPC64
-
 config EMBEDDED6xx
        bool "Embedded 6xx/7xx/7xxx-based board"
        depends on PPC32 && (BROKEN||BROKEN_ON_SMP)
@@ -355,6 +351,16 @@ config APUS
          <http://linux-apus.sourceforge.net/>.
 endchoice
 
+config QUICC_ENGINE
+       bool
+       depends on PPC_MPC836x || PPC_MPC832x
+       default y
+       help
+         The QUICC Engine (QE) is a new generation of communications
+         coprocessors on Freescale embedded CPUs (akin to CPM in older chips).
+         Selecting this option means that you wish to build a kernel
+         for a machine with a QE coprocessor.
+
 config PPC_PSERIES
        depends on PPC_MULTIPLATFORM && PPC64
        bool "IBM pSeries & new (POWER5-based) iSeries"
@@ -365,6 +371,10 @@ config PPC_PSERIES
        select PPC_UDBG_16550
        default y
 
+config PPC_ISERIES
+       bool "IBM Legacy iSeries"
+       depends on PPC_MULTIPLATFORM && PPC64
+
 config PPC_CHRP
        bool "Common Hardware Reference Platform (CHRP) based machines"
        depends on PPC_MULTIPLATFORM && PPC32
@@ -594,6 +604,7 @@ endmenu
 
 source arch/powerpc/platforms/embedded6xx/Kconfig
 source arch/powerpc/platforms/4xx/Kconfig
+source arch/powerpc/platforms/82xx/Kconfig
 source arch/powerpc/platforms/83xx/Kconfig
 source arch/powerpc/platforms/85xx/Kconfig
 source arch/powerpc/platforms/86xx/Kconfig
@@ -1058,6 +1069,8 @@ source "fs/Kconfig"
 
 # XXX source "arch/ppc/8260_io/Kconfig"
 
+source "arch/powerpc/sysdev/qe_lib/Kconfig"
+
 source "arch/powerpc/platforms/iseries/Kconfig"
 
 source "lib/Kconfig"
diff --git a/arch/powerpc/boot/dts/mpc8272ads.dts b/arch/powerpc/boot/dts/mpc8272ads.dts
new file mode 100644 (file)
index 0000000..34efdd0
--- /dev/null
@@ -0,0 +1,223 @@
+/*
+ * MPC8272 ADS Device Tree Source
+ *
+ * Copyright 2005 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/ {
+       model = "MPC8272ADS";
+       compatible = "MPC8260ADS";
+       #address-cells = <1>;
+       #size-cells = <1>;
+       linux,phandle = <100>;
+
+       cpus {
+               #cpus = <1>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               linux,phandle = <200>;
+
+               PowerPC,8272@0 {
+                       device_type = "cpu";
+                       reg = <0>;
+                       d-cache-line-size = <20>;       // 32 bytes
+                       i-cache-line-size = <20>;       // 32 bytes
+                       d-cache-size = <4000>;          // L1, 16K
+                       i-cache-size = <4000>;          // L1, 16K
+                       timebase-frequency = <0>;
+                       bus-frequency = <0>;
+                       clock-frequency = <0>;
+                       32-bit;
+                       linux,phandle = <201>;
+                       linux,boot-cpu;
+               };
+       };
+
+       interrupt-controller@f8200000 {
+               linux,phandle = <f8200000>;
+               #address-cells = <0>;
+               #interrupt-cells = <2>;
+               interrupt-controller;
+               reg = <f8200000 f8200004>;
+               built-in;
+               device_type = "pci-pic";
+       };
+       memory {
+               device_type = "memory";
+               linux,phandle = <300>;
+               reg = <00000000 4000000 f4500000 00000020>;
+       };
+
+       soc8272@f0000000 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               #interrupt-cells = <2>;
+               device_type = "soc";
+               ranges = < 0 0 2 00000000 f0000000 00053000>;
+               reg = <f0000000 0>;
+
+               mdio@0 {
+                       device_type = "mdio";
+                       compatible = "fs_enet";
+                       reg = <0 0>;
+                       linux,phandle = <24520>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       ethernet-phy@0 {
+                               linux,phandle = <2452000>;
+                               interrupt-parent = <10c00>;
+                               interrupts = <19 1>;
+                               reg = <0>;
+                               bitbang = [ 12 12 13 02 02 01 ];
+                               device_type = "ethernet-phy";
+                       };
+                       ethernet-phy@1 {
+                               linux,phandle = <2452001>;
+                               interrupt-parent = <10c00>;
+                               interrupts = <19 1>;
+                               bitbang = [ 12 12 13 02 02 01 ];
+                               reg = <3>;
+                               device_type = "ethernet-phy";
+                       };
+               };
+
+               ethernet@24000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       device_type = "network";
+                       device-id = <2>;
+                       compatible = "fs_enet";
+                       model = "FCC";
+                       reg = <11300 20 8400 100 11380 30>;
+                       mac-address = [ 00 11 2F 99 43 54 ];
+                       interrupts = <20 2>;
+                       interrupt-parent = <10c00>;
+                       phy-handle = <2452000>;
+                       rx-clock = <13>;
+                       tx-clock = <12>;
+               };
+
+               ethernet@25000 {
+                       device_type = "network";
+                       device-id = <3>;
+                       compatible = "fs_enet";
+                       model = "FCC";
+                       reg = <11320 20 8500 100 113b0 30>;
+                       mac-address = [ 00 11 2F 99 44 54 ];
+                       interrupts = <21 2>;
+                       interrupt-parent = <10c00>;
+                       phy-handle = <2452001>;
+                       rx-clock = <17>;
+                       tx-clock = <18>;
+               };
+
+               cpm@f0000000 {
+                       linux,phandle = <f0000000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       #interrupt-cells = <2>;
+                       device_type = "cpm";
+                       model = "CPM2";
+                       ranges = <00000000 00000000 3ffff>;
+                       reg = <10d80 3280>;
+                       command-proc = <119c0>;
+                       brg-frequency = <17D7840>;
+                       cpm_clk = <BEBC200>;
+
+                       scc@11a00 {
+                               device_type = "serial";
+                               compatible = "cpm_uart";
+                               model = "SCC";
+                               device-id = <2>;
+                               reg = <11a00 20 8000 100>;
+                               current-speed = <1c200>;
+                               interrupts = <28 2>;
+                               interrupt-parent = <10c00>;
+                               clock-setup = <0 00ffffff>;
+                               rx-clock = <1>;
+                               tx-clock = <1>;
+                       };
+
+                       scc@11a60 {
+                               device_type = "serial";
+                               compatible = "cpm_uart";
+                               model = "SCC";
+                               device-id = <5>;
+                               reg = <11a60 20 8300 100>;
+                               current-speed = <1c200>;
+                               interrupts = <2b 2>;
+                               interrupt-parent = <10c00>;
+                               clock-setup = <1b ffffff00>;
+                               rx-clock = <4>;
+                               tx-clock = <4>;
+                       };
+
+               };
+               interrupt-controller@10c00 {
+                       linux,phandle = <10c00>;
+                       #address-cells = <0>;
+                       #interrupt-cells = <2>;
+                       interrupt-controller;
+                       reg = <10c00 80>;
+                       built-in;
+                       device_type = "cpm-pic";
+                      compatible = "CPM2";
+               };
+               pci@0500 {
+                       linux,phandle = <0500>;
+                       #interrupt-cells = <1>;
+                       #size-cells = <2>;
+                       #address-cells = <3>;
+                       compatible = "8272";
+                       device_type = "pci";
+                       reg = <10430 4dc>;
+                       clock-frequency = <3f940aa>;
+                       interrupt-map-mask = <f800 0 0 7>;
+                       interrupt-map = <
+
+                                       /* IDSEL 0x16 */
+                                        b000 0 0 1 f8200000 40 0
+                                        b000 0 0 2 f8200000 41 0
+                                        b000 0 0 3 f8200000 42 0
+                                        b000 0 0 4 f8200000 43 0
+
+                                       /* IDSEL 0x17 */
+                                        b800 0 0 1 f8200000 43 0
+                                        b800 0 0 2 f8200000 40 0
+                                        b800 0 0 3 f8200000 41 0
+                                        b800 0 0 4 f8200000 42 0
+
+                                       /* IDSEL 0x18 */
+                                        c000 0 0 1 f8200000 42 0
+                                        c000 0 0 2 f8200000 43 0
+                                        c000 0 0 3 f8200000 40 0
+                                        c000 0 0 4 f8200000 41 0>;
+                       interrupt-parent = <10c00>;
+                       interrupts = <14 3>;
+                       bus-range = <0 0>;
+                       ranges = <02000000 0 80000000 80000000 0 40000000
+                                 01000000 0 00000000 f6000000 0 02000000>;
+               };
+
+/* May need to remove if on a part without crypto engine */
+               crypto@30000 {
+                       device_type = "crypto";
+                       model = "SEC2";
+                       compatible = "talitos";
+                       reg = <30000 10000>;
+                       interrupts = <b 0>;
+                       interrupt-parent = <10c00>;
+                       num-channels = <4>;
+                       channel-fifo-len = <18>;
+                       exec-units-mask = <0000007e>;
+/* desc mask is for rev1.x, we need runtime fixup for >=2.x */
+                       descriptor-types-mask = <01010ebf>;
+               };
+
+       };
+};
diff --git a/arch/powerpc/boot/dts/mpc8360emds.dts b/arch/powerpc/boot/dts/mpc8360emds.dts
new file mode 100644 (file)
index 0000000..9022192
--- /dev/null
@@ -0,0 +1,375 @@
+/*
+ * MPC8360E EMDS Device Tree Source
+ *
+ * Copyright 2006 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+
+/*
+/memreserve/   00000000 1000000;
+*/
+
+/ {
+       model = "MPC8360EPB";
+       compatible = "MPC83xx";
+       #address-cells = <1>;
+       #size-cells = <1>;
+       linux,phandle = <100>;
+
+       cpus {
+               #cpus = <1>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               linux,phandle = <200>;
+
+               PowerPC,8360@0 {
+                       device_type = "cpu";
+                       reg = <0>;
+                       d-cache-line-size = <20>;       // 32 bytes
+                       i-cache-line-size = <20>;       // 32 bytes
+                       d-cache-size = <8000>;          // L1, 32K
+                       i-cache-size = <8000>;          // L1, 32K
+                       timebase-frequency = <3EF1480>;
+                       bus-frequency = <FBC5200>;
+                       clock-frequency = <1F78A400>;
+                       32-bit;
+                       linux,phandle = <201>;
+                       linux,boot-cpu;
+               };
+       };
+
+       memory {
+               device_type = "memory";
+               linux,phandle = <300>;
+               reg = <00000000 10000000>;
+       };
+
+       bcsr@f8000000 {
+               device_type = "board-control";
+               reg = <f8000000 8000>;
+       };
+
+       soc8360@e0000000 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               #interrupt-cells = <2>;
+               device_type = "soc";
+               ranges = <0 e0000000 00100000>;
+               reg = <e0000000 00000200>;
+               bus-frequency = <FBC5200>;
+
+               wdt@200 {
+                       device_type = "watchdog";
+                       compatible = "mpc83xx_wdt";
+                       reg = <200 100>;
+               };
+
+               i2c@3000 {
+                       device_type = "i2c";
+                       compatible = "fsl-i2c";
+                       reg = <3000 100>;
+                       interrupts = <e 8>;
+                       interrupt-parent = <700>;
+                       dfsrr;
+               };
+
+               i2c@3100 {
+                       device_type = "i2c";
+                       compatible = "fsl-i2c";
+                       reg = <3100 100>;
+                       interrupts = <f 8>;
+                       interrupt-parent = <700>;
+                       dfsrr;
+               };
+
+               serial@4500 {
+                       device_type = "serial";
+                       compatible = "ns16550";
+                       reg = <4500 100>;
+                       clock-frequency = <FBC5200>;
+                       interrupts = <9 8>;
+                       interrupt-parent = <700>;
+               };
+
+               serial@4600 {
+                       device_type = "serial";
+                       compatible = "ns16550";
+                       reg = <4600 100>;
+                       clock-frequency = <FBC5200>;
+                       interrupts = <a 8>;
+                       interrupt-parent = <700>;
+               };
+
+               crypto@30000 {
+                       device_type = "crypto";
+                       model = "SEC2";
+                       compatible = "talitos";
+                       reg = <30000 10000>;
+                       interrupts = <b 8>;
+                       interrupt-parent = <700>;
+                       num-channels = <4>;
+                       channel-fifo-len = <18>;
+                       exec-units-mask = <0000007e>;
+                       /* desc mask is for rev1.x, we need runtime fixup for >=2.x */
+                       descriptor-types-mask = <01010ebf>;
+               };
+
+               pci@8500 {
+                       linux,phandle = <8500>;
+                       interrupt-map-mask = <f800 0 0 7>;
+                       interrupt-map = <
+
+                                       /* IDSEL 0x11 AD17 */
+                                        8800 0 0 1 700 14 8
+                                        8800 0 0 2 700 15 8
+                                        8800 0 0 3 700 16 8
+                                        8800 0 0 4 700 17 8
+
+                                       /* IDSEL 0x12 AD18 */
+                                        9000 0 0 1 700 16 8
+                                        9000 0 0 2 700 17 8
+                                        9000 0 0 3 700 14 8
+                                        9000 0 0 4 700 15 8
+
+                                       /* IDSEL 0x13 AD19 */
+                                        9800 0 0 1 700 17 8
+                                        9800 0 0 2 700 14 8
+                                        9800 0 0 3 700 15 8
+                                        9800 0 0 4 700 16 8
+
+                                       /* IDSEL 0x15 AD21*/
+                                        a800 0 0 1 700 14 8
+                                        a800 0 0 2 700 15 8
+                                        a800 0 0 3 700 16 8
+                                        a800 0 0 4 700 17 8
+
+                                       /* IDSEL 0x16 AD22*/
+                                        b000 0 0 1 700 17 8
+                                        b000 0 0 2 700 14 8
+                                        b000 0 0 3 700 15 8
+                                        b000 0 0 4 700 16 8
+
+                                       /* IDSEL 0x17 AD23*/
+                                        b800 0 0 1 700 16 8
+                                        b800 0 0 2 700 17 8
+                                        b800 0 0 3 700 14 8
+                                        b800 0 0 4 700 15 8
+
+                                       /* IDSEL 0x18 AD24*/
+                                        c000 0 0 1 700 15 8
+                                        c000 0 0 2 700 16 8
+                                        c000 0 0 3 700 17 8
+                                        c000 0 0 4 700 14 8>;
+                       interrupt-parent = <700>;
+                       interrupts = <42 8>;
+                       bus-range = <0 0>;
+                       ranges = <02000000 0 a0000000 a0000000 0 10000000
+                                 42000000 0 80000000 80000000 0 10000000
+                                 01000000 0 00000000 e2000000 0 00100000>;
+                       clock-frequency = <3f940aa>;
+                       #interrupt-cells = <1>;
+                       #size-cells = <2>;
+                       #address-cells = <3>;
+                       reg = <8500 100>;
+                       compatible = "83xx";
+                       device_type = "pci";
+               };
+
+               pic@700 {
+                       linux,phandle = <700>;
+                       interrupt-controller;
+                       #address-cells = <0>;
+                       #interrupt-cells = <2>;
+                       reg = <700 100>;
+                       built-in;
+                       device_type = "ipic";
+               };
+
+               par_io@1400 {
+                       reg = <1400 100>;
+                       device_type = "par_io";
+                       num-ports = <7>;
+
+                       ucc_pin@01 {
+                               linux,phandle = <140001>;
+                               pio-map = <
+                       /* port  pin  dir  open_drain  assignment  has_irq */
+                                       0  3  1  0  1  0        /* TxD0 */
+                                       0  4  1  0  1  0        /* TxD1 */
+                                       0  5  1  0  1  0        /* TxD2 */
+                                       0  6  1  0  1  0        /* TxD3 */
+                                       1  6  1  0  3  0        /* TxD4 */
+                                       1  7  1  0  1  0        /* TxD5 */
+                                       1  9  1  0  2  0        /* TxD6 */
+                                       1  a  1  0  2  0        /* TxD7 */
+                                       0  9  2  0  1  0        /* RxD0 */
+                                       0  a  2  0  1  0        /* RxD1 */
+                                       0  b  2  0  1  0        /* RxD2 */
+                                       0  c  2  0  1  0        /* RxD3 */
+                                       0  d  2  0  1  0        /* RxD4 */
+                                       1  1  2  0  2  0        /* RxD5 */
+                                       1  0  2  0  2  0        /* RxD6 */
+                                       1  4  2  0  2  0        /* RxD7 */
+                                       0  7  1  0  1  0        /* TX_EN */
+                                       0  8  1  0  1  0        /* TX_ER */
+                                       0  f  2  0  1  0        /* RX_DV */
+                                       0  10 2  0  1  0        /* RX_ER */
+                                       0  0  2  0  1  0        /* RX_CLK */
+                                       2  9  1  0  3  0        /* GTX_CLK - CLK10 */
+                                       2  8  2  0  1  0>;      /* GTX125 - CLK9 */
+                       };
+                       ucc_pin@02 {
+                               linux,phandle = <140002>;
+                               pio-map = <
+                       /* port  pin  dir  open_drain  assignment  has_irq */
+                                       0  11 1  0  1  0   /* TxD0 */
+                                       0  12 1  0  1  0   /* TxD1 */
+                                       0  13 1  0  1  0   /* TxD2 */
+                                       0  14 1  0  1  0   /* TxD3 */
+                                       1  2  1  0  1  0   /* TxD4 */
+                                       1  3  1  0  2  0   /* TxD5 */
+                                       1  5  1  0  3  0   /* TxD6 */
+                                       1  8  1  0  3  0   /* TxD7 */
+                                       0  17 2  0  1  0   /* RxD0 */
+                                       0  18 2  0  1  0   /* RxD1 */
+                                       0  19 2  0  1  0   /* RxD2 */
+                                       0  1a 2  0  1  0   /* RxD3 */
+                                       0  1b 2  0  1  0   /* RxD4 */
+                                       1  c  2  0  2  0   /* RxD5 */
+                                       1  d  2  0  3  0   /* RxD6 */
+                                       1  b  2  0  2  0   /* RxD7 */
+                                       0  15 1  0  1  0   /* TX_EN */
+                                       0  16 1  0  1  0   /* TX_ER */
+                                       0  1d 2  0  1  0   /* RX_DV */
+                                       0  1e 2  0  1  0   /* RX_ER */
+                                       0  1f 2  0  1  0   /* RX_CLK */
+                                       2  2  1  0  2  0   /* GTX_CLK - CLK10 */
+                                       2  3  2  0  1  0   /* GTX125 - CLK4 */
+                                       0  1  3  0  2  0   /* MDIO */
+                                       0  2  1  0  1  0>; /* MDC */
+                       };
+
+               };
+       };
+
+       qe@e0100000 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               device_type = "qe";
+               model = "QE";
+               ranges = <0 e0100000 00100000>;
+               reg = <e0100000 480>;
+               brg-frequency = <0>;
+               bus-frequency = <179A7B00>;
+
+               muram@10000 {
+                       device_type = "muram";
+                       ranges = <0 00010000 0000c000>;
+
+                       data-only@0{
+                               reg = <0 c000>;
+                       };
+               };
+
+               spi@4c0 {
+                       device_type = "spi";
+                       compatible = "fsl_spi";
+                       reg = <4c0 40>;
+                       interrupts = <2>;
+                       interrupt-parent = <80>;
+                       mode = "cpu";
+               };
+
+               spi@500 {
+                       device_type = "spi";
+                       compatible = "fsl_spi";
+                       reg = <500 40>;
+                       interrupts = <1>;
+                       interrupt-parent = <80>;
+                       mode = "cpu";
+               };
+
+               usb@6c0 {
+                       device_type = "usb";
+                       compatible = "qe_udc";
+                       reg = <6c0 40 8B00 100>;
+                       interrupts = <b>;
+                       interrupt-parent = <80>;
+                       mode = "slave";
+               };
+
+               ucc@2000 {
+                       device_type = "network";
+                       compatible = "ucc_geth";
+                       model = "UCC";
+                       device-id = <1>;
+                       reg = <2000 200>;
+                       interrupts = <20>;
+                       interrupt-parent = <80>;
+                       mac-address = [ 00 04 9f 00 23 23 ];
+                       rx-clock = <0>;
+                       tx-clock = <19>;
+                       phy-handle = <212000>;
+                       pio-handle = <140001>;
+               };
+
+               ucc@3000 {
+                       device_type = "network";
+                       compatible = "ucc_geth";
+                       model = "UCC";
+                       device-id = <2>;
+                       reg = <3000 200>;
+                       interrupts = <21>;
+                       interrupt-parent = <80>;
+                       mac-address = [ 00 11 22 33 44 55 ];
+                       rx-clock = <0>;
+                       tx-clock = <14>;
+                       phy-handle = <212001>;
+                       pio-handle = <140002>;
+               };
+
+               mdio@2120 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <2120 18>;
+                       device_type = "mdio";
+                       compatible = "ucc_geth_phy";
+
+                       ethernet-phy@00 {
+                               linux,phandle = <212000>;
+                               interrupt-parent = <700>;
+                               interrupts = <11 2>;
+                               reg = <0>;
+                               device_type = "ethernet-phy";
+                               interface = <6>; //ENET_1000_GMII
+                       };
+                       ethernet-phy@01 {
+                               linux,phandle = <212001>;
+                               interrupt-parent = <700>;
+                               interrupts = <12 2>;
+                               reg = <1>;
+                               device_type = "ethernet-phy";
+                               interface = <6>;
+                       };
+               };
+
+               qeic@80 {
+                       linux,phandle = <80>;
+                       interrupt-controller;
+                       device_type = "qeic";
+                       #address-cells = <0>;
+                       #interrupt-cells = <1>;
+                       reg = <80 80>;
+                       built-in;
+                       big-endian;
+                       interrupts = <20 8 21 8>; //high:32 low:33
+                       interrupt-parent = <700>;
+               };
+
+       };
+};
index 6016251..05f3238 100644 (file)
@@ -15,6 +15,7 @@ SECTIONS
   {
     *(.rodata*)
     *(.data*)
+    *(__builtin_*)
     *(.sdata*)
     __got2_start = .;
     *(.got2)
diff --git a/arch/powerpc/configs/mpc8360emds_defconfig b/arch/powerpc/configs/mpc8360emds_defconfig
new file mode 100644 (file)
index 0000000..c070341
--- /dev/null
@@ -0,0 +1,1018 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.18
+# Thu Sep 21 18:14:27 2006
+#
+# CONFIG_PPC64 is not set
+CONFIG_PPC32=y
+CONFIG_PPC_MERGE=y
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_IRQ_PER_CPU=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_PPC_UDBG_16550=y
+# CONFIG_GENERIC_TBSYNC is not set
+CONFIG_AUDIT_ARCH=y
+CONFIG_DEFAULT_UIMAGE=y
+
+#
+# Processor support
+#
+# CONFIG_CLASSIC32 is not set
+# CONFIG_PPC_52xx is not set
+# CONFIG_PPC_82xx is not set
+CONFIG_PPC_83xx=y
+# CONFIG_PPC_85xx is not set
+# CONFIG_PPC_86xx is not set
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_8xx is not set
+# CONFIG_E200 is not set
+CONFIG_6xx=y
+CONFIG_83xx=y
+CONFIG_PPC_FPU=y
+CONFIG_PPC_STD_MMU=y
+CONFIG_PPC_STD_MMU_32=y
+# CONFIG_SMP is not set
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+# CONFIG_RELAY is not set
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL=y
+# CONFIG_KALLSYMS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+# CONFIG_EPOLL is not set
+CONFIG_SHMEM=y
+CONFIG_SLAB=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_SLOB is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+
+#
+# Block layer
+#
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_QUICC_ENGINE=y
+CONFIG_PPC_GEN550=y
+# CONFIG_WANT_EARLY_SERIAL is not set
+
+#
+# Platform support
+#
+# CONFIG_MPC834x_SYS is not set
+# CONFIG_MPC834x_ITX is not set
+CONFIG_MPC8360E_PB=y
+CONFIG_PPC_MPC836x=y
+# CONFIG_MPIC is not set
+
+#
+# Kernel options
+#
+# CONFIG_HIGHMEM is not set
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_CMDLINE_BOOL is not set
+# CONFIG_PM is not set
+CONFIG_SECCOMP=y
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_GENERIC_ISA_DMA=y
+# CONFIG_MPIC_WEIRD is not set
+# CONFIG_PPC_I8259 is not set
+CONFIG_PPC_INDIRECT_PCI=y
+CONFIG_FSL_SOC=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_PCIEPORTBUS is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# PCI Hotplug Support
+#
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_HIGHMEM_START=0xfe000000
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_TASK_SIZE=0x80000000
+CONFIG_BOOT_LOAD=0x00800000
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_NETDEBUG is not set
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_BIC=y
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+
+#
+# DCCP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_DCCP is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+
+#
+# TIPC Configuration (EXPERIMENTAL)
+#
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_IEEE80211 is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_SYS_HYPERVISOR is not set
+
+#
+# Connector - unified userspace <-> kernelspace linker
+#
+# CONFIG_CONNECTOR is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=32768
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+# CONFIG_BLK_DEV_SD is not set
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI Transport Attributes
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_SATA is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+# CONFIG_FUSION_SPI is not set
+# CONFIG_FUSION_FC is not set
+# CONFIG_FUSION_SAS is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# Macintosh device drivers
+#
+# CONFIG_WINDFARM is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# PHY device support
+#
+# CONFIG_PHYLIB is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+
+#
+# Tulip family network device support
+#
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_PCI is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_GIANFAR is not set
+CONFIG_UCC_GETH=y
+# CONFIG_UGETH_NAPI is not set
+# CONFIG_UGETH_MAGIC_PACKET is not set
+# CONFIG_UGETH_FILTERING is not set
+# CONFIG_UGETH_TX_ON_DEMOND is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_CHELSIO_T1 is not set
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+# CONFIG_MYRI10GE is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_83xx_WDT=y
+
+#
+# PCI-based Watchdog Cards
+#
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+CONFIG_GEN_RTC=y
+# CONFIG_GEN_RTC_X is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+# CONFIG_TELCLOCK is not set
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_PIIX4 is not set
+CONFIG_I2C_MPC=y
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+# CONFIG_I2C_PCA_ISA is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_M41T00 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+
+#
+# Dallas's 1-wire bus
+#
+
+#
+# Hardware Monitoring support
+#
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_ABITUGURU is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_FSCPOS is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+CONFIG_VIDEO_V4L2=y
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+CONFIG_FIRMWARE_EDID=y
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+# CONFIG_USB is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# LED devices
+#
+# CONFIG_NEW_LEDS is not set
+
+#
+# LED drivers
+#
+
+#
+# LED Triggers
+#
+
+#
+# InfiniBand support
+#
+# CONFIG_INFINIBAND is not set
+
+#
+# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
+#
+
+#
+# Real Time Clock
+#
+# CONFIG_RTC_CLASS is not set
+
+#
+# DMA Engine support
+#
+# CONFIG_DMA_ENGINE is not set
+
+#
+# DMA Clients
+#
+
+#
+# DMA Devices
+#
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_9P_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+# CONFIG_MSDOS_PARTITION is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# QE Options
+#
+# CONFIG_UCC_SLOW is not set
+CONFIG_UCC_FAST=y
+CONFIG_UCC=y
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_PLIST=y
+
+#
+# Instrumentation Support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_DEBUG_FS is not set
+# CONFIG_BOOTX_TEXT is not set
+# CONFIG_SERIAL_TEXT_DEBUG is not set
+# CONFIG_PPC_EARLY_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+CONFIG_CRYPTO=y
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Hardware crypto devices
+#
index 190a57e..47a613c 100644 (file)
@@ -763,10 +763,10 @@ struct cpu_spec   cpu_specs[] = {
                .cpu_setup              = __setup_cpu_603,
                .platform               = "ppc603",
        },
-       {       /* e300 (a 603e core, plus some) on 83xx */
+       {       /* e300c1 (a 603e core, plus some) on 83xx */
                .pvr_mask               = 0x7fff0000,
                .pvr_value              = 0x00830000,
-               .cpu_name               = "e300",
+               .cpu_name               = "e300c1",
                .cpu_features           = CPU_FTRS_E300,
                .cpu_user_features      = COMMON_USER,
                .icache_bsize           = 32,
@@ -774,6 +774,17 @@ struct cpu_spec    cpu_specs[] = {
                .cpu_setup              = __setup_cpu_603,
                .platform               = "ppc603",
        },
+       {       /* e300c2 (an e300c1 core, plus some, minus FPU) on 83xx */
+               .pvr_mask               = 0x7fff0000,
+               .pvr_value              = 0x00840000,
+               .cpu_name               = "e300c2",
+               .cpu_features           = CPU_FTRS_E300,
+               .cpu_user_features      = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
+               .icache_bsize           = 32,
+               .dcache_bsize           = 32,
+               .cpu_setup              = __setup_cpu_603,
+               .platform               = "ppc603",
+       },
        {       /* default match, we assume split I/D cache & TB (non-601)... */
                .pvr_mask               = 0x00000000,
                .pvr_value              = 0x00000000,
index 2cd872b..748e74f 100644 (file)
 #include <asm/ppc_asm.h>
 #include <asm/asm-offsets.h>
 #include <asm/cputable.h>
-
-#ifdef CONFIG_PPC_ISERIES
-#define DO_SOFT_DISABLE
-#endif
+#include <asm/firmware.h>
 
 /*
  * System calls.
@@ -91,6 +88,7 @@ system_call_common:
        ld      r11,exception_marker@toc(r2)
        std     r11,-16(r9)             /* "regshere" marker */
 #ifdef CONFIG_PPC_ISERIES
+BEGIN_FW_FTR_SECTION
        /* Hack for handling interrupts when soft-enabling on iSeries */
        cmpdi   cr1,r0,0x5555           /* syscall 0x5555 */
        andi.   r10,r12,MSR_PR          /* from kernel */
@@ -98,6 +96,7 @@ system_call_common:
        beq     hardware_interrupt_entry
        lbz     r10,PACAPROCENABLED(r13)
        std     r10,SOFTE(r1)
+END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
 #endif
        mfmsr   r11
        ori     r11,r11,MSR_EE
@@ -462,6 +461,7 @@ _GLOBAL(ret_from_except_lite)
 
 restore:
 #ifdef CONFIG_PPC_ISERIES
+BEGIN_FW_FTR_SECTION
        ld      r5,SOFTE(r1)
        cmpdi   0,r5,0
        beq     4f
@@ -480,6 +480,7 @@ restore:
        b       .ret_from_except_lite           /* loop back and handle more */
 
 4:     stb     r5,PACAPROCENABLED(r13)
+END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
 #endif
 
        ld      r3,_MSR(r1)
@@ -538,18 +539,23 @@ do_work:
        lwz     r8,TI_PREEMPT(r9)
        cmpwi   cr1,r8,0
 #ifdef CONFIG_PPC_ISERIES
+BEGIN_FW_FTR_SECTION
        ld      r0,SOFTE(r1)
        cmpdi   r0,0
-#else
-       andi.   r0,r3,MSR_EE
+END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
 #endif
+BEGIN_FW_FTR_SECTION
+       andi.   r0,r3,MSR_EE
+END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
        crandc  eq,cr1*4+eq,eq
        bne     restore
        /* here we are preempting the current task */
 1:
 #ifdef CONFIG_PPC_ISERIES
+BEGIN_FW_FTR_SECTION
        li      r0,1
        stb     r0,PACAPROCENABLED(r13)
+END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
 #endif
        ori     r10,r10,MSR_EE
        mtmsrd  r10,1           /* reenable interrupts */
index 3065b47..645c7f1 100644 (file)
@@ -33,6 +33,7 @@
 #include <asm/hvcall.h>
 #include <asm/iseries/lpar_map.h>
 #include <asm/thread_info.h>
+#include <asm/firmware.h>
 
 #ifdef CONFIG_PPC_ISERIES
 #define DO_SOFT_DISABLE
@@ -365,19 +366,28 @@ label##_iSeries:                                                  \
 
 #ifdef DO_SOFT_DISABLE
 #define DISABLE_INTS                           \
+BEGIN_FW_FTR_SECTION;                          \
        lbz     r10,PACAPROCENABLED(r13);       \
        li      r11,0;                          \
        std     r10,SOFTE(r1);                  \
        mfmsr   r10;                            \
        stb     r11,PACAPROCENABLED(r13);       \
        ori     r10,r10,MSR_EE;                 \
-       mtmsrd  r10,1
+       mtmsrd  r10,1;                          \
+END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
 
 #define ENABLE_INTS                            \
+BEGIN_FW_FTR_SECTION;                          \
        lbz     r10,PACAPROCENABLED(r13);       \
        mfmsr   r11;                            \
        std     r10,SOFTE(r1);                  \
        ori     r11,r11,MSR_EE;                 \
+END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES);  \
+BEGIN_FW_FTR_SECTION;                          \
+       ld      r12,_MSR(r1);                   \
+       mfmsr   r11;                            \
+       rlwimi  r11,r12,0,MSR_EE;               \
+END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES);  \
        mtmsrd  r11,1
 
 #else  /* hard enable/disable interrupts */
@@ -1071,8 +1081,10 @@ _GLOBAL(slb_miss_realmode)
        ld      r3,PACA_EXSLB+EX_R3(r13)
        lwz     r9,PACA_EXSLB+EX_CCR(r13)       /* get saved CR */
 #ifdef CONFIG_PPC_ISERIES
+BEGIN_FW_FTR_SECTION
        ld      r11,PACALPPACAPTR(r13)
        ld      r11,LPPACASRR0(r11)             /* get SRR0 value */
+END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
 #endif /* CONFIG_PPC_ISERIES */
 
        mtlr    r10
@@ -1087,8 +1099,10 @@ _GLOBAL(slb_miss_realmode)
 .machine       pop
 
 #ifdef CONFIG_PPC_ISERIES
+BEGIN_FW_FTR_SECTION
        mtspr   SPRN_SRR0,r11
        mtspr   SPRN_SRR1,r12
+END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
 #endif /* CONFIG_PPC_ISERIES */
        ld      r9,PACA_EXSLB+EX_R9(r13)
        ld      r10,PACA_EXSLB+EX_R10(r13)
@@ -1301,6 +1315,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
        cmpdi   r3,0                    /* see if hash_page succeeded */
 
 #ifdef DO_SOFT_DISABLE
+BEGIN_FW_FTR_SECTION
        /*
         * If we had interrupts soft-enabled at the point where the
         * DSI/ISI occurred, and an interrupt came in during hash_page,
@@ -1321,12 +1336,14 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
        ld      r3,SOFTE(r1)
        bl      .local_irq_restore
        b       11f
-#else
+END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
+#endif
+BEGIN_FW_FTR_SECTION
        beq     fast_exception_return   /* Return from exception on success */
        ble-    12f                     /* Failure return from hash_page */
 
        /* fall through */
-#endif
+END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
 
 /* Here we have a page fault that hash_page can't handle. */
 _GLOBAL(handle_page_fault)
@@ -1861,7 +1878,9 @@ _GLOBAL(__secondary_start)
        LOAD_REG_ADDR(r3, .start_secondary_prolog)
        LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
 #ifdef DO_SOFT_DISABLE
+BEGIN_FW_FTR_SECTION
        ori     r4,r4,MSR_EE
+END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
 #endif
        mtspr   SPRN_SRR0,r3
        mtspr   SPRN_SRR1,r4
@@ -1986,6 +2005,7 @@ _STATIC(start_here_common)
         */
        li      r3,0
        bl      .do_cpu_ftr_fixups
+       bl      .do_fw_ftr_fixups
 
        /* ptr to current */
        LOAD_REG_IMMEDIATE(r4, init_task)
@@ -2000,11 +2020,13 @@ _STATIC(start_here_common)
        /* Load up the kernel context */
 5:
 #ifdef DO_SOFT_DISABLE
+BEGIN_FW_FTR_SECTION
        li      r5,0
        stb     r5,PACAPROCENABLED(r13) /* Soft Disabled */
        mfmsr   r5
        ori     r5,r5,MSR_EE            /* Hard Enabled */
        mtmsrd  r5
+END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
 #endif
 
        bl .start_kernel
index 9c54ecc..41521b3 100644 (file)
@@ -325,6 +325,52 @@ _GLOBAL(do_cpu_ftr_fixups)
        isync
        b       1b
 
+/*
+ * do_fw_ftr_fixups - goes through the list of firmware feature fixups
+ * and writes nop's over sections of code that don't apply for this firmware.
+ * r3 = data offset (not changed)
+ */
+_GLOBAL(do_fw_ftr_fixups)
+       /* Get firmware features */
+       LOAD_REG_IMMEDIATE(r6,powerpc_firmware_features)
+       sub     r6,r6,r3
+       ld      r4,0(r6)
+       /* Get the fixup table */
+       LOAD_REG_IMMEDIATE(r6,__start___fw_ftr_fixup)
+       sub     r6,r6,r3
+       LOAD_REG_IMMEDIATE(r7,__stop___fw_ftr_fixup)
+       sub     r7,r7,r3
+       /* Do the fixup */
+1:     cmpld   r6,r7
+       bgelr
+       addi    r6,r6,32
+       ld      r8,-32(r6)      /* mask */
+       and     r8,r8,r4
+       ld      r9,-24(r6)      /* value */
+       cmpld   r8,r9
+       beq     1b
+       ld      r8,-16(r6)      /* section begin */
+       ld      r9,-8(r6)       /* section end */
+       subf.   r9,r8,r9
+       beq     1b
+       /* write nops over the section of code */
+       /* todo: if large section, add a branch at the start of it */
+       srwi    r9,r9,2
+       mtctr   r9
+       sub     r8,r8,r3
+       lis     r0,0x60000000@h /* nop */
+3:     stw     r0,0(r8)
+BEGIN_FTR_SECTION
+       dcbst   0,r8            /* suboptimal, but simpler */
+       sync
+       icbi    0,r8
+END_FTR_SECTION_IFSET(CPU_FTR_SPLIT_ID_CACHE)
+       addi    r8,r8,4
+       bdnz    3b
+       sync                    /* additional sync needed on g4 */
+       isync
+       b       1b
+
 #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE)
 /*
  * Do an IO access in real mode
index c1b1e14..78d3c0f 100644 (file)
@@ -30,6 +30,7 @@
 #include <asm/byteorder.h>
 #include <asm/machdep.h>
 #include <asm/ppc-pci.h>
+#include <asm/firmware.h>
 
 #ifdef DEBUG
 #include <asm/udbg.h>
@@ -209,7 +210,6 @@ void pcibios_free_controller(struct pci_controller *phb)
                kfree(phb);
 }
 
-#ifndef CONFIG_PPC_ISERIES
 void __devinit pcibios_claim_one_bus(struct pci_bus *b)
 {
        struct pci_dev *dev;
@@ -238,10 +238,12 @@ static void __init pcibios_claim_of_setup(void)
 {
        struct pci_bus *b;
 
+       if (firmware_has_feature(FW_FEATURE_ISERIES))
+               return;
+
        list_for_each_entry(b, &pci_root_buses, node)
                pcibios_claim_one_bus(b);
 }
-#endif
 
 #ifdef CONFIG_PPC_MULTIPLATFORM
 static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
@@ -554,9 +556,8 @@ static int __init pcibios_init(void)
         */
        ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
 
-#ifdef CONFIG_PPC_ISERIES
-       iSeries_pcibios_init(); 
-#endif
+       if (firmware_has_feature(FW_FEATURE_ISERIES))
+               iSeries_pcibios_init();
 
        printk(KERN_DEBUG "PCI: Probing PCI hardware\n");
 
@@ -566,15 +567,15 @@ static int __init pcibios_init(void)
                pci_bus_add_devices(hose->bus);
        }
 
-#ifndef CONFIG_PPC_ISERIES
-       if (pci_probe_only)
-               pcibios_claim_of_setup();
-       else
-               /* FIXME: `else' will be removed when
-                  pci_assign_unassigned_resources() is able to work
-                  correctly with [partially] allocated PCI tree. */
-               pci_assign_unassigned_resources();
-#endif /* !CONFIG_PPC_ISERIES */
+       if (!firmware_has_feature(FW_FEATURE_ISERIES)) {
+               if (pci_probe_only)
+                       pcibios_claim_of_setup();
+               else
+                       /* FIXME: `else' will be removed when
+                          pci_assign_unassigned_resources() is able to work
+                          correctly with [partially] allocated PCI tree. */
+                       pci_assign_unassigned_resources();
+       }
 
        /* Call machine dependent final fixup */
        if (ppc_md.pcibios_fixup)
@@ -586,8 +587,9 @@ static int __init pcibios_init(void)
                printk(KERN_DEBUG "ISA bridge at %s\n", pci_name(ppc64_isabridge_dev));
 
 #ifdef CONFIG_PPC_MULTIPLATFORM
-       /* map in PCI I/O space */
-       phbs_remap_io();
+       if (!firmware_has_feature(FW_FEATURE_ISERIES))
+               /* map in PCI I/O space */
+               phbs_remap_io();
 #endif
 
        printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");
@@ -637,13 +639,13 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
  */
 int pci_domain_nr(struct pci_bus *bus)
 {
-#ifdef CONFIG_PPC_ISERIES
-       return 0;
-#else
-       struct pci_controller *hose = pci_bus_to_host(bus);
+       if (firmware_has_feature(FW_FEATURE_ISERIES))
+               return 0;
+       else {
+               struct pci_controller *hose = pci_bus_to_host(bus);
 
-       return hose->global_number;
-#endif
+               return hose->global_number;
+       }
 }
 
 EXPORT_SYMBOL(pci_domain_nr);
@@ -651,12 +653,12 @@ EXPORT_SYMBOL(pci_domain_nr);
 /* Decide whether to display the domain number in /proc */
 int pci_proc_domain(struct pci_bus *bus)
 {
-#ifdef CONFIG_PPC_ISERIES
-       return 0;
-#else
-       struct pci_controller *hose = pci_bus_to_host(bus);
-       return hose->buid;
-#endif
+       if (firmware_has_feature(FW_FEATURE_ISERIES))
+               return 0;
+       else {
+               struct pci_controller *hose = pci_bus_to_host(bus);
+               return hose->buid;
+       }
 }
 
 /*
index 0af3fc1..89cfaf4 100644 (file)
@@ -442,31 +442,6 @@ void __init smp_setup_cpu_maps(void)
 }
 #endif /* CONFIG_SMP */
 
-int __initdata do_early_xmon;
-#ifdef CONFIG_XMON
-extern int xmon_no_auto_backtrace;
-
-static int __init early_xmon(char *p)
-{
-       /* ensure xmon is enabled */
-       if (p) {
-               if (strncmp(p, "on", 2) == 0)
-                       xmon_init(1);
-               if (strncmp(p, "off", 3) == 0)
-                       xmon_init(0);
-               if (strncmp(p, "nobt", 4) == 0)
-                       xmon_no_auto_backtrace = 1;
-               if (strncmp(p, "early", 5) != 0)
-                       return 0;
-       }
-       xmon_init(1);
-       do_early_xmon = 1;
-
-       return 0;
-}
-early_param("xmon", early_xmon);
-#endif
-
 static __init int add_pcspkr(void)
 {
        struct device_node *np;
index 79a1779..191d0ab 100644 (file)
@@ -238,12 +238,11 @@ void __init setup_arch(char **cmdline_p)
 
        smp_setup_cpu_maps();
 
-#ifdef CONFIG_XMON_DEFAULT
-       xmon_init(1);
-#endif
        /* Register early console */
        register_early_udbg_console();
 
+       xmon_setup();
+
 #if defined(CONFIG_KGDB)
        if (ppc_md.kgdb_map_scc)
                ppc_md.kgdb_map_scc();
@@ -280,9 +279,6 @@ void __init setup_arch(char **cmdline_p)
        init_mm.end_data = (unsigned long) _edata;
        init_mm.brk = klimit;
 
-       if (do_early_xmon)
-               debugger(NULL);
-
        /* set up the bootmem stuff with available memory */
        do_init_bootmem();
        if ( ppc_md.progress ) ppc_md.progress("setup_arch: bootmem", 0x3eab);
index cda2dbe..4b2e32e 100644 (file)
@@ -390,19 +390,15 @@ void __init setup_system(void)
         */
        find_legacy_serial_ports();
 
-       /*
-        * Initialize xmon
-        */
-#ifdef CONFIG_XMON_DEFAULT
-       xmon_init(1);
-#endif
        /*
         * Register early console
         */
        register_early_udbg_console();
 
-       if (do_early_xmon)
-               debugger(NULL);
+       /*
+        * Initialize xmon
+        */
+       xmon_setup();
 
        check_smt_enabled();
        smp_setup_cpu_maps();
index 02665a0..cb0e8d4 100644 (file)
@@ -132,6 +132,14 @@ SECTIONS
                *(__ftr_fixup)
                __stop___ftr_fixup = .;
        }
+#ifdef CONFIG_PPC64
+       . = ALIGN(8);
+       __fw_ftr_fixup : {
+               __start___fw_ftr_fixup = .;
+               *(__fw_ftr_fixup)
+               __stop___fw_ftr_fixup = .;
+       }
+#endif
 
        . = ALIGN(PAGE_SIZE);
        .init.ramfs : {
index b1da031..ac64f4a 100644 (file)
 #include <asm/iommu.h>
 #include <asm/abs_addr.h>
 #include <asm/vdso.h>
+#include <asm/firmware.h>
 
 #include "mmu_decl.h"
 
 unsigned long ioremap_bot = IMALLOC_BASE;
 static unsigned long phbs_io_bot = PHBS_IO_BASE;
 
-#ifdef CONFIG_PPC_ISERIES
-
-void __iomem *ioremap(unsigned long addr, unsigned long size)
-{
-       return (void __iomem *)addr;
-}
-
-extern void __iomem *__ioremap(unsigned long addr, unsigned long size,
-                      unsigned long flags)
-{
-       return (void __iomem *)addr;
-}
-
-void iounmap(volatile void __iomem *addr)
-{
-       return;
-}
-
-#else
-
 /*
  * map_io_page currently only called by __ioremap
  * map_io_page adds an entry to the ioremap page table
@@ -161,6 +142,9 @@ void __iomem * __ioremap(unsigned long addr, unsigned long size,
        unsigned long pa, ea;
        void __iomem *ret;
 
+       if (firmware_has_feature(FW_FEATURE_ISERIES))
+               return (void __iomem *)addr;
+
        /*
         * Choose an address to map it to.
         * Once the imalloc system is running, we use it.
@@ -255,6 +239,9 @@ void iounmap(volatile void __iomem *token)
 {
        void *addr;
 
+       if (firmware_has_feature(FW_FEATURE_ISERIES))
+               return;
+
        if (!mem_init_done)
                return;
        
@@ -315,8 +302,6 @@ int iounmap_explicit(volatile void __iomem *start, unsigned long size)
        return 0;
 }
 
-#endif
-
 EXPORT_SYMBOL(ioremap);
 EXPORT_SYMBOL(__ioremap);
 EXPORT_SYMBOL(iounmap);
index dbc1abb..b10e470 100644 (file)
@@ -21,6 +21,7 @@
 #include <asm/page.h>
 #include <asm/mmu.h>
 #include <asm/pgtable.h>
+#include <asm/firmware.h>
 
 /* void slb_allocate_realmode(unsigned long ea);
  *
@@ -183,6 +184,7 @@ slb_finish_load:
         * dont have any LRU information to help us choose a slot.
         */
 #ifdef CONFIG_PPC_ISERIES
+BEGIN_FW_FTR_SECTION
        /*
         * On iSeries, the "bolted" stack segment can be cast out on
         * shared processor switch so we need to check for a miss on
@@ -194,6 +196,7 @@ slb_finish_load:
        li      r10,SLB_NUM_BOLTED-1    /* Stack goes in last bolted slot */
        cmpld   r9,r3
        beq     3f
+END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
 #endif /* CONFIG_PPC_ISERIES */
 
        ld      r10,PACASTABRR(r13)
diff --git a/arch/powerpc/platforms/82xx/Kconfig b/arch/powerpc/platforms/82xx/Kconfig
new file mode 100644 (file)
index 0000000..47d841e
--- /dev/null
@@ -0,0 +1,21 @@
+menu "Platform support"
+       depends on PPC_82xx
+
+choice
+       prompt "Machine Type"
+       default MPC82xx_ADS
+
+config MPC82xx_ADS
+       bool "Freescale MPC82xx ADS"
+       select DEFAULT_UIMAGE
+       select PQ2ADS
+       select 8272
+       select 8260
+       select CPM2
+       select FSL_SOC
+       help
+         This option enables support for the MPC8272 ADS board
+
+endchoice
+
+endmenu
diff --git a/arch/powerpc/platforms/82xx/Makefile b/arch/powerpc/platforms/82xx/Makefile
new file mode 100644 (file)
index 0000000..d9fd4c8
--- /dev/null
@@ -0,0 +1,5 @@
+#
+# Makefile for the PowerPC 82xx linux kernel.
+#
+obj-$(CONFIG_PPC_82xx) += mpc82xx.o
+obj-$(CONFIG_MPC82xx_ADS) += mpc82xx_ads.o
diff --git a/arch/powerpc/platforms/82xx/m82xx_pci.h b/arch/powerpc/platforms/82xx/m82xx_pci.h
new file mode 100644 (file)
index 0000000..9cd8893
--- /dev/null
@@ -0,0 +1,19 @@
+#ifndef _PPC_KERNEL_M82XX_PCI_H
+#define _PPC_KERNEL_M82XX_PCI_H
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <asm/m8260_pci.h>
+
+#define SIU_INT_IRQ1   ((uint)0x13 + CPM_IRQ_OFFSET)
+
+#ifndef _IO_BASE
+#define _IO_BASE isa_io_base
+#endif
+
+#endif                         /* _PPC_KERNEL_M8260_PCI_H */
diff --git a/arch/powerpc/platforms/82xx/mpc82xx.c b/arch/powerpc/platforms/82xx/mpc82xx.c
new file mode 100644 (file)
index 0000000..89d702d
--- /dev/null
@@ -0,0 +1,111 @@
+/*
+ * MPC82xx setup and early boot code plus other random bits.
+ *
+ * Author: Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * Copyright (c) 2006 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/reboot.h>
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/kdev_t.h>
+#include <linux/major.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/root_dev.h>
+#include <linux/initrd.h>
+#include <linux/module.h>
+#include <linux/fsl_devices.h>
+#include <linux/fs_uart_pd.h>
+
+#include <asm/system.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/atomic.h>
+#include <asm/time.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/bootinfo.h>
+#include <asm/pci-bridge.h>
+#include <asm/mpc8260.h>
+#include <asm/irq.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/cpm2.h>
+#include <asm/udbg.h>
+#include <asm/i8259.h>
+#include <linux/fs_enet_pd.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/cpm2_pic.h>
+
+#include "pq2ads_pd.h"
+
+static int __init get_freq(char *name, unsigned long *val)
+{
+       struct device_node *cpu;
+       unsigned int *fp;
+       int found = 0;
+
+       /* The cpu node should have timebase and clock frequency properties */
+       cpu = of_find_node_by_type(NULL, "cpu");
+
+       if (cpu) {
+               fp = (unsigned int *)get_property(cpu, name, NULL);
+               if (fp) {
+                       found = 1;
+                       *val = *fp++;
+               }
+
+               of_node_put(cpu);
+       }
+
+       return found;
+}
+
+void __init m82xx_calibrate_decr(void)
+{
+       ppc_tb_freq = 125000000;
+       if (!get_freq("bus-frequency", &ppc_tb_freq)) {
+               printk(KERN_ERR "WARNING: Estimating decrementer frequency "
+                               "(not found)\n");
+       }
+       ppc_tb_freq /= 4;
+       ppc_proc_freq = 1000000000;
+       if (!get_freq("clock-frequency", &ppc_proc_freq))
+               printk(KERN_ERR "WARNING: Estimating processor frequency"
+                               "(not found)\n");
+}
+
+void mpc82xx_ads_show_cpuinfo(struct seq_file *m)
+{
+       uint pvid, svid, phid1;
+       uint memsize = total_memory;
+
+       pvid = mfspr(SPRN_PVR);
+       svid = mfspr(SPRN_SVR);
+
+       seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
+       seq_printf(m, "Machine\t\t: %s\n", CPUINFO_MACHINE);
+       seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
+       seq_printf(m, "SVR\t\t: 0x%x\n", svid);
+
+       /* Display cpu Pll setting */
+       phid1 = mfspr(SPRN_HID1);
+       seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
+
+       /* Display the amount of memory */
+       seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
+}
diff --git a/arch/powerpc/platforms/82xx/mpc82xx_ads.c b/arch/powerpc/platforms/82xx/mpc82xx_ads.c
new file mode 100644 (file)
index 0000000..4276f08
--- /dev/null
@@ -0,0 +1,661 @@
+/*
+ * MPC82xx_ads setup and early boot code plus other random bits.
+ *
+ * Author: Vitaly Bordug <vbordug@ru.mvista.com>
+ * m82xx_restart fix by Wade Farnsworth <wfarnsworth@mvista.com>
+ *
+ * Copyright (c) 2006 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+
+#include <linux/config.h>
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/reboot.h>
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/kdev_t.h>
+#include <linux/major.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/root_dev.h>
+#include <linux/initrd.h>
+#include <linux/module.h>
+#include <linux/fsl_devices.h>
+#include <linux/fs_uart_pd.h>
+
+#include <asm/system.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/atomic.h>
+#include <asm/time.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/bootinfo.h>
+#include <asm/pci-bridge.h>
+#include <asm/mpc8260.h>
+#include <asm/irq.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/cpm2.h>
+#include <asm/udbg.h>
+#include <asm/i8259.h>
+#include <linux/fs_enet_pd.h>
+
+#include <sysdev/fsl_soc.h>
+#include <../sysdev/cpm2_pic.h>
+
+#include "pq2ads_pd.h"
+
+#ifdef CONFIG_PCI
+static uint pci_clk_frq;
+static struct {
+       unsigned long *pci_int_stat_reg;
+       unsigned long *pci_int_mask_reg;
+} pci_regs;
+
+static unsigned long pci_int_base;
+static struct irq_host *pci_pic_host;
+static struct device_node *pci_pic_node;
+#endif
+
+static void __init mpc82xx_ads_pic_init(void)
+{
+       struct device_node *np = of_find_compatible_node(NULL, "cpm-pic", "CPM2");
+       struct resource r;
+       cpm2_map_t *cpm_reg;
+
+       if (np == NULL) {
+               printk(KERN_ERR "PIC init: can not find cpm-pic node\n");
+               return;
+       }
+       if (of_address_to_resource(np, 0, &r)) {
+               printk(KERN_ERR "PIC init: invalid resource\n");
+               of_node_put(np);
+               return;
+       }
+       cpm2_pic_init(np);
+       of_node_put(np);
+
+       /* Initialize the default interrupt mapping priorities,
+        * in case the boot rom changed something on us.
+        */
+       cpm_reg = (cpm2_map_t *) ioremap(get_immrbase(), sizeof(cpm2_map_t));
+       cpm_reg->im_intctl.ic_siprr = 0x05309770;
+       iounmap(cpm_reg);
+#ifdef CONFIG_PCI
+       /* Initialize stuff for the 82xx CPLD IC and install demux  */
+       m82xx_pci_init_irq();
+#endif
+}
+
+static void init_fcc1_ioports(struct fs_platform_info *fpi)
+{
+       struct io_port *io;
+       u32 tempval;
+       cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
+       struct device_node *np;
+       struct resource r;
+       u32 *bcsr;
+
+       np = of_find_node_by_type(NULL, "memory");
+       if (!np) {
+               printk(KERN_INFO "No memory node in device tree\n");
+               return;
+       }
+       if (of_address_to_resource(np, 1, &r)) {
+               printk(KERN_INFO "No memory reg property [1] in devicetree\n");
+               return;
+       }
+       of_node_put(np);
+       bcsr = ioremap(r.start + 4, sizeof(u32));
+       io = &immap->im_ioport;
+
+       /* Enable the PHY */
+       clrbits32(bcsr, BCSR1_FETHIEN);
+       setbits32(bcsr, BCSR1_FETH_RST);
+
+       /* FCC1 pins are on port A/C. */
+       /* Configure port A and C pins for FCC1 Ethernet. */
+
+       tempval = in_be32(&io->iop_pdira);
+       tempval &= ~PA1_DIRA0;
+       tempval |= PA1_DIRA1;
+       out_be32(&io->iop_pdira, tempval);
+
+       tempval = in_be32(&io->iop_psora);
+       tempval &= ~PA1_PSORA0;
+       tempval |= PA1_PSORA1;
+       out_be32(&io->iop_psora, tempval);
+
+       setbits32(&io->iop_ppara, PA1_DIRA0 | PA1_DIRA1);
+
+       /* Alter clocks */
+       tempval = PC_CLK(fpi->clk_tx - 8) | PC_CLK(fpi->clk_rx - 8);
+
+       clrbits32(&io->iop_psorc, tempval);
+       clrbits32(&io->iop_pdirc, tempval);
+       setbits32(&io->iop_pparc, tempval);
+
+       cpm2_clk_setup(CPM_CLK_FCC1, fpi->clk_rx, CPM_CLK_RX);
+       cpm2_clk_setup(CPM_CLK_FCC1, fpi->clk_tx, CPM_CLK_TX);
+
+       iounmap(bcsr);
+       iounmap(immap);
+}
+
+static void init_fcc2_ioports(struct fs_platform_info *fpi)
+{
+       cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
+       struct device_node *np;
+       struct resource r;
+       u32 *bcsr;
+
+       struct io_port *io;
+       u32 tempval;
+
+       np = of_find_node_by_type(NULL, "memory");
+       if (!np) {
+               printk(KERN_INFO "No memory node in device tree\n");
+               return;
+       }
+       if (of_address_to_resource(np, 1, &r)) {
+               printk(KERN_INFO "No memory reg property [1] in devicetree\n");
+               return;
+       }
+       of_node_put(np);
+       io = &immap->im_ioport;
+       bcsr = ioremap(r.start + 12, sizeof(u32));
+
+       /* Enable the PHY */
+       clrbits32(bcsr, BCSR3_FETHIEN2);
+       setbits32(bcsr, BCSR3_FETH2_RST);
+
+       /* FCC2 are port B/C. */
+       /* Configure port A and C pins for FCC2 Ethernet. */
+
+       tempval = in_be32(&io->iop_pdirb);
+       tempval &= ~PB2_DIRB0;
+       tempval |= PB2_DIRB1;
+       out_be32(&io->iop_pdirb, tempval);
+
+       tempval = in_be32(&io->iop_psorb);
+       tempval &= ~PB2_PSORB0;
+       tempval |= PB2_PSORB1;
+       out_be32(&io->iop_psorb, tempval);
+
+       setbits32(&io->iop_pparb, PB2_DIRB0 | PB2_DIRB1);
+
+       tempval = PC_CLK(fpi->clk_tx - 8) | PC_CLK(fpi->clk_rx - 8);
+
+       /* Alter clocks */
+       clrbits32(&io->iop_psorc, tempval);
+       clrbits32(&io->iop_pdirc, tempval);
+       setbits32(&io->iop_pparc, tempval);
+
+       cpm2_clk_setup(CPM_CLK_FCC2, fpi->clk_rx, CPM_CLK_RX);
+       cpm2_clk_setup(CPM_CLK_FCC2, fpi->clk_tx, CPM_CLK_TX);
+
+       iounmap(bcsr);
+       iounmap(immap);
+}
+
+void init_fcc_ioports(struct fs_platform_info *fpi)
+{
+       int fcc_no = fs_get_fcc_index(fpi->fs_no);
+
+       switch (fcc_no) {
+       case 0:
+               init_fcc1_ioports(fpi);
+               break;
+       case 1:
+               init_fcc2_ioports(fpi);
+               break;
+       default:
+               printk(KERN_ERR "init_fcc_ioports: invalid FCC number\n");
+               return;
+       }
+}
+
+static void init_scc1_uart_ioports(struct fs_uart_platform_info *data)
+{
+       cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
+
+       /* SCC1 is only on port D */
+       setbits32(&immap->im_ioport.iop_ppard, 0x00000003);
+       clrbits32(&immap->im_ioport.iop_psord, 0x00000001);
+       setbits32(&immap->im_ioport.iop_psord, 0x00000002);
+       clrbits32(&immap->im_ioport.iop_pdird, 0x00000001);
+       setbits32(&immap->im_ioport.iop_pdird, 0x00000002);
+
+       clrbits32(&immap->im_cpmux.cmx_scr, (0x00000007 << (4 - data->clk_tx)));
+       clrbits32(&immap->im_cpmux.cmx_scr, (0x00000038 << (4 - data->clk_rx)));
+       setbits32(&immap->im_cpmux.cmx_scr,
+                 ((data->clk_tx - 1) << (4 - data->clk_tx)));
+       setbits32(&immap->im_cpmux.cmx_scr,
+                 ((data->clk_rx - 1) << (4 - data->clk_rx)));
+
+       iounmap(immap);
+}
+
+static void init_scc4_uart_ioports(struct fs_uart_platform_info *data)
+{
+       cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
+
+       setbits32(&immap->im_ioport.iop_ppard, 0x00000600);
+       clrbits32(&immap->im_ioport.iop_psord, 0x00000600);
+       clrbits32(&immap->im_ioport.iop_pdird, 0x00000200);
+       setbits32(&immap->im_ioport.iop_pdird, 0x00000400);
+
+       clrbits32(&immap->im_cpmux.cmx_scr, (0x00000007 << (4 - data->clk_tx)));
+       clrbits32(&immap->im_cpmux.cmx_scr, (0x00000038 << (4 - data->clk_rx)));
+       setbits32(&immap->im_cpmux.cmx_scr,
+                 ((data->clk_tx - 1) << (4 - data->clk_tx)));
+       setbits32(&immap->im_cpmux.cmx_scr,
+                 ((data->clk_rx - 1) << (4 - data->clk_rx)));
+
+       iounmap(immap);
+}
+
+void init_scc_ioports(struct fs_uart_platform_info *data)
+{
+       int scc_no = fs_get_scc_index(data->fs_no);
+
+       switch (scc_no) {
+       case 0:
+               init_scc1_uart_ioports(data);
+               data->brg = data->clk_rx;
+               break;
+       case 3:
+               init_scc4_uart_ioports(data);
+               data->brg = data->clk_rx;
+               break;
+       default:
+               printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
+               return;
+       }
+}
+
+void __init m82xx_board_setup(void)
+{
+       cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
+       struct device_node *np;
+       struct resource r;
+       u32 *bcsr;
+
+       np = of_find_node_by_type(NULL, "memory");
+       if (!np) {
+               printk(KERN_INFO "No memory node in device tree\n");
+               return;
+       }
+       if (of_address_to_resource(np, 1, &r)) {
+               printk(KERN_INFO "No memory reg property [1] in devicetree\n");
+               return;
+       }
+       of_node_put(np);
+       bcsr = ioremap(r.start + 4, sizeof(u32));
+       /* Enable the 2nd UART port */
+       clrbits32(bcsr, BCSR1_RS232_EN2);
+
+#ifdef CONFIG_SERIAL_CPM_SCC1
+       clrbits32((u32 *) & immap->im_scc[0].scc_sccm,
+                 UART_SCCM_TX | UART_SCCM_RX);
+       clrbits32((u32 *) & immap->im_scc[0].scc_gsmrl,
+                 SCC_GSMRL_ENR | SCC_GSMRL_ENT);
+#endif
+
+#ifdef CONFIG_SERIAL_CPM_SCC2
+       clrbits32((u32 *) & immap->im_scc[1].scc_sccm,
+                 UART_SCCM_TX | UART_SCCM_RX);
+       clrbits32((u32 *) & immap->im_scc[1].scc_gsmrl,
+                 SCC_GSMRL_ENR | SCC_GSMRL_ENT);
+#endif
+
+#ifdef CONFIG_SERIAL_CPM_SCC3
+       clrbits32((u32 *) & immap->im_scc[2].scc_sccm,
+                 UART_SCCM_TX | UART_SCCM_RX);
+       clrbits32((u32 *) & immap->im_scc[2].scc_gsmrl,
+                 SCC_GSMRL_ENR | SCC_GSMRL_ENT);
+#endif
+
+#ifdef CONFIG_SERIAL_CPM_SCC4
+       clrbits32((u32 *) & immap->im_scc[3].scc_sccm,
+                 UART_SCCM_TX | UART_SCCM_RX);
+       clrbits32((u32 *) & immap->im_scc[3].scc_gsmrl,
+                 SCC_GSMRL_ENR | SCC_GSMRL_ENT);
+#endif
+
+       iounmap(bcsr);
+       iounmap(immap);
+}
+
+#ifdef CONFIG_PCI
+static void m82xx_pci_mask_irq(unsigned int irq)
+{
+       int bit = irq - pci_int_base;
+
+       *pci_regs.pci_int_mask_reg |= (1 << (31 - bit));
+       return;
+}
+
+static void m82xx_pci_unmask_irq(unsigned int irq)
+{
+       int bit = irq - pci_int_base;
+
+       *pci_regs.pci_int_mask_reg &= ~(1 << (31 - bit));
+       return;
+}
+
+static void m82xx_pci_mask_and_ack(unsigned int irq)
+{
+       int bit = irq - pci_int_base;
+
+       *pci_regs.pci_int_mask_reg |= (1 << (31 - bit));
+       return;
+}
+
+static void m82xx_pci_end_irq(unsigned int irq)
+{
+       int bit = irq - pci_int_base;
+
+       *pci_regs.pci_int_mask_reg &= ~(1 << (31 - bit));
+       return;
+}
+
+struct hw_interrupt_type m82xx_pci_ic = {
+       .typename = "MPC82xx ADS PCI",
+       .name = "MPC82xx ADS PCI",
+       .enable = m82xx_pci_unmask_irq,
+       .disable = m82xx_pci_mask_irq,
+       .ack = m82xx_pci_mask_and_ack,
+       .end = m82xx_pci_end_irq,
+       .mask = m82xx_pci_mask_irq,
+       .mask_ack = m82xx_pci_mask_and_ack,
+       .unmask = m82xx_pci_unmask_irq,
+       .eoi = m82xx_pci_end_irq,
+};
+
+static void
+m82xx_pci_irq_demux(unsigned int irq, struct irq_desc *desc,
+                   struct pt_regs *regs)
+{
+       unsigned long stat, mask, pend;
+       int bit;
+
+       for (;;) {
+               stat = *pci_regs.pci_int_stat_reg;
+               mask = *pci_regs.pci_int_mask_reg;
+               pend = stat & ~mask & 0xf0000000;
+               if (!pend)
+                       break;
+               for (bit = 0; pend != 0; ++bit, pend <<= 1) {
+                       if (pend & 0x80000000)
+                               __do_IRQ(pci_int_base + bit, regs);
+               }
+       }
+}
+
+static int pci_pic_host_match(struct irq_host *h, struct device_node *node)
+{
+       return node == pci_pic_node;
+}
+
+static int pci_pic_host_map(struct irq_host *h, unsigned int virq,
+                           irq_hw_number_t hw)
+{
+       get_irq_desc(virq)->status |= IRQ_LEVEL;
+       set_irq_chip(virq, &m82xx_pci_ic);
+       return 0;
+}
+
+static void pci_host_unmap(struct irq_host *h, unsigned int virq)
+{
+       /* remove chip and handler */
+       set_irq_chip(virq, NULL);
+}
+
+static struct irq_host_ops pci_pic_host_ops = {
+       .match = pci_pic_host_match,
+       .map = pci_pic_host_map,
+       .unmap = pci_host_unmap,
+};
+
+void m82xx_pci_init_irq(void)
+{
+       int irq;
+       cpm2_map_t *immap;
+       struct device_node *np;
+       struct resource r;
+       const u32 *regs;
+       unsigned int size;
+       const u32 *irq_map;
+       int i;
+       unsigned int irq_max, irq_min;
+
+       if ((np = of_find_node_by_type(NULL, "soc")) == NULL) {
+               printk(KERN_INFO "No SOC node in device tree\n");
+               return;
+       }
+       memset(&r, 0, sizeof(r));
+       if (of_address_to_resource(np, 0, &r)) {
+               printk(KERN_INFO "No SOC reg property in device tree\n");
+               return;
+       }
+       immap = ioremap(r.start, sizeof(*immap));
+       of_node_put(np);
+
+       /* install the demultiplexer for the PCI cascade interrupt */
+       np = of_find_node_by_type(NULL, "pci");
+       if (!np) {
+               printk(KERN_INFO "No pci node on device tree\n");
+               iounmap(immap);
+               return;
+       }
+       irq_map = get_property(np, "interrupt-map", &size);
+       if ((!irq_map) || (size <= 7)) {
+               printk(KERN_INFO "No interrupt-map property of pci node\n");
+               iounmap(immap);
+               return;
+       }
+       size /= sizeof(irq_map[0]);
+       for (i = 0, irq_max = 0, irq_min = 512; i < size; i += 7, irq_map += 7) {
+               if (irq_map[5] < irq_min)
+                       irq_min = irq_map[5];
+               if (irq_map[5] > irq_max)
+                       irq_max = irq_map[5];
+       }
+       pci_int_base = irq_min;
+       irq = irq_of_parse_and_map(np, 0);
+       set_irq_chained_handler(irq, m82xx_pci_irq_demux);
+       of_node_put(np);
+       np = of_find_node_by_type(NULL, "pci-pic");
+       if (!np) {
+               printk(KERN_INFO "No pci pic node on device tree\n");
+               iounmap(immap);
+               return;
+       }
+       pci_pic_node = of_node_get(np);
+       /* PCI interrupt controller registers: status and mask */
+       regs = get_property(np, "reg", &size);
+       if ((!regs) || (size <= 2)) {
+               printk(KERN_INFO "No reg property in pci pic node\n");
+               iounmap(immap);
+               return;
+       }
+       pci_regs.pci_int_stat_reg =
+           ioremap(regs[0], sizeof(*pci_regs.pci_int_stat_reg));
+       pci_regs.pci_int_mask_reg =
+           ioremap(regs[1], sizeof(*pci_regs.pci_int_mask_reg));
+       of_node_put(np);
+       /* configure chip select for PCI interrupt controller */
+       immap->im_memctl.memc_br3 = regs[0] | 0x00001801;
+       immap->im_memctl.memc_or3 = 0xffff8010;
+       /* make PCI IRQ level sensitive */
+       immap->im_intctl.ic_siexr &= ~(1 << (14 - (irq - SIU_INT_IRQ1)));
+
+       /* mask all PCI interrupts */
+       *pci_regs.pci_int_mask_reg |= 0xfff00000;
+       iounmap(immap);
+       pci_pic_host =
+           irq_alloc_host(IRQ_HOST_MAP_LINEAR, irq_max - irq_min + 1,
+                          &pci_pic_host_ops, irq_max + 1);
+       return;
+}
+
+static int m82xx_pci_exclude_device(u_char bus, u_char devfn)
+{
+       if (bus == 0 && PCI_SLOT(devfn) == 0)
+               return PCIBIOS_DEVICE_NOT_FOUND;
+       else
+               return PCIBIOS_SUCCESSFUL;
+}
+
+static void
+__init mpc82xx_pcibios_fixup(void)
+{
+       struct pci_dev *dev = NULL;
+
+       for_each_pci_dev(dev) {
+               pci_read_irq_line(dev);
+       }
+}
+
+void __init add_bridge(struct device_node *np)
+{
+       int len;
+       struct pci_controller *hose;
+       struct resource r;
+       const int *bus_range;
+       const void *ptr;
+
+       memset(&r, 0, sizeof(r));
+       if (of_address_to_resource(np, 0, &r)) {
+               printk(KERN_INFO "No PCI reg property in device tree\n");
+               return;
+       }
+       if (!(ptr = get_property(np, "clock-frequency", NULL))) {
+               printk(KERN_INFO "No clock-frequency property in PCI node");
+               return;
+       }
+       pci_clk_frq = *(uint *) ptr;
+       of_node_put(np);
+       bus_range = get_property(np, "bus-range", &len);
+       if (bus_range == NULL || len < 2 * sizeof(int)) {
+               printk(KERN_WARNING "Can't get bus-range for %s, assume"
+                      " bus 0\n", np->full_name);
+       }
+
+       pci_assign_all_buses = 1;
+
+       hose = pcibios_alloc_controller();
+
+       if (!hose)
+               return;
+
+       hose->arch_data = np;
+       hose->set_cfg_type = 1;
+
+       hose->first_busno = bus_range ? bus_range[0] : 0;
+       hose->last_busno = bus_range ? bus_range[1] : 0xff;
+       hose->bus_offset = 0;
+
+       hose->set_cfg_type = 1;
+
+       setup_indirect_pci(hose,
+                          r.start + offsetof(pci_cpm2_t, pci_cfg_addr),
+                          r.start + offsetof(pci_cpm2_t, pci_cfg_data));
+
+       pci_process_bridge_OF_ranges(hose, np, 1);
+}
+#endif
+
+/*
+ * Setup the architecture
+ */
+static void __init mpc82xx_ads_setup_arch(void)
+{
+#ifdef CONFIG_PCI
+       struct device_node *np;
+#endif
+
+       if (ppc_md.progress)
+               ppc_md.progress("mpc82xx_ads_setup_arch()", 0);
+       cpm2_reset();
+
+       /* Map I/O region to a 256MB BAT */
+
+       m82xx_board_setup();
+
+#ifdef CONFIG_PCI
+       ppc_md.pci_exclude_device = m82xx_pci_exclude_device;
+       for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
+               add_bridge(np);
+
+       of_node_put(np);
+       ppc_md.pci_map_irq = NULL;
+       ppc_md.pcibios_fixup = mpc82xx_pcibios_fixup;
+       ppc_md.pcibios_fixup_bus = NULL;
+#endif
+
+#ifdef  CONFIG_ROOT_NFS
+       ROOT_DEV = Root_NFS;
+#else
+       ROOT_DEV = Root_HDA1;
+#endif
+
+       if (ppc_md.progress)
+               ppc_md.progress("mpc82xx_ads_setup_arch(), finish", 0);
+}
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init mpc82xx_ads_probe(void)
+{
+       /* We always match for now, eventually we should look at
+        * the flat dev tree to ensure this is the board we are
+        * supposed to run on
+        */
+       return 1;
+}
+
+#define RMR_CSRE 0x00000001
+static void m82xx_restart(char *cmd)
+{
+       __volatile__ unsigned char dummy;
+
+       local_irq_disable();
+       ((cpm2_map_t *) cpm2_immr)->im_clkrst.car_rmr |= RMR_CSRE;
+
+       /* Clear the ME,EE,IR & DR bits in MSR to cause checkstop */
+       mtmsr(mfmsr() & ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR));
+       dummy = ((cpm2_map_t *) cpm2_immr)->im_clkrst.res[0];
+       printk("Restart failed\n");
+       while (1) ;
+}
+
+static void m82xx_halt(void)
+{
+       local_irq_disable();
+       while (1) ;
+}
+
+define_machine(mpc82xx_ads)
+{
+       .name = "MPC82xx ADS",
+       .probe = mpc82xx_ads_probe,
+       .setup_arch =    mpc82xx_ads_setup_arch,
+       .init_IRQ =    mpc82xx_ads_pic_init,
+       .show_cpuinfo =    mpc82xx_ads_show_cpuinfo,
+       .get_irq =    cpm2_get_irq,
+       .calibrate_decr =    m82xx_calibrate_decr,
+       .restart = m82xx_restart,.halt = m82xx_halt,
+};
diff --git a/arch/powerpc/platforms/82xx/pq2ads.h b/arch/powerpc/platforms/82xx/pq2ads.h
new file mode 100644 (file)
index 0000000..a734821
--- /dev/null
@@ -0,0 +1,67 @@
+/*
+ * PQ2/mpc8260 board-specific stuff
+ *
+ * A collection of structures, addresses, and values associated with
+ * the Freescale MPC8260ADS/MPC8266ADS-PCI boards.
+ * Copied from the RPX-Classic and SBS8260 stuff.
+ *
+ * Author: Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * Originally written by Dan Malek for Motorola MPC8260 family
+ *
+ * Copyright (c) 2001 Dan Malek <dan@embeddedalley.com>
+ * Copyright (c) 2006 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifdef __KERNEL__
+#ifndef __MACH_ADS8260_DEFS
+#define __MACH_ADS8260_DEFS
+
+#include <linux/config.h>
+
+#include <asm/ppcboot.h>
+
+/* For our show_cpuinfo hooks. */
+#define CPUINFO_VENDOR         "Freescale Semiconductor"
+#define CPUINFO_MACHINE                "PQ2 ADS PowerPC"
+
+/* Backword-compatibility stuff for the drivers */
+#define CPM_MAP_ADDR           ((uint)0xf0000000)
+#define CPM_IRQ_OFFSET 0
+
+/* The ADS8260 has 16, 32-bit wide control/status registers, accessed
+ * only on word boundaries.
+ * Not all are used (yet), or are interesting to us (yet).
+ */
+
+/* Things of interest in the CSR.
+ */
+#define BCSR0_LED0             ((uint)0x02000000)      /* 0 == on */
+#define BCSR0_LED1             ((uint)0x01000000)      /* 0 == on */
+#define BCSR1_FETHIEN          ((uint)0x08000000)      /* 0 == enable*/
+#define BCSR1_FETH_RST         ((uint)0x04000000)      /* 0 == reset */
+#define BCSR1_RS232_EN1                ((uint)0x02000000)      /* 0 ==enable */
+#define BCSR1_RS232_EN2                ((uint)0x01000000)      /* 0 ==enable */
+#define BCSR3_FETHIEN2         ((uint)0x10000000)      /* 0 == enable*/
+#define BCSR3_FETH2_RS         ((uint)0x80000000)      /* 0 == reset */
+
+/* cpm serial driver works with constants below */
+
+#define SIU_INT_SMC1           ((uint)0x04+CPM_IRQ_OFFSET)
+#define SIU_INT_SMC2i          ((uint)0x05+CPM_IRQ_OFFSET)
+#define SIU_INT_SCC1           ((uint)0x28+CPM_IRQ_OFFSET)
+#define SIU_INT_SCC2           ((uint)0x29+CPM_IRQ_OFFSET)
+#define SIU_INT_SCC3           ((uint)0x2a+CPM_IRQ_OFFSET)
+#define SIU_INT_SCC4           ((uint)0x2b+CPM_IRQ_OFFSET)
+
+void m82xx_pci_init_irq(void);
+void mpc82xx_ads_show_cpuinfo(struct seq_file*);
+void m82xx_calibrate_decr(void);
+
+#endif /* __MACH_ADS8260_DEFS */
+#endif /* __KERNEL__ */
index 5fe7b7f..0975e94 100644 (file)
@@ -5,6 +5,13 @@ choice
        prompt "Machine Type"
        default MPC834x_SYS
 
+config MPC832x_MDS
+       bool "Freescale MPC832x MDS"
+       select DEFAULT_UIMAGE
+       select QUICC_ENGINE
+       help
+         This option enables support for the MPC832x MDS evaluation board.
+
 config MPC834x_SYS
        bool "Freescale MPC834x SYS"
        select DEFAULT_UIMAGE
@@ -27,6 +34,12 @@ config MPC834x_ITX
 
 endchoice
 
+config PPC_MPC832x
+       bool
+       select PPC_UDBG_16550
+       select PPC_INDIRECT_PCI
+       default y if MPC832x_MDS
+
 config MPC834x
        bool
        select PPC_UDBG_16550
diff --git a/arch/powerpc/platforms/83xx/mpc832x_mds.c b/arch/powerpc/platforms/83xx/mpc832x_mds.c
new file mode 100644 (file)
index 0000000..54dea9d
--- /dev/null
@@ -0,0 +1,215 @@
+/*
+ * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
+ *
+ * Description:
+ * MPC832xE MDS board specific routines.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/reboot.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/major.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/root_dev.h>
+#include <linux/initrd.h>
+
+#include <asm/system.h>
+#include <asm/atomic.h>
+#include <asm/time.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/ipic.h>
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <sysdev/fsl_soc.h>
+#include <asm/qe.h>
+#include <asm/qe_ic.h>
+
+#include "mpc83xx.h"
+#include "mpc832x_mds.h"
+
+#undef DEBUG
+#ifdef DEBUG
+#define DBG(fmt...) udbg_printf(fmt)
+#else
+#define DBG(fmt...)
+#endif
+
+#ifndef CONFIG_PCI
+unsigned long isa_io_base = 0;
+unsigned long isa_mem_base = 0;
+#endif
+
+static u8 *bcsr_regs = NULL;
+
+u8 *get_bcsr(void)
+{
+       return bcsr_regs;
+}
+
+/* ************************************************************************
+ *
+ * Setup the architecture
+ *
+ */
+static void __init mpc832x_sys_setup_arch(void)
+{
+       struct device_node *np;
+
+       if (ppc_md.progress)
+               ppc_md.progress("mpc832x_sys_setup_arch()", 0);
+
+       np = of_find_node_by_type(NULL, "cpu");
+       if (np != 0) {
+               unsigned int *fp =
+                   (int *)get_property(np, "clock-frequency", NULL);
+               if (fp != 0)
+                       loops_per_jiffy = *fp / HZ;
+               else
+                       loops_per_jiffy = 50000000 / HZ;
+               of_node_put(np);
+       }
+
+       /* Map BCSR area */
+       np = of_find_node_by_name(NULL, "bcsr");
+       if (np != 0) {
+               struct resource res;
+
+               of_address_to_resource(np, 0, &res);
+               bcsr_regs = ioremap(res.start, res.end - res.start +1);
+               of_node_put(np);
+       }
+
+#ifdef CONFIG_PCI
+       for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
+               add_bridge(np);
+
+       ppc_md.pci_swizzle = common_swizzle;
+       ppc_md.pci_exclude_device = mpc83xx_exclude_device;
+#endif
+
+#ifdef CONFIG_QUICC_ENGINE
+       qe_reset();
+
+       if ((np = of_find_node_by_name(np, "par_io")) != NULL) {
+               par_io_init(np);
+               of_node_put(np);
+
+               for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
+                       par_io_of_config(np);
+       }
+
+       if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
+                       != NULL){
+               /* Reset the Ethernet PHY */
+               bcsr_regs[9] &= ~0x20;
+               udelay(1000);
+               bcsr_regs[9] |= 0x20;
+               iounmap(bcsr_regs);
+               of_node_put(np);
+       }
+
+#endif                         /* CONFIG_QUICC_ENGINE */
+
+#ifdef CONFIG_BLK_DEV_INITRD
+       if (initrd_start)
+               ROOT_DEV = Root_RAM0;
+       else
+#endif
+#ifdef  CONFIG_ROOT_NFS
+               ROOT_DEV = Root_NFS;
+#else
+               ROOT_DEV = Root_HDA1;
+#endif
+}
+
+void __init mpc832x_sys_init_IRQ(void)
+{
+
+       struct device_node *np;
+
+       np = of_find_node_by_type(NULL, "ipic");
+       if (!np)
+               return;
+
+       ipic_init(np, 0);
+
+       /* Initialize the default interrupt mapping priorities,
+        * in case the boot rom changed something on us.
+        */
+       ipic_set_default_priority();
+       of_node_put(np);
+
+#ifdef CONFIG_QUICC_ENGINE
+       np = of_find_node_by_type(NULL, "qeic");
+       if (!np)
+               return;
+
+       qe_ic_init(np, 0);
+       of_node_put(np);
+#endif                         /* CONFIG_QUICC_ENGINE */
+}
+
+#if defined(CONFIG_I2C_MPC) && defined(CONFIG_SENSORS_DS1374)
+extern ulong ds1374_get_rtc_time(void);
+extern int ds1374_set_rtc_time(ulong);
+
+static int __init mpc832x_rtc_hookup(void)
+{
+       struct timespec tv;
+
+       ppc_md.get_rtc_time = ds1374_get_rtc_time;
+       ppc_md.set_rtc_time = ds1374_set_rtc_time;
+
+       tv.tv_nsec = 0;
+       tv.tv_sec = (ppc_md.get_rtc_time) ();
+       do_settimeofday(&tv);
+
+       return 0;
+}
+
+late_initcall(mpc832x_rtc_hookup);
+#endif
+
+/*
+ * Called very early, MMU is off, device-tree isn't unflattened
+ */
+static int __init mpc832x_sys_probe(void)
+{
+       char *model = of_get_flat_dt_prop(of_get_flat_dt_root(),
+                                         "model", NULL);
+
+       if (model == NULL)
+               return 0;
+       if (strcmp(model, "MPC8323EMDS"))
+               return 0;
+
+       DBG("%s found\n", model);
+
+       return 1;
+}
+
+define_machine(mpc832x_mds) {
+       .name           = "MPC832x MDS",
+       .probe          = mpc832x_sys_probe,
+       .setup_arch     = mpc832x_sys_setup_arch,
+       .init_IRQ       = mpc832x_sys_init_IRQ,
+       .get_irq        = ipic_get_irq,
+       .restart        = mpc83xx_restart,
+       .time_init      = mpc83xx_time_init,
+       .calibrate_decr = generic_calibrate_decr,
+       .progress       = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/83xx/mpc832x_mds.h b/arch/powerpc/platforms/83xx/mpc832x_mds.h
new file mode 100644 (file)
index 0000000..a495889
--- /dev/null
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
+ *
+ * Description:
+ * MPC832x MDS board specific header.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __MACH_MPC832x_MDS_H__
+#define __MACH_MPC832x_MDS_H__
+
+extern u8 *get_bcsr(void);
+
+#endif                         /* __MACH_MPC832x_MDS_H__ */
diff --git a/arch/powerpc/platforms/83xx/mpc8360e_pb.c b/arch/powerpc/platforms/83xx/mpc8360e_pb.c
new file mode 100644 (file)
index 0000000..c019190
--- /dev/null
@@ -0,0 +1,219 @@
+/*
+ * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
+ *
+ * Author: Li Yang <LeoLi@freescale.com>
+ *        Yin Olivia <Hong-hua.Yin@freescale.com>
+ *
+ * Description:
+ * MPC8360E MDS PB board specific routines.
+ *
+ * Changelog:
+ * Jun 21, 2006        Initial version
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/reboot.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/major.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/root_dev.h>
+#include <linux/initrd.h>
+
+#include <asm/system.h>
+#include <asm/atomic.h>
+#include <asm/time.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/ipic.h>
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <sysdev/fsl_soc.h>
+#include <asm/qe.h>
+#include <asm/qe_ic.h>
+
+#include "mpc83xx.h"
+
+#undef DEBUG
+#ifdef DEBUG
+#define DBG(fmt...) udbg_printf(fmt)
+#else
+#define DBG(fmt...)
+#endif
+
+#ifndef CONFIG_PCI
+unsigned long isa_io_base = 0;
+unsigned long isa_mem_base = 0;
+#endif
+
+static u8 *bcsr_regs = NULL;
+
+u8 *get_bcsr(void)
+{
+       return bcsr_regs;
+}
+
+/* ************************************************************************
+ *
+ * Setup the architecture
+ *
+ */
+static void __init mpc8360_sys_setup_arch(void)
+{
+       struct device_node *np;
+
+       if (ppc_md.progress)
+               ppc_md.progress("mpc8360_sys_setup_arch()", 0);
+
+       np = of_find_node_by_type(NULL, "cpu");
+       if (np != 0) {
+               const unsigned int *fp =
+                   get_property(np, "clock-frequency", NULL);
+               if (fp != 0)
+                       loops_per_jiffy = *fp / HZ;
+               else
+                       loops_per_jiffy = 50000000 / HZ;
+               of_node_put(np);
+       }
+
+       /* Map BCSR area */
+       np = of_find_node_by_name(NULL, "bcsr");
+       if (np != 0) {
+               struct resource res;
+
+               of_address_to_resource(np, 0, &res);
+               bcsr_regs = ioremap(res.start, res.end - res.start +1);
+               of_node_put(np);
+       }
+
+#ifdef CONFIG_PCI
+       for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
+               add_bridge(np);
+
+       ppc_md.pci_swizzle = common_swizzle;
+       ppc_md.pci_exclude_device = mpc83xx_exclude_device;
+#endif
+
+#ifdef CONFIG_QUICC_ENGINE
+       qe_reset();
+
+       if ((np = of_find_node_by_name(np, "par_io")) != NULL) {
+               par_io_init(np);
+               of_node_put(np);
+
+               for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
+                       par_io_of_config(np);
+       }
+
+       if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
+                       != NULL){
+               /* Reset the Ethernet PHY */
+               bcsr_regs[9] &= ~0x20;
+               udelay(1000);
+               bcsr_regs[9] |= 0x20;
+               iounmap(bcsr_regs);
+               of_node_put(np);
+       }
+
+#endif                         /* CONFIG_QUICC_ENGINE */
+
+#ifdef CONFIG_BLK_DEV_INITRD
+       if (initrd_start)
+               ROOT_DEV = Root_RAM0;
+       else
+#endif
+#ifdef  CONFIG_ROOT_NFS
+               ROOT_DEV = Root_NFS;
+#else
+               ROOT_DEV = Root_HDA1;
+#endif
+}
+
+void __init mpc8360_sys_init_IRQ(void)
+{
+
+       struct device_node *np;
+
+       np = of_find_node_by_type(NULL, "ipic");
+       if (!np)
+               return;
+
+       ipic_init(np, 0);
+
+       /* Initialize the default interrupt mapping priorities,
+        * in case the boot rom changed something on us.
+        */
+       ipic_set_default_priority();
+       of_node_put(np);
+
+#ifdef CONFIG_QUICC_ENGINE
+       np = of_find_node_by_type(NULL, "qeic");
+       if (!np)
+               return;
+
+       qe_ic_init(np, 0);
+       of_node_put(np);
+#endif                         /* CONFIG_QUICC_ENGINE */
+}
+
+#if defined(CONFIG_I2C_MPC) && defined(CONFIG_SENSORS_DS1374)
+extern ulong ds1374_get_rtc_time(void);
+extern int ds1374_set_rtc_time(ulong);
+
+static int __init mpc8360_rtc_hookup(void)
+{
+       struct timespec tv;
+
+       ppc_md.get_rtc_time = ds1374_get_rtc_time;
+       ppc_md.set_rtc_time = ds1374_set_rtc_time;
+
+       tv.tv_nsec = 0;
+       tv.tv_sec = (ppc_md.get_rtc_time) ();
+       do_settimeofday(&tv);
+
+       return 0;
+}
+
+late_initcall(mpc8360_rtc_hookup);
+#endif
+
+/*
+ * Called very early, MMU is off, device-tree isn't unflattened
+ */
+static int __init mpc8360_sys_probe(void)
+{
+       char *model = of_get_flat_dt_prop(of_get_flat_dt_root(),
+                                         "model", NULL);
+       if (model == NULL)
+               return 0;
+       if (strcmp(model, "MPC8360EPB"))
+               return 0;
+
+       DBG("MPC8360EMDS-PB found\n");
+
+       return 1;
+}
+
+define_machine(mpc8360_sys) {
+       .name           = "MPC8360E PB",
+       .probe          = mpc8360_sys_probe,
+       .setup_arch     = mpc8360_sys_setup_arch,
+       .init_IRQ       = mpc8360_sys_init_IRQ,
+       .get_irq        = ipic_get_irq,
+       .restart        = mpc83xx_restart,
+       .time_init      = mpc83xx_time_init,
+       .calibrate_decr = generic_calibrate_decr,
+       .progress       = udbg_progress,
+};
index 6b57a47..6cc59e0 100644 (file)
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * TODO:
+ * - Fix various assumptions related to HW CPU numbers vs. linux CPU numbers
+ *   vs node numbers in the setup code
+ * - Implement proper handling of maxcpus=1/2 (that is, routing of irqs from
+ *   a non-active node to the active node)
  */
 
 #include <linux/interrupt.h>
@@ -44,24 +50,25 @@ struct iic {
        u8 target_id;
        u8 eoi_stack[16];
        int eoi_ptr;
-       struct irq_host *host;
+       struct device_node *node;
 };
 
 static DEFINE_PER_CPU(struct iic, iic);
 #define IIC_NODE_COUNT 2
-static struct irq_host *iic_hosts[IIC_NODE_COUNT];
+static struct irq_host *iic_host;
 
 /* Convert between "pending" bits and hw irq number */
 static irq_hw_number_t iic_pending_to_hwnum(struct cbe_iic_pending_bits bits)
 {
        unsigned char unit = bits.source & 0xf;
+       unsigned char node = bits.source >> 4;
+       unsigned char class = bits.class & 3;
 
+       /* Decode IPIs */
        if (bits.flags & CBE_IIC_IRQ_IPI)
-               return IIC_IRQ_IPI0 | (bits.prio >> 4);
-       else if (bits.class <= 3)
-               return (bits.class << 4) | unit;
+               return IIC_IRQ_TYPE_IPI | (bits.prio >> 4);
        else
-               return IIC_IRQ_INVALID;
+               return (node << IIC_IRQ_NODE_SHIFT) | (class << 4) | unit;
 }
 
 static void iic_mask(unsigned int irq)
@@ -86,21 +93,70 @@ static struct irq_chip iic_chip = {
        .eoi = iic_eoi,
 };
 
+
+static void iic_ioexc_eoi(unsigned int irq)
+{
+}
+
+static void iic_ioexc_cascade(unsigned int irq, struct irq_desc *desc,
+                           struct pt_regs *regs)
+{
+       struct cbe_iic_regs *node_iic = desc->handler_data;
+       unsigned int base = (irq & 0xffffff00) | IIC_IRQ_TYPE_IOEXC;
+       unsigned long bits, ack;
+       int cascade;
+
+       for (;;) {
+               bits = in_be64(&node_iic->iic_is);
+               if (bits == 0)
+                       break;
+               /* pre-ack edge interrupts */
+               ack = bits & IIC_ISR_EDGE_MASK;
+               if (ack)
+                       out_be64(&node_iic->iic_is, ack);
+               /* handle them */
+               for (cascade = 63; cascade >= 0; cascade--)
+                       if (bits & (0x8000000000000000UL >> cascade)) {
+                               unsigned int cirq =
+                                       irq_linear_revmap(iic_host,
+                                                         base | cascade);
+                               if (cirq != NO_IRQ)
+                                       generic_handle_irq(cirq, regs);
+                       }
+               /* post-ack level interrupts */
+               ack = bits & ~IIC_ISR_EDGE_MASK;
+               if (ack)
+                       out_be64(&node_iic->iic_is, ack);
+       }
+       desc->chip->eoi(irq);
+}
+
+
+static struct irq_chip iic_ioexc_chip = {
+       .typename = " CELL-IOEX",
+       .mask = iic_mask,
+       .unmask = iic_unmask,
+       .eoi = iic_ioexc_eoi,
+};
+
 /* Get an IRQ number from the pending state register of the IIC */
 static unsigned int iic_get_irq(struct pt_regs *regs)
 {
        struct cbe_iic_pending_bits pending;
        struct iic *iic;
+       unsigned int virq;
 
        iic = &__get_cpu_var(iic);
        *(unsigned long *) &pending =
                in_be64((unsigned long __iomem *) &iic->regs->pending_destr);
+       if (!(pending.flags & CBE_IIC_IRQ_VALID))
+               return NO_IRQ;
+       virq = irq_linear_revmap(iic_host, iic_pending_to_hwnum(pending));
+       if (virq == NO_IRQ)
+               return NO_IRQ;
        iic->eoi_stack[++iic->eoi_ptr] = pending.prio;
        BUG_ON(iic->eoi_ptr > 15);
-       if (pending.flags & CBE_IIC_IRQ_VALID)
-               return irq_linear_revmap(iic->host,
-                                        iic_pending_to_hwnum(pending));
-       return NO_IRQ;
+       return virq;
 }
 
 #ifdef CONFIG_SMP
@@ -108,12 +164,7 @@ static unsigned int iic_get_irq(struct pt_regs *regs)
 /* Use the highest interrupt priorities for IPI */
 static inline int iic_ipi_to_irq(int ipi)
 {
-       return IIC_IRQ_IPI0 + IIC_NUM_IPIS - 1 - ipi;
-}
-
-static inline int iic_irq_to_ipi(int irq)
-{
-       return IIC_NUM_IPIS - 1 - (irq - IIC_IRQ_IPI0);
+       return IIC_IRQ_TYPE_IPI + 0xf - ipi;
 }
 
 void iic_setup_cpu(void)
@@ -123,7 +174,7 @@ void iic_setup_cpu(void)
 
 void iic_cause_IPI(int cpu, int mesg)
 {
-       out_be64(&per_cpu(iic, cpu).regs->generate, (IIC_NUM_IPIS - 1 - mesg) << 4);
+       out_be64(&per_cpu(iic, cpu).regs->generate, (0xf - mesg) << 4);
 }
 
 u8 iic_get_target_id(int cpu)
@@ -134,9 +185,7 @@ EXPORT_SYMBOL_GPL(iic_get_target_id);
 
 struct irq_host *iic_get_irq_host(int node)
 {
-       if (node < 0 || node >= IIC_NODE_COUNT)
-               return NULL;
-       return iic_hosts[node];
+       return iic_host;
 }
 EXPORT_SYMBOL_GPL(iic_get_irq_host);
 
@@ -149,34 +198,20 @@ static irqreturn_t iic_ipi_action(int irq, void *dev_id, struct pt_regs *regs)
 
        return IRQ_HANDLED;
 }
-
 static void iic_request_ipi(int ipi, const char *name)
 {
-       int node, virq;
+       int virq;
 
-       for (node = 0; node < IIC_NODE_COUNT; node++) {
-               char *rname;
-               if (iic_hosts[node] == NULL)
-                       continue;
-               virq = irq_create_mapping(iic_hosts[node],
-                                         iic_ipi_to_irq(ipi));
-               if (virq == NO_IRQ) {
-                       printk(KERN_ERR
-                              "iic: failed to map IPI %s on node %d\n",
-                              name, node);
-                       continue;
-               }
-               rname = kzalloc(strlen(name) + 16, GFP_KERNEL);
-               if (rname)
-                       sprintf(rname, "%s node %d", name, node);
-               else
-                       rname = (char *)name;
-               if (request_irq(virq, iic_ipi_action, IRQF_DISABLED,
-                               rname, (void *)(long)ipi))
-                       printk(KERN_ERR
-                              "iic: failed to request IPI %s on node %d\n",
-                              name, node);
+       virq = irq_create_mapping(iic_host, iic_ipi_to_irq(ipi));
+       if (virq == NO_IRQ) {
+               printk(KERN_ERR
+                      "iic: failed to map IPI %s\n", name);
+               return;
        }
+       if (request_irq(virq, iic_ipi_action, IRQF_DISABLED, name,
+                       (void *)(long)ipi))
+               printk(KERN_ERR
+                      "iic: failed to request IPI %s\n", name);
 }
 
 void iic_request_IPIs(void)
@@ -193,16 +228,24 @@ void iic_request_IPIs(void)
 
 static int iic_host_match(struct irq_host *h, struct device_node *node)
 {
-       return h->host_data != NULL && node == h->host_data;
+       return device_is_compatible(node,
+                                   "IBM,CBEA-Internal-Interrupt-Controller");
 }
 
 static int iic_host_map(struct irq_host *h, unsigned int virq,
                        irq_hw_number_t hw)
 {
-       if (hw < IIC_IRQ_IPI0)
-               set_irq_chip_and_handler(virq, &iic_chip, handle_fasteoi_irq);
-       else
+       switch (hw & IIC_IRQ_TYPE_MASK) {
+       case IIC_IRQ_TYPE_IPI:
                set_irq_chip_and_handler(virq, &iic_chip, handle_percpu_irq);
+               break;
+       case IIC_IRQ_TYPE_IOEXC:
+               set_irq_chip_and_handler(virq, &iic_ioexc_chip,
+                                        handle_fasteoi_irq);
+               break;
+       default:
+               set_irq_chip_and_handler(virq, &iic_chip, handle_fasteoi_irq);
+       }
        return 0;
 }
 
@@ -211,11 +254,39 @@ static int iic_host_xlate(struct irq_host *h, struct device_node *ct,
                           irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 
 {
-       /* Currently, we don't translate anything. That needs to be fixed as
-        * we get better defined device-trees. iic interrupts have to be
-        * explicitely mapped by whoever needs them
-        */
-       return -ENODEV;
+       unsigned int node, ext, unit, class;
+       const u32 *val;
+
+       if (!device_is_compatible(ct,
+                                    "IBM,CBEA-Internal-Interrupt-Controller"))
+               return -ENODEV;
+       if (intsize != 1)
+               return -ENODEV;
+       val = get_property(ct, "#interrupt-cells", NULL);
+       if (val == NULL || *val != 1)
+               return -ENODEV;
+
+       node = intspec[0] >> 24;
+       ext = (intspec[0] >> 16) & 0xff;
+       class = (intspec[0] >> 8) & 0xff;
+       unit = intspec[0] & 0xff;
+
+       /* Check if node is in supported range */
+       if (node > 1)
+               return -EINVAL;
+
+       /* Build up interrupt number, special case for IO exceptions */
+       *out_hwirq = (node << IIC_IRQ_NODE_SHIFT);
+       if (unit == IIC_UNIT_IIC && class == 1)
+               *out_hwirq |= IIC_IRQ_TYPE_IOEXC | ext;
+       else
+               *out_hwirq |= IIC_IRQ_TYPE_NORMAL |
+                       (class << IIC_IRQ_CLASS_SHIFT) | unit;
+
+       /* Dummy flags, ignored by iic code */
+       *out_flags = IRQ_TYPE_EDGE_RISING;
+
+       return 0;
 }
 
 static struct irq_host_ops iic_host_ops = {
@@ -225,7 +296,7 @@ static struct irq_host_ops iic_host_ops = {
 };
 
 static void __init init_one_iic(unsigned int hw_cpu, unsigned long addr,
-                               struct irq_host *host)
+                               struct device_node *node)
 {
        /* XXX FIXME: should locate the linux CPU number from the HW cpu
         * number properly. We are lucky for now
@@ -237,19 +308,19 @@ static void __init init_one_iic(unsigned int hw_cpu, unsigned long addr,
 
        iic->target_id = ((hw_cpu & 2) << 3) | ((hw_cpu & 1) ? 0xf : 0xe);
        iic->eoi_stack[0] = 0xff;
-       iic->host = host;
+       iic->node = of_node_get(node);
        out_be64(&iic->regs->prio, 0);
 
-       printk(KERN_INFO "IIC for CPU %d at %lx mapped to %p, target id 0x%x\n",
-              hw_cpu, addr, iic->regs, iic->target_id);
+       printk(KERN_INFO "IIC for CPU %d target id 0x%x : %s\n",
+              hw_cpu, iic->target_id, node->full_name);
 }
 
 static int __init setup_iic(void)
 {
        struct device_node *dn;
        struct resource r0, r1;
-       struct irq_host *host;
-       int found = 0;
+       unsigned int node, cascade, found = 0;
+       struct cbe_iic_regs *node_iic;
        const u32 *np;
 
        for (dn = NULL;
@@ -269,19 +340,33 @@ static int __init setup_iic(void)
                        of_node_put(dn);
                        return -ENODEV;
                }
-               host = NULL;
-               if (found < IIC_NODE_COUNT) {
-                       host = irq_alloc_host(IRQ_HOST_MAP_LINEAR,
-                                             IIC_SOURCE_COUNT,
-                                             &iic_host_ops,
-                                             IIC_IRQ_INVALID);
-                       iic_hosts[found] = host;
-                       BUG_ON(iic_hosts[found] == NULL);
-                       iic_hosts[found]->host_data = of_node_get(dn);
-                       found++;
-               }
-               init_one_iic(np[0], r0.start, host);
-               init_one_iic(np[1], r1.start, host);
+               found++;
+               init_one_iic(np[0], r0.start, dn);
+               init_one_iic(np[1], r1.start, dn);
+
+               /* Setup cascade for IO exceptions. XXX cleanup tricks to get
+                * node vs CPU etc...
+                * Note that we configure the IIC_IRR here with a hard coded
+                * priority of 1. We might want to improve that later.
+                */
+               node = np[0] >> 1;
+               node_iic = cbe_get_cpu_iic_regs(np[0]);
+               cascade = node << IIC_IRQ_NODE_SHIFT;
+               cascade |= 1 << IIC_IRQ_CLASS_SHIFT;
+               cascade |= IIC_UNIT_IIC;
+               cascade = irq_create_mapping(iic_host, cascade);
+               if (cascade == NO_IRQ)
+                       continue;
+               set_irq_data(cascade, node_iic);
+               set_irq_chained_handler(cascade , iic_ioexc_cascade);
+               out_be64(&node_iic->iic_ir,
+                        (1 << 12)              /* priority */ |
+                        (node << 4)            /* dest node */ |
+                        IIC_UNIT_THREAD_0      /* route them to thread 0 */);
+               /* Flush pending (make sure it triggers if there is
+                * anything pending
+                */
+               out_be64(&node_iic->iic_is, 0xfffffffffffffffful);
        }
 
        if (found)
@@ -292,6 +377,12 @@ static int __init setup_iic(void)
 
 void __init iic_init_IRQ(void)
 {
+       /* Setup an irq host data structure */
+       iic_host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, IIC_SOURCE_COUNT,
+                                 &iic_host_ops, IIC_IRQ_INVALID);
+       BUG_ON(iic_host == NULL);
+       irq_set_default_host(iic_host);
+
        /* Discover and initialize iics */
        if (setup_iic() < 0)
                panic("IIC: Failed to initialize !\n");
index 5560a92..9ba1d3c 100644 (file)
@@ -2,48 +2,76 @@
 #define ASM_CELL_PIC_H
 #ifdef __KERNEL__
 /*
- * Mapping of IIC pending bits into per-node
- * interrupt numbers.
+ * Mapping of IIC pending bits into per-node interrupt numbers.
  *
- * IRQ     FF CC SS PP   FF CC SS PP   Description
+ * Interrupt numbers are in the range 0...0x1ff where the top bit
+ * (0x100) represent the source node. Only 2 nodes are supported with
+ * the current code though it's trivial to extend that if necessary using
+ * higher level bits
  *
- * 00-3f   80 02 +0 00 - 80 02 +0 3f   South Bridge
- * 00-3f   80 02 +b 00 - 80 02 +b 3f   South Bridge
- * 41-4a   80 00 +1 ** - 80 00 +a **   SPU Class 0
- * 51-5a   80 01 +1 ** - 80 01 +a **   SPU Class 1
- * 61-6a   80 02 +1 ** - 80 02 +a **   SPU Class 2
- * 70-7f   C0 ** ** 00 - C0 ** ** 0f   IPI
+ * The bottom 8 bits are split into 2 type bits and 6 data bits that
+ * depend on the type:
  *
- *    F flags
- *    C class
- *    S source
- *    P Priority
- *    + node number
- *    * don't care
+ * 00 (0x00 | data) : normal interrupt. data is (class << 4) | source
+ * 01 (0x40 | data) : IO exception. data is the exception number as
+ *                    defined by bit numbers in IIC_SR
+ * 10 (0x80 | data) : IPI. data is the IPI number (obtained from the priority)
+ *                    and node is always 0 (IPIs are per-cpu, their source is
+ *                    not relevant)
+ * 11 (0xc0 | data) : reserved
  *
- * A node consists of a Cell Broadband Engine and an optional
- * south bridge device providing a maximum of 64 IRQs.
- * The south bridge may be connected to either IOIF0
- * or IOIF1.
- * Each SPE is represented as three IRQ lines, one per
- * interrupt class.
- * 16 IRQ numbers are reserved for inter processor
- * interruptions, although these are only used in the
- * range of the first node.
+ * In addition, interrupt number 0x80000000 is defined as always invalid
+ * (that is the node field is expected to never extend to move than 23 bits)
  *
- * This scheme needs 128 IRQ numbers per BIF node ID,
- * which means that with the total of 512 lines
- * available, we can have a maximum of four nodes.
  */
 
 enum {
-       IIC_IRQ_INVALID         = 0xff,
-       IIC_IRQ_MAX             = 0x3f,
-       IIC_IRQ_EXT_IOIF0       = 0x20,
-       IIC_IRQ_EXT_IOIF1       = 0x2b,
-       IIC_IRQ_IPI0            = 0x40,
-       IIC_NUM_IPIS            = 0x10, /* IRQs reserved for IPI */
-       IIC_SOURCE_COUNT        = 0x50,
+       IIC_IRQ_INVALID         = 0x80000000u,
+       IIC_IRQ_NODE_MASK       = 0x100,
+       IIC_IRQ_NODE_SHIFT      = 8,
+       IIC_IRQ_MAX             = 0x1ff,
+       IIC_IRQ_TYPE_MASK       = 0xc0,
+       IIC_IRQ_TYPE_NORMAL     = 0x00,
+       IIC_IRQ_TYPE_IOEXC      = 0x40,
+       IIC_IRQ_TYPE_IPI        = 0x80,
+       IIC_IRQ_CLASS_SHIFT     = 4,
+       IIC_IRQ_CLASS_0         = 0x00,
+       IIC_IRQ_CLASS_1         = 0x10,
+       IIC_IRQ_CLASS_2         = 0x20,
+       IIC_SOURCE_COUNT        = 0x200,
+
+       /* Here are defined the various source/dest units. Avoid using those
+        * definitions if you can, they are mostly here for reference
+        */
+       IIC_UNIT_SPU_0          = 0x4,
+       IIC_UNIT_SPU_1          = 0x7,
+       IIC_UNIT_SPU_2          = 0x3,
+       IIC_UNIT_SPU_3          = 0x8,
+       IIC_UNIT_SPU_4          = 0x2,
+       IIC_UNIT_SPU_5          = 0x9,
+       IIC_UNIT_SPU_6          = 0x1,
+       IIC_UNIT_SPU_7          = 0xa,
+       IIC_UNIT_IOC_0          = 0x0,
+       IIC_UNIT_IOC_1          = 0xb,
+       IIC_UNIT_THREAD_0       = 0xe, /* target only */
+       IIC_UNIT_THREAD_1       = 0xf, /* target only */
+       IIC_UNIT_IIC            = 0xe, /* source only (IO exceptions) */
+
+       /* Base numbers for the external interrupts */
+       IIC_IRQ_EXT_IOIF0       =
+               IIC_IRQ_TYPE_NORMAL | IIC_IRQ_CLASS_2 | IIC_UNIT_IOC_0,
+       IIC_IRQ_EXT_IOIF1       =
+               IIC_IRQ_TYPE_NORMAL | IIC_IRQ_CLASS_2 | IIC_UNIT_IOC_1,
+
+       /* Base numbers for the IIC_ISR interrupts */
+       IIC_IRQ_IOEX_TMI        = IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 63,
+       IIC_IRQ_IOEX_PMI        = IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 62,
+       IIC_IRQ_IOEX_ATI        = IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 61,
+       IIC_IRQ_IOEX_MATBFI     = IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 60,
+       IIC_IRQ_IOEX_ELDI       = IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 59,
+
+       /* Which bits in IIC_ISR are edge sensitive */
+       IIC_ISR_EDGE_MASK       = 0x4ul,
 };
 
 extern void iic_init_IRQ(void);
@@ -52,7 +80,6 @@ extern void iic_request_IPIs(void);
 extern void iic_setup_cpu(void);
 
 extern u8 iic_get_target_id(int cpu);
-extern struct irq_host *iic_get_irq_host(int node);
 
 extern void spider_init_IRQ(void);
 
index 742a032..608b1eb 100644 (file)
@@ -243,7 +243,6 @@ static unsigned int __init spider_find_cascade_and_node(struct spider_pic *pic)
        const u32 *imap, *tmp;
        int imaplen, intsize, unit;
        struct device_node *iic;
-       struct irq_host *iic_host;
 
 #if 0 /* Enable that when we have a way to retreive the node as well */
        /* First, we check wether we have a real "interrupts" in the device
@@ -289,11 +288,11 @@ static unsigned int __init spider_find_cascade_and_node(struct spider_pic *pic)
         * the iic host from the iic OF node, but that way I'm still compatible
         * with really really old old firmwares for which we don't have a node
         */
-       iic_host = iic_get_irq_host(pic->node_id);
-       if (iic_host == NULL)
-               return NO_IRQ;
        /* Manufacture an IIC interrupt number of class 2 */
-       virq = irq_create_mapping(iic_host, 0x20 | unit);
+       virq = irq_create_mapping(NULL,
+                                 (pic->node_id << IIC_IRQ_NODE_SHIFT) |
+                                 (2 << IIC_IRQ_CLASS_SHIFT) |
+                                 unit);
        if (virq == NO_IRQ)
                printk(KERN_ERR "spider_pic: failed to map cascade !");
        return virq;
index 0f5c8eb..f786803 100644 (file)
@@ -568,24 +568,23 @@ static void spu_unmap(struct spu *spu)
 /* This function shall be abstracted for HV platforms */
 static int __init spu_map_interrupts(struct spu *spu, struct device_node *np)
 {
-       struct irq_host *host;
        unsigned int isrc;
        const u32 *tmp;
 
-       host = iic_get_irq_host(spu->node);
-       if (host == NULL)
-               return -ENODEV;
-
-       /* Get the interrupt source from the device-tree */
+       /* Get the interrupt source unit from the device-tree */
        tmp = get_property(np, "isrc", NULL);
        if (!tmp)
                return -ENODEV;
-       spu->isrc = isrc = tmp[0];
+       isrc = tmp[0];
+
+       /* Add the node number */
+       isrc |= spu->node << IIC_IRQ_NODE_SHIFT;
+       spu->isrc = isrc;
 
        /* Now map interrupts of all 3 classes */
-       spu->irqs[0] = irq_create_mapping(host, 0x00 | isrc);
-       spu->irqs[1] = irq_create_mapping(host, 0x10 | isrc);
-       spu->irqs[2] = irq_create_mapping(host, 0x20 | isrc);
+       spu->irqs[0] = irq_create_mapping(NULL, IIC_IRQ_CLASS_0 | isrc);
+       spu->irqs[1] = irq_create_mapping(NULL, IIC_IRQ_CLASS_1 | isrc);
+       spu->irqs[2] = irq_create_mapping(NULL, IIC_IRQ_CLASS_2 | isrc);
 
        /* Right now, we only fail if class 2 failed */
        return spu->irqs[2] == NO_IRQ ? -EINVAL : 0;
index 3eb1206..4aa165e 100644 (file)
@@ -262,14 +262,6 @@ void __init iSeries_pci_final_fixup(void)
        mf_display_src(0xC9000200);
 }
 
-void pcibios_fixup_bus(struct pci_bus *PciBus)
-{
-}
-
-void pcibios_fixup_resources(struct pci_dev *pdev)
-{
-}
-
 /*
  * Look down the chain to find the matching Device Device
  */
index 7f19530..a0ff7ba 100644 (file)
@@ -649,15 +649,21 @@ static void iseries_dedicated_idle(void)
 void __init iSeries_init_IRQ(void) { }
 #endif
 
+/*
+ * iSeries has no legacy IO, anything calling this function has to
+ * fail or bad things will happen
+ */
+static int iseries_check_legacy_ioport(unsigned int baseport)
+{
+       return -ENODEV;
+}
+
 static int __init iseries_probe(void)
 {
        unsigned long root = of_get_flat_dt_root();
        if (!of_flat_dt_is_compatible(root, "IBM,iSeries"))
                return 0;
 
-       powerpc_firmware_features |= FW_FEATURE_ISERIES;
-       powerpc_firmware_features |= FW_FEATURE_LPAR;
-
        hpte_init_iSeries();
 
        return 1;
@@ -680,6 +686,7 @@ define_machine(iseries) {
        .calibrate_decr = generic_calibrate_decr,
        .progress       = iSeries_progress,
        .probe          = iseries_probe,
+       .check_legacy_ioport    = iseries_check_legacy_ioport,
        /* XXX Implement enable_pmcs for iSeries */
 };
 
@@ -687,6 +694,9 @@ void * __init iSeries_early_setup(void)
 {
        unsigned long phys_mem_size;
 
+       powerpc_firmware_features |= FW_FEATURE_ISERIES;
+       powerpc_firmware_features |= FW_FEATURE_LPAR;
+
        iSeries_fixup_klimit();
 
        /*
index ce1a235..379db05 100644 (file)
@@ -111,8 +111,6 @@ void udbg_scc_init(int force_scc)
        pmac_call_feature(PMAC_FTR_SCC_ENABLE, ch,
                          PMAC_SCC_ASYNC | PMAC_SCC_FLAG_XMON, 1);
 
-
-       /* Setup for 57600 8N1 */
        if (ch == ch_a)
                addr += 0x20;
        sccc = ioremap(addr & PAGE_MASK, PAGE_SIZE) ;
@@ -125,9 +123,21 @@ void udbg_scc_init(int force_scc)
                x = in_8(sccc);
        out_8(sccc, 0x09);              /* reset A or B side */
        out_8(sccc, 0xc0);
+
+       /* If SCC was the OF output port, read the BRG value, else
+        * Setup for 57600 8N1
+        */
+       if (ch_def != NULL) {
+               out_8(sccc, 13);
+               scc_inittab[1] = in_8(sccc);
+               out_8(sccc, 12);
+               scc_inittab[3] = in_8(sccc);
+       }
+
        for (i = 0; i < sizeof(scc_inittab); ++i)
                out_8(sccc, scc_inittab[i]);
 
+
        udbg_putc = udbg_scc_putc;
        udbg_getc = udbg_scc_getc;
        udbg_getc_poll = udbg_scc_getc_poll;
index 43dbf73..f82b13e 100644 (file)
@@ -180,7 +180,7 @@ static void __init pseries_mpic_init_IRQ(void)
 
        cascade_irq = irq_of_parse_and_map(cascade, 0);
        if (cascade == NO_IRQ) {
-               printk(KERN_ERR "xics: failed to map cascade interrupt");
+               printk(KERN_ERR "mpic: failed to map cascade interrupt");
                return;
        }
 
index f15f4d7..91f052d 100644 (file)
@@ -12,6 +12,7 @@ obj-$(CONFIG_MMIO_NVRAM)      += mmio_nvram.o
 obj-$(CONFIG_FSL_SOC)          += fsl_soc.o
 obj-$(CONFIG_PPC_TODC)         += todc.o
 obj-$(CONFIG_TSI108_BRIDGE)    += tsi108_pci.o tsi108_dev.o
+obj-$(CONFIG_QUICC_ENGINE)     += qe_lib/
 
 ifeq ($(CONFIG_PPC_MERGE),y)
 obj-$(CONFIG_PPC_I8259)                += i8259.o
index 5175299..28b0189 100644 (file)
@@ -147,7 +147,7 @@ static struct irq_chip cpm2_pic = {
        .end = cpm2_end_irq,
 };
 
-int cpm2_get_irq(struct pt_regs *regs)
+unsigned int cpm2_get_irq(struct pt_regs *regs)
 {
        int irq;
        unsigned long bits;
index d63e45d..3c513e5 100644 (file)
@@ -3,7 +3,7 @@
 
 extern intctl_cpm2_t *cpm2_intctl;
 
-extern int cpm2_get_irq(struct pt_regs *regs);
+extern unsigned int cpm2_get_irq(struct pt_regs *regs);
 
 extern void cpm2_pic_init(struct device_node*);
 
index 022ed27..7d759f1 100644 (file)
@@ -37,6 +37,7 @@
 #include <asm/cpm2.h>
 
 extern void init_fcc_ioports(struct fs_platform_info*);
+extern void init_scc_ioports(struct fs_uart_platform_info*);
 static phys_addr_t immrbase = -1;
 
 phys_addr_t get_immrbase(void)
@@ -566,7 +567,7 @@ static int __init fs_enet_of_init(void)
                struct resource r[4];
                struct device_node *phy, *mdio;
                struct fs_platform_info fs_enet_data;
-               const unsigned int *id, *phy_addr;
+               const unsigned int *id, *phy_addr, phy_irq;
                const void *mac_addr;
                const phandle *ph;
                const char *model;
@@ -588,6 +589,7 @@ static int __init fs_enet_of_init(void)
                if (ret)
                        goto err;
                r[2].name = fcc_regs_c;
+               fs_enet_data.fcc_regs_c = r[2].start;
 
                r[3].start = r[3].end = irq_of_parse_and_map(np, 0);
                r[3].flags = IORESOURCE_IRQ;
@@ -620,6 +622,8 @@ static int __init fs_enet_of_init(void)
                phy_addr = get_property(phy, "reg", NULL);
                fs_enet_data.phy_addr = *phy_addr;
 
+               phy_irq = get_property(phy, "interrupts", NULL);
+
                id = get_property(np, "device-id", NULL);
                fs_enet_data.fs_no = *id;
                strcpy(fs_enet_data.fs_type, model);
@@ -637,6 +641,7 @@ static int __init fs_enet_of_init(void)
 
                if (strstr(model, "FCC")) {
                        int fcc_index = *id - 1;
+                       unsigned char* mdio_bb_prop;
 
                        fs_enet_data.dpram_offset = (u32)cpm_dpram_addr(0);
                        fs_enet_data.rx_ring = 32;
@@ -652,14 +657,57 @@ static int __init fs_enet_of_init(void)
                                                        (u32)res.start, fs_enet_data.phy_addr);
                        fs_enet_data.bus_id = (char*)&bus_id[(*id)];
                        fs_enet_data.init_ioports = init_fcc_ioports;
-               }
 
-               of_node_put(phy);
-               of_node_put(mdio);
+                       mdio_bb_prop = get_property(phy, "bitbang", NULL);
+                       if (mdio_bb_prop) {
+                               struct platform_device *fs_enet_mdio_bb_dev;
+                               struct fs_mii_bb_platform_info fs_enet_mdio_bb_data;
+
+                               fs_enet_mdio_bb_dev =
+                                       platform_device_register_simple("fsl-bb-mdio",
+                                                       i, NULL, 0);
+                               memset(&fs_enet_mdio_bb_data, 0,
+                                               sizeof(struct fs_mii_bb_platform_info));
+                               fs_enet_mdio_bb_data.mdio_dat.bit =
+                                       mdio_bb_prop[0];
+                               fs_enet_mdio_bb_data.mdio_dir.bit =
+                                       mdio_bb_prop[1];
+                               fs_enet_mdio_bb_data.mdc_dat.bit =
+                                       mdio_bb_prop[2];
+                               fs_enet_mdio_bb_data.mdio_port =
+                                       mdio_bb_prop[3];
+                               fs_enet_mdio_bb_data.mdc_port =
+                                       mdio_bb_prop[4];
+                               fs_enet_mdio_bb_data.delay =
+                                       mdio_bb_prop[5];
+
+                               fs_enet_mdio_bb_data.irq[0] = phy_irq[0];
+                               fs_enet_mdio_bb_data.irq[1] = -1;
+                               fs_enet_mdio_bb_data.irq[2] = -1;
+                               fs_enet_mdio_bb_data.irq[3] = phy_irq[0];
+                               fs_enet_mdio_bb_data.irq[31] = -1;
+
+                               fs_enet_mdio_bb_data.mdio_dat.offset =
+                                       (u32)&cpm2_immr->im_ioport.iop_pdatc;
+                               fs_enet_mdio_bb_data.mdio_dir.offset =
+                                       (u32)&cpm2_immr->im_ioport.iop_pdirc;
+                               fs_enet_mdio_bb_data.mdc_dat.offset =
+                                       (u32)&cpm2_immr->im_ioport.iop_pdatc;
+
+                               ret = platform_device_add_data(
+                                               fs_enet_mdio_bb_dev,
+                                               &fs_enet_mdio_bb_data,
+                                               sizeof(struct fs_mii_bb_platform_info));
+                               if (ret)
+                                       goto unreg;
+                       }
+                       
+                       of_node_put(phy);
+                       of_node_put(mdio);
 
-               ret = platform_device_add_data(fs_enet_dev, &fs_enet_data,
-                                            sizeof(struct
-                                                   fs_platform_info));
+                       ret = platform_device_add_data(fs_enet_dev, &fs_enet_data,
+                                                    sizeof(struct
+                                                           fs_platform_info));
                if (ret)
                        goto unreg;
        }
diff --git a/arch/powerpc/sysdev/qe_lib/Kconfig b/arch/powerpc/sysdev/qe_lib/Kconfig
new file mode 100644 (file)
index 0000000..a725e80
--- /dev/null
@@ -0,0 +1,30 @@
+#
+# QE Communication options
+#
+
+menu "QE Options"
+       depends on QUICC_ENGINE
+
+config UCC_SLOW
+       bool "UCC Slow Protocols Support"
+       default n
+       select UCC
+       help
+         This option provides qe_lib support to UCC slow
+         protocols: UART, BISYNC, QMC
+
+config UCC_FAST
+       bool "UCC Fast Protocols Support"
+       default n
+       select UCC
+       select UCC_SLOW
+       help
+         This option provides qe_lib support to UCC fast
+         protocols: HDLC, Ethernet, ATM, transparent
+
+config UCC
+       bool
+       default y if UCC_FAST || UCC_SLOW
+
+endmenu
+
diff --git a/arch/powerpc/sysdev/qe_lib/Makefile b/arch/powerpc/sysdev/qe_lib/Makefile
new file mode 100644 (file)
index 0000000..874fe1a
--- /dev/null
@@ -0,0 +1,8 @@
+#
+# Makefile for the linux ppc-specific parts of QE
+#
+obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_ic.o qe_io.o
+
+obj-$(CONFIG_UCC)      += ucc.o
+obj-$(CONFIG_UCC_SLOW) += ucc_slow.o
+obj-$(CONFIG_UCC_FAST) += ucc_fast.o
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
new file mode 100644 (file)
index 0000000..2bae632
--- /dev/null
@@ -0,0 +1,353 @@
+/*
+ * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
+ *
+ * Authors:    Shlomi Gridish <gridish@freescale.com>
+ *             Li Yang <leoli@freescale.com>
+ * Based on cpm2_common.c from Dan Malek (dmalek@jlc.net)
+ *
+ * Description:
+ * General Purpose functions for the global management of the
+ * QUICC Engine (QE).
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/interrupt.h>
+#include <linux/bootmem.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/ioport.h>
+#include <asm/irq.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/immap_qe.h>
+#include <asm/qe.h>
+#include <asm/prom.h>
+#include <asm/rheap.h>
+
+static void qe_snums_init(void);
+static void qe_muram_init(void);
+static int qe_sdma_init(void);
+
+static DEFINE_SPINLOCK(qe_lock);
+
+/* QE snum state */
+enum qe_snum_state {
+       QE_SNUM_STATE_USED,
+       QE_SNUM_STATE_FREE
+};
+
+/* QE snum */
+struct qe_snum {
+       u8 num;
+       enum qe_snum_state state;
+};
+
+/* We allocate this here because it is used almost exclusively for
+ * the communication processor devices.
+ */
+struct qe_immap *qe_immr = NULL;
+EXPORT_SYMBOL(qe_immr);
+
+static struct qe_snum snums[QE_NUM_OF_SNUM];   /* Dynamically allocated SNUMs */
+
+static phys_addr_t qebase = -1;
+
+phys_addr_t get_qe_base(void)
+{
+       struct device_node *qe;
+
+       if (qebase != -1)
+               return qebase;
+
+       qe = of_find_node_by_type(NULL, "qe");
+       if (qe) {
+               unsigned int size;
+               const void *prop = get_property(qe, "reg", &size);
+               qebase = of_translate_address(qe, prop);
+               of_node_put(qe);
+       };
+
+       return qebase;
+}
+
+EXPORT_SYMBOL(get_qe_base);
+
+void qe_reset(void)
+{
+       if (qe_immr == NULL)
+               qe_immr = ioremap(get_qe_base(), QE_IMMAP_SIZE);
+
+       qe_snums_init();
+
+       qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
+                    QE_CR_PROTOCOL_UNSPECIFIED, 0);
+
+       /* Reclaim the MURAM memory for our use. */
+       qe_muram_init();
+
+       if (qe_sdma_init())
+               panic("sdma init failed!");
+}
+
+int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
+{
+       unsigned long flags;
+       u8 mcn_shift = 0, dev_shift = 0;
+
+       spin_lock_irqsave(&qe_lock, flags);
+       if (cmd == QE_RESET) {
+               out_be32(&qe_immr->cp.cecr, (u32) (cmd | QE_CR_FLG));
+       } else {
+               if (cmd == QE_ASSIGN_PAGE) {
+                       /* Here device is the SNUM, not sub-block */
+                       dev_shift = QE_CR_SNUM_SHIFT;
+               } else if (cmd == QE_ASSIGN_RISC) {
+                       /* Here device is the SNUM, and mcnProtocol is
+                        * e_QeCmdRiscAssignment value */
+                       dev_shift = QE_CR_SNUM_SHIFT;
+                       mcn_shift = QE_CR_MCN_RISC_ASSIGN_SHIFT;
+               } else {
+                       if (device == QE_CR_SUBBLOCK_USB)
+                               mcn_shift = QE_CR_MCN_USB_SHIFT;
+                       else
+                               mcn_shift = QE_CR_MCN_NORMAL_SHIFT;
+               }
+
+               out_be32(&qe_immr->cp.cecdr,
+                        immrbar_virt_to_phys((void *)cmd_input));
+               out_be32(&qe_immr->cp.cecr,
+                        (cmd | QE_CR_FLG | ((u32) device << dev_shift) | (u32)
+                         mcn_protocol << mcn_shift));
+       }
+
+       /* wait for the QE_CR_FLG to clear */
+       while(in_be32(&qe_immr->cp.cecr) & QE_CR_FLG)
+               cpu_relax();
+       spin_unlock_irqrestore(&qe_lock, flags);
+
+       return 0;
+}
+EXPORT_SYMBOL(qe_issue_cmd);
+
+/* Set a baud rate generator. This needs lots of work. There are
+ * 16 BRGs, which can be connected to the QE channels or output
+ * as clocks. The BRGs are in two different block of internal
+ * memory mapped space.
+ * The baud rate clock is the system clock divided by something.
+ * It was set up long ago during the initial boot phase and is
+ * is given to us.
+ * Baud rate clocks are zero-based in the driver code (as that maps
+ * to port numbers). Documentation uses 1-based numbering.
+ */
+static unsigned int brg_clk = 0;
+
+unsigned int get_brg_clk(void)
+{
+       struct device_node *qe;
+       if (brg_clk)
+               return brg_clk;
+
+       qe = of_find_node_by_type(NULL, "qe");
+       if (qe) {
+               unsigned int size;
+               const u32 *prop = get_property(qe, "brg-frequency", &size);
+               brg_clk = *prop;
+               of_node_put(qe);
+       };
+       return brg_clk;
+}
+
+/* This function is used by UARTS, or anything else that uses a 16x
+ * oversampled clock.
+ */
+void qe_setbrg(u32 brg, u32 rate)
+{
+       volatile u32 *bp;
+       u32 divisor, tempval;
+       int div16 = 0;
+
+       bp = &qe_immr->brg.brgc1;
+       bp += brg;
+
+       divisor = (get_brg_clk() / rate);
+       if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
+               div16 = 1;
+               divisor /= 16;
+       }
+
+       tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE;
+       if (div16)
+               tempval |= QE_BRGC_DIV16;
+
+       out_be32(bp, tempval);
+}
+
+/* Initialize SNUMs (thread serial numbers) according to
+ * QE Module Control chapter, SNUM table
+ */
+static void qe_snums_init(void)
+{
+       int i;
+       static const u8 snum_init[] = {
+               0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
+               0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
+               0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
+               0xD8, 0xD9, 0xE8, 0xE9,
+       };
+
+       for (i = 0; i < QE_NUM_OF_SNUM; i++) {
+               snums[i].num = snum_init[i];
+               snums[i].state = QE_SNUM_STATE_FREE;
+       }
+}
+
+int qe_get_snum(void)
+{
+       unsigned long flags;
+       int snum = -EBUSY;
+       int i;
+
+       spin_lock_irqsave(&qe_lock, flags);
+       for (i = 0; i < QE_NUM_OF_SNUM; i++) {
+               if (snums[i].state == QE_SNUM_STATE_FREE) {
+                       snums[i].state = QE_SNUM_STATE_USED;
+                       snum = snums[i].num;
+                       break;
+               }
+       }
+       spin_unlock_irqrestore(&qe_lock, flags);
+
+       return snum;
+}
+EXPORT_SYMBOL(qe_get_snum);
+
+void qe_put_snum(u8 snum)
+{
+       int i;
+
+       for (i = 0; i < QE_NUM_OF_SNUM; i++) {
+               if (snums[i].num == snum) {
+                       snums[i].state = QE_SNUM_STATE_FREE;
+                       break;
+               }
+       }
+}
+EXPORT_SYMBOL(qe_put_snum);
+
+static int qe_sdma_init(void)
+{
+       struct sdma *sdma = &qe_immr->sdma;
+       u32 sdma_buf_offset;
+
+       if (!sdma)
+               return -ENODEV;
+
+       /* allocate 2 internal temporary buffers (512 bytes size each) for
+        * the SDMA */
+       sdma_buf_offset = qe_muram_alloc(512 * 2, 64);
+       if (IS_MURAM_ERR(sdma_buf_offset))
+               return -ENOMEM;
+
+       out_be32(&sdma->sdebcr, sdma_buf_offset & QE_SDEBCR_BA_MASK);
+       out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK | (0x1 >>
+                                       QE_SDMR_CEN_SHIFT)));
+
+       return 0;
+}
+
+/*
+ * muram_alloc / muram_free bits.
+ */
+static DEFINE_SPINLOCK(qe_muram_lock);
+
+/* 16 blocks should be enough to satisfy all requests
+ * until the memory subsystem goes up... */
+static rh_block_t qe_boot_muram_rh_block[16];
+static rh_info_t qe_muram_info;
+
+static void qe_muram_init(void)
+{
+       struct device_node *np;
+       u32 address;
+       u64 size;
+       unsigned int flags;
+
+       /* initialize the info header */
+       rh_init(&qe_muram_info, 1,
+               sizeof(qe_boot_muram_rh_block) /
+               sizeof(qe_boot_muram_rh_block[0]), qe_boot_muram_rh_block);
+
+       /* Attach the usable muram area */
+       /* XXX: This is a subset of the available muram. It
+        * varies with the processor and the microcode patches activated.
+        */
+       if ((np = of_find_node_by_name(NULL, "data-only")) != NULL) {
+               address = *of_get_address(np, 0, &size, &flags);
+               of_node_put(np);
+               rh_attach_region(&qe_muram_info,
+                       (void *)address, (int)size);
+       }
+}
+
+/* This function returns an index into the MURAM area.
+ */
+u32 qe_muram_alloc(u32 size, u32 align)
+{
+       void *start;
+       unsigned long flags;
+
+       spin_lock_irqsave(&qe_muram_lock, flags);
+       start = rh_alloc_align(&qe_muram_info, size, align, "QE");
+       spin_unlock_irqrestore(&qe_muram_lock, flags);
+
+       return (u32) start;
+}
+EXPORT_SYMBOL(qe_muram_alloc);
+
+int qe_muram_free(u32 offset)
+{
+       int ret;
+       unsigned long flags;
+
+       spin_lock_irqsave(&qe_muram_lock, flags);
+       ret = rh_free(&qe_muram_info, (void *)offset);
+       spin_unlock_irqrestore(&qe_muram_lock, flags);
+
+       return ret;
+}
+EXPORT_SYMBOL(qe_muram_free);
+
+/* not sure if this is ever needed */
+u32 qe_muram_alloc_fixed(u32 offset, u32 size)
+{
+       void *start;
+       unsigned long flags;
+
+       spin_lock_irqsave(&qe_muram_lock, flags);
+       start = rh_alloc_fixed(&qe_muram_info, (void *)offset, size, "commproc");
+       spin_unlock_irqrestore(&qe_muram_lock, flags);
+
+       return (u32) start;
+}
+EXPORT_SYMBOL(qe_muram_alloc_fixed);
+
+void qe_muram_dump(void)
+{
+       rh_dump(&qe_muram_info);
+}
+EXPORT_SYMBOL(qe_muram_dump);
+
+void *qe_muram_addr(u32 offset)
+{
+       return (void *)&qe_immr->muram[offset];
+}
+EXPORT_SYMBOL(qe_muram_addr);
diff --git a/arch/powerpc/sysdev/qe_lib/qe_ic.c b/arch/powerpc/sysdev/qe_lib/qe_ic.c
new file mode 100644 (file)
index 0000000..c229d07
--- /dev/null
@@ -0,0 +1,555 @@
+/*
+ * arch/powerpc/sysdev/qe_lib/qe_ic.c
+ *
+ * Copyright (C) 2006 Freescale Semicondutor, Inc.  All rights reserved.
+ *
+ * Author: Li Yang <leoli@freescale.com>
+ * Based on code from Shlomi Gridish <gridish@freescale.com>
+ *
+ * QUICC ENGINE Interrupt Controller
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/reboot.h>
+#include <linux/slab.h>
+#include <linux/stddef.h>
+#include <linux/sched.h>
+#include <linux/signal.h>
+#include <linux/sysdev.h>
+#include <linux/device.h>
+#include <linux/bootmem.h>
+#include <linux/spinlock.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+#include <asm/prom.h>
+#include <asm/qe_ic.h>
+
+#include "qe_ic.h"
+
+static DEFINE_SPINLOCK(qe_ic_lock);
+
+static struct qe_ic_info qe_ic_info[] = {
+       [1] = {
+              .mask = 0x00008000,
+              .mask_reg = QEIC_CIMR,
+              .pri_code = 0,
+              .pri_reg = QEIC_CIPWCC,
+              },
+       [2] = {
+              .mask = 0x00004000,
+              .mask_reg = QEIC_CIMR,
+              .pri_code = 1,
+              .pri_reg = QEIC_CIPWCC,
+              },
+       [3] = {
+              .mask = 0x00002000,
+              .mask_reg = QEIC_CIMR,
+              .pri_code = 2,
+              .pri_reg = QEIC_CIPWCC,
+              },
+       [10] = {
+               .mask = 0x00000040,
+               .mask_reg = QEIC_CIMR,
+               .pri_code = 1,
+               .pri_reg = QEIC_CIPZCC,
+               },
+       [11] = {
+               .mask = 0x00000020,
+               .mask_reg = QEIC_CIMR,
+               .pri_code = 2,
+               .pri_reg = QEIC_CIPZCC,
+               },
+       [12] = {
+               .mask = 0x00000010,
+               .mask_reg = QEIC_CIMR,
+               .pri_code = 3,
+               .pri_reg = QEIC_CIPZCC,
+               },
+       [13] = {
+               .mask = 0x00000008,
+               .mask_reg = QEIC_CIMR,
+               .pri_code = 4,
+               .pri_reg = QEIC_CIPZCC,
+               },
+       [14] = {
+               .mask = 0x00000004,
+               .mask_reg = QEIC_CIMR,
+               .pri_code = 5,
+               .pri_reg = QEIC_CIPZCC,
+               },
+       [15] = {
+               .mask = 0x00000002,
+               .mask_reg = QEIC_CIMR,
+               .pri_code = 6,
+               .pri_reg = QEIC_CIPZCC,
+               },
+       [20] = {
+               .mask = 0x10000000,
+               .mask_reg = QEIC_CRIMR,
+               .pri_code = 3,
+               .pri_reg = QEIC_CIPRTA,
+               },
+       [25] = {
+               .mask = 0x00800000,
+               .mask_reg = QEIC_CRIMR,
+               .pri_code = 0,
+               .pri_reg = QEIC_CIPRTB,
+               },
+       [26] = {
+               .mask = 0x00400000,
+               .mask_reg = QEIC_CRIMR,
+               .pri_code = 1,
+               .pri_reg = QEIC_CIPRTB,
+               },
+       [27] = {
+               .mask = 0x00200000,
+               .mask_reg = QEIC_CRIMR,
+               .pri_code = 2,
+               .pri_reg = QEIC_CIPRTB,
+               },
+       [28] = {
+               .mask = 0x00100000,
+               .mask_reg = QEIC_CRIMR,
+               .pri_code = 3,
+               .pri_reg = QEIC_CIPRTB,
+               },
+       [32] = {
+               .mask = 0x80000000,
+               .mask_reg = QEIC_CIMR,
+               .pri_code = 0,
+               .pri_reg = QEIC_CIPXCC,
+               },
+       [33] = {
+               .mask = 0x40000000,
+               .mask_reg = QEIC_CIMR,
+               .pri_code = 1,
+               .pri_reg = QEIC_CIPXCC,
+               },
+       [34] = {
+               .mask = 0x20000000,
+               .mask_reg = QEIC_CIMR,
+               .pri_code = 2,
+               .pri_reg = QEIC_CIPXCC,
+               },
+       [35] = {
+               .mask = 0x10000000,
+               .mask_reg = QEIC_CIMR,
+               .pri_code = 3,
+               .pri_reg = QEIC_CIPXCC,
+               },
+       [36] = {
+               .mask = 0x08000000,
+               .mask_reg = QEIC_CIMR,
+               .pri_code = 4,
+               .pri_reg = QEIC_CIPXCC,
+               },
+       [40] = {
+               .mask = 0x00800000,
+               .mask_reg = QEIC_CIMR,
+               .pri_code = 0,
+               .pri_reg = QEIC_CIPYCC,
+               },
+       [41] = {
+               .mask = 0x00400000,
+               .mask_reg = QEIC_CIMR,
+               .pri_code = 1,
+               .pri_reg = QEIC_CIPYCC,
+               },
+       [42] = {
+               .mask = 0x00200000,
+               .mask_reg = QEIC_CIMR,
+               .pri_code = 2,
+               .pri_reg = QEIC_CIPYCC,
+               },
+       [43] = {
+               .mask = 0x00100000,
+               .mask_reg = QEIC_CIMR,
+               .pri_code = 3,
+               .pri_reg = QEIC_CIPYCC,
+               },
+};
+
+static inline u32 qe_ic_read(volatile __be32  __iomem * base, unsigned int reg)
+{
+       return in_be32(base + (reg >> 2));
+}
+
+static inline void qe_ic_write(volatile __be32  __iomem * base, unsigned int reg,
+                              u32 value)
+{
+       out_be32(base + (reg >> 2), value);
+}
+
+static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
+{
+       return irq_desc[virq].chip_data;
+}
+
+#define virq_to_hw(virq)       ((unsigned int)irq_map[virq].hwirq)
+
+static void qe_ic_unmask_irq(unsigned int virq)
+{
+       struct qe_ic *qe_ic = qe_ic_from_irq(virq);
+       unsigned int src = virq_to_hw(virq);
+       unsigned long flags;
+       u32 temp;
+
+       spin_lock_irqsave(&qe_ic_lock, flags);
+
+       temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
+       qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
+                   temp | qe_ic_info[src].mask);
+
+       spin_unlock_irqrestore(&qe_ic_lock, flags);
+}
+
+static void qe_ic_mask_irq(unsigned int virq)
+{
+       struct qe_ic *qe_ic = qe_ic_from_irq(virq);
+       unsigned int src = virq_to_hw(virq);
+       unsigned long flags;
+       u32 temp;
+
+       spin_lock_irqsave(&qe_ic_lock, flags);
+
+       temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
+       qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
+                   temp & ~qe_ic_info[src].mask);
+
+       spin_unlock_irqrestore(&qe_ic_lock, flags);
+}
+
+static void qe_ic_mask_irq_and_ack(unsigned int virq)
+{
+       struct qe_ic *qe_ic = qe_ic_from_irq(virq);
+       unsigned int src = virq_to_hw(virq);
+       unsigned long flags;
+       u32 temp;
+
+       spin_lock_irqsave(&qe_ic_lock, flags);
+
+       temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
+       qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
+                   temp & ~qe_ic_info[src].mask);
+
+       /* There is nothing to do for ack here, ack is handled in ISR */
+
+       spin_unlock_irqrestore(&qe_ic_lock, flags);
+}
+
+static struct irq_chip qe_ic_irq_chip = {
+       .typename = " QEIC  ",
+       .unmask = qe_ic_unmask_irq,
+       .mask = qe_ic_mask_irq,
+       .mask_ack = qe_ic_mask_irq_and_ack,
+};
+
+static int qe_ic_host_match(struct irq_host *h, struct device_node *node)
+{
+       struct qe_ic *qe_ic = h->host_data;
+
+       /* Exact match, unless qe_ic node is NULL */
+       return qe_ic->of_node == NULL || qe_ic->of_node == node;
+}
+
+static int qe_ic_host_map(struct irq_host *h, unsigned int virq,
+                         irq_hw_number_t hw)
+{
+       struct qe_ic *qe_ic = h->host_data;
+       struct irq_chip *chip;
+
+       if (qe_ic_info[hw].mask == 0) {
+               printk(KERN_ERR "Can't map reserved IRQ \n");
+               return -EINVAL;
+       }
+       /* Default chip */
+       chip = &qe_ic->hc_irq;
+
+       set_irq_chip_data(virq, qe_ic);
+       get_irq_desc(virq)->status |= IRQ_LEVEL;
+
+       set_irq_chip_and_handler(virq, chip, handle_level_irq);
+
+       return 0;
+}
+
+static int qe_ic_host_xlate(struct irq_host *h, struct device_node *ct,
+                           u32 * intspec, unsigned int intsize,
+                           irq_hw_number_t * out_hwirq,
+                           unsigned int *out_flags)
+{
+       *out_hwirq = intspec[0];
+       if (intsize > 1)
+               *out_flags = intspec[1];
+       else
+               *out_flags = IRQ_TYPE_NONE;
+       return 0;
+}
+
+static struct irq_host_ops qe_ic_host_ops = {
+       .match = qe_ic_host_match,
+       .map = qe_ic_host_map,
+       .xlate = qe_ic_host_xlate,
+};
+
+/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
+unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic, struct pt_regs *regs)
+{
+       int irq;
+
+       BUG_ON(qe_ic == NULL);
+
+       /* get the interrupt source vector. */
+       irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;
+
+       if (irq == 0)
+               return NO_IRQ;
+
+       return irq_linear_revmap(qe_ic->irqhost, irq);
+}
+
+/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
+unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic, struct pt_regs *regs)
+{
+       int irq;
+
+       BUG_ON(qe_ic == NULL);
+
+       /* get the interrupt source vector. */
+       irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;
+
+       if (irq == 0)
+               return NO_IRQ;
+
+       return irq_linear_revmap(qe_ic->irqhost, irq);
+}
+
+/* FIXME: We mask all the QE Low interrupts while handling.  We should
+ * let other interrupt come in, but BAD interrupts are generated */
+void fastcall qe_ic_cascade_low(unsigned int irq, struct irq_desc *desc,
+                               struct pt_regs *regs)
+{
+       struct qe_ic *qe_ic = desc->handler_data;
+       struct irq_chip *chip = irq_desc[irq].chip;
+
+       unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic, regs);
+
+       chip->mask_ack(irq);
+       if (cascade_irq != NO_IRQ)
+               generic_handle_irq(cascade_irq, regs);
+       chip->unmask(irq);
+}
+
+/* FIXME: We mask all the QE High interrupts while handling.  We should
+ * let other interrupt come in, but BAD interrupts are generated */
+void fastcall qe_ic_cascade_high(unsigned int irq, struct irq_desc *desc,
+                                struct pt_regs *regs)
+{
+       struct qe_ic *qe_ic = desc->handler_data;
+       struct irq_chip *chip = irq_desc[irq].chip;
+
+       unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic, regs);
+
+       chip->mask_ack(irq);
+       if (cascade_irq != NO_IRQ)
+               generic_handle_irq(cascade_irq, regs);
+       chip->unmask(irq);
+}
+
+void __init qe_ic_init(struct device_node *node, unsigned int flags)
+{
+       struct qe_ic *qe_ic;
+       struct resource res;
+       u32 temp = 0, ret, high_active = 0;
+
+       qe_ic = alloc_bootmem(sizeof(struct qe_ic));
+       if (qe_ic == NULL)
+               return;
+
+       memset(qe_ic, 0, sizeof(struct qe_ic));
+       qe_ic->of_node = node ? of_node_get(node) : NULL;
+
+       qe_ic->irqhost = irq_alloc_host(IRQ_HOST_MAP_LINEAR,
+                                       NR_QE_IC_INTS, &qe_ic_host_ops, 0);
+       if (qe_ic->irqhost == NULL) {
+               of_node_put(node);
+               return;
+       }
+
+       ret = of_address_to_resource(node, 0, &res);
+       if (ret)
+               return;
+
+       qe_ic->regs = ioremap(res.start, res.end - res.start + 1);
+
+       qe_ic->irqhost->host_data = qe_ic;
+       qe_ic->hc_irq = qe_ic_irq_chip;
+
+       qe_ic->virq_high = irq_of_parse_and_map(node, 0);
+       qe_ic->virq_low = irq_of_parse_and_map(node, 1);
+
+       if (qe_ic->virq_low == NO_IRQ) {
+               printk(KERN_ERR "Failed to map QE_IC low IRQ\n");
+               return;
+       }
+
+       /* default priority scheme is grouped. If spread mode is    */
+       /* required, configure cicr accordingly.                    */
+       if (flags & QE_IC_SPREADMODE_GRP_W)
+               temp |= CICR_GWCC;
+       if (flags & QE_IC_SPREADMODE_GRP_X)
+               temp |= CICR_GXCC;
+       if (flags & QE_IC_SPREADMODE_GRP_Y)
+               temp |= CICR_GYCC;
+       if (flags & QE_IC_SPREADMODE_GRP_Z)
+               temp |= CICR_GZCC;
+       if (flags & QE_IC_SPREADMODE_GRP_RISCA)
+               temp |= CICR_GRTA;
+       if (flags & QE_IC_SPREADMODE_GRP_RISCB)
+               temp |= CICR_GRTB;
+
+       /* choose destination signal for highest priority interrupt */
+       if (flags & QE_IC_HIGH_SIGNAL) {
+               temp |= (SIGNAL_HIGH << CICR_HPIT_SHIFT);
+               high_active = 1;
+       }
+
+       qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
+
+       set_irq_data(qe_ic->virq_low, qe_ic);
+       set_irq_chained_handler(qe_ic->virq_low, qe_ic_cascade_low);
+
+       if (qe_ic->virq_high != NO_IRQ) {
+               set_irq_data(qe_ic->virq_high, qe_ic);
+               set_irq_chained_handler(qe_ic->virq_high, qe_ic_cascade_high);
+       }
+
+       printk("QEIC (%d IRQ sources) at %p\n", NR_QE_IC_INTS, qe_ic->regs);
+}
+
+void qe_ic_set_highest_priority(unsigned int virq, int high)
+{
+       struct qe_ic *qe_ic = qe_ic_from_irq(virq);
+       unsigned int src = virq_to_hw(virq);
+       u32 temp = 0;
+
+       temp = qe_ic_read(qe_ic->regs, QEIC_CICR);
+
+       temp &= ~CICR_HP_MASK;
+       temp |= src << CICR_HP_SHIFT;
+
+       temp &= ~CICR_HPIT_MASK;
+       temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT;
+
+       qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
+}
+
+/* Set Priority level within its group, from 1 to 8 */
+int qe_ic_set_priority(unsigned int virq, unsigned int priority)
+{
+       struct qe_ic *qe_ic = qe_ic_from_irq(virq);
+       unsigned int src = virq_to_hw(virq);
+       u32 temp;
+
+       if (priority > 8 || priority == 0)
+               return -EINVAL;
+       if (src > 127)
+               return -EINVAL;
+       if (qe_ic_info[src].pri_reg == 0)
+               return -EINVAL;
+
+       temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg);
+
+       if (priority < 4) {
+               temp &= ~(0x7 << (32 - priority * 3));
+               temp |= qe_ic_info[src].pri_code << (32 - priority * 3);
+       } else {
+               temp &= ~(0x7 << (24 - priority * 3));
+               temp |= qe_ic_info[src].pri_code << (24 - priority * 3);
+       }
+
+       qe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp);
+
+       return 0;
+}
+
+/* Set a QE priority to use high irq, only priority 1~2 can use high irq */
+int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)
+{
+       struct qe_ic *qe_ic = qe_ic_from_irq(virq);
+       unsigned int src = virq_to_hw(virq);
+       u32 temp, control_reg = QEIC_CICNR, shift = 0;
+
+       if (priority > 2 || priority == 0)
+               return -EINVAL;
+
+       switch (qe_ic_info[src].pri_reg) {
+       case QEIC_CIPZCC:
+               shift = CICNR_ZCC1T_SHIFT;
+               break;
+       case QEIC_CIPWCC:
+               shift = CICNR_WCC1T_SHIFT;
+               break;
+       case QEIC_CIPYCC:
+               shift = CICNR_YCC1T_SHIFT;
+               break;
+       case QEIC_CIPXCC:
+               shift = CICNR_XCC1T_SHIFT;
+               break;
+       case QEIC_CIPRTA:
+               shift = CRICR_RTA1T_SHIFT;
+               control_reg = QEIC_CRICR;
+               break;
+       case QEIC_CIPRTB:
+               shift = CRICR_RTB1T_SHIFT;
+               control_reg = QEIC_CRICR;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       shift += (2 - priority) * 2;
+       temp = qe_ic_read(qe_ic->regs, control_reg);
+       temp &= ~(SIGNAL_MASK << shift);
+       temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift;
+       qe_ic_write(qe_ic->regs, control_reg, temp);
+
+       return 0;
+}
+
+static struct sysdev_class qe_ic_sysclass = {
+       set_kset_name("qe_ic"),
+};
+
+static struct sys_device device_qe_ic = {
+       .id = 0,
+       .cls = &qe_ic_sysclass,
+};
+
+static int __init init_qe_ic_sysfs(void)
+{
+       int rc;
+
+       printk(KERN_DEBUG "Registering qe_ic with sysfs...\n");
+
+       rc = sysdev_class_register(&qe_ic_sysclass);
+       if (rc) {
+               printk(KERN_ERR "Failed registering qe_ic sys class\n");
+               return -ENODEV;
+       }
+       rc = sysdev_register(&device_qe_ic);
+       if (rc) {
+               printk(KERN_ERR "Failed registering qe_ic sys device\n");
+               return -ENODEV;
+       }
+       return 0;
+}
+
+subsys_initcall(init_qe_ic_sysfs);
diff --git a/arch/powerpc/sysdev/qe_lib/qe_ic.h b/arch/powerpc/sysdev/qe_lib/qe_ic.h
new file mode 100644 (file)
index 0000000..9a631ad
--- /dev/null
@@ -0,0 +1,106 @@
+/*
+ * arch/powerpc/sysdev/qe_lib/qe_ic.h
+ *
+ * QUICC ENGINE Interrupt Controller Header
+ *
+ * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
+ *
+ * Author: Li Yang <leoli@freescale.com>
+ * Based on code from Shlomi Gridish <gridish@freescale.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef _POWERPC_SYSDEV_QE_IC_H
+#define _POWERPC_SYSDEV_QE_IC_H
+
+#include <asm/qe_ic.h>
+
+#define NR_QE_IC_INTS          64
+
+/* QE IC registers offset */
+#define QEIC_CICR              0x00
+#define QEIC_CIVEC             0x04
+#define QEIC_CRIPNR            0x08
+#define QEIC_CIPNR             0x0c
+#define QEIC_CIPXCC            0x10
+#define QEIC_CIPYCC            0x14
+#define QEIC_CIPWCC            0x18
+#define QEIC_CIPZCC            0x1c
+#define QEIC_CIMR              0x20
+#define QEIC_CRIMR             0x24
+#define QEIC_CICNR             0x28
+#define QEIC_CIPRTA            0x30
+#define QEIC_CIPRTB            0x34
+#define QEIC_CRICR             0x3c
+#define QEIC_CHIVEC            0x60
+
+/* Interrupt priority registers */
+#define CIPCC_SHIFT_PRI0       29
+#define CIPCC_SHIFT_PRI1       26
+#define CIPCC_SHIFT_PRI2       23
+#define CIPCC_SHIFT_PRI3       20
+#define CIPCC_SHIFT_PRI4       13
+#define CIPCC_SHIFT_PRI5       10
+#define CIPCC_SHIFT_PRI6       7
+#define CIPCC_SHIFT_PRI7       4
+
+/* CICR priority modes */
+#define CICR_GWCC              0x00040000
+#define CICR_GXCC              0x00020000
+#define CICR_GYCC              0x00010000
+#define CICR_GZCC              0x00080000
+#define CICR_GRTA              0x00200000
+#define CICR_GRTB              0x00400000
+#define CICR_HPIT_SHIFT                8
+#define CICR_HPIT_MASK         0x00000300
+#define CICR_HP_SHIFT          24
+#define CICR_HP_MASK           0x3f000000
+
+/* CICNR */
+#define CICNR_WCC1T_SHIFT      20
+#define CICNR_ZCC1T_SHIFT      28
+#define CICNR_YCC1T_SHIFT      12
+#define CICNR_XCC1T_SHIFT      4
+
+/* CRICR */
+#define CRICR_RTA1T_SHIFT      20
+#define CRICR_RTB1T_SHIFT      28
+
+/* Signal indicator */
+#define SIGNAL_MASK            3
+#define SIGNAL_HIGH            2
+#define SIGNAL_LOW             0
+
+struct qe_ic {
+       /* Control registers offset */
+       volatile u32 __iomem *regs;
+
+       /* The remapper for this QEIC */
+       struct irq_host *irqhost;
+
+       /* The "linux" controller struct */
+       struct irq_chip hc_irq;
+
+       /* The device node of the interrupt controller */
+       struct device_node *of_node;
+
+       /* VIRQ numbers of QE high/low irqs */
+       unsigned int virq_high;
+       unsigned int virq_low;
+};
+
+/*
+ * QE interrupt controller internal structure
+ */
+struct qe_ic_info {
+       u32     mask;     /* location of this source at the QIMR register. */
+       u32     mask_reg; /* Mask register offset */
+       u8      pri_code; /* for grouped interrupts sources - the interrupt
+                            code as appears at the group priority register */
+       u32     pri_reg;  /* Group priority register offset */
+};
+
+#endif /* _POWERPC_SYSDEV_QE_IC_H */
diff --git a/arch/powerpc/sysdev/qe_lib/qe_io.c b/arch/powerpc/sysdev/qe_lib/qe_io.c
new file mode 100644 (file)
index 0000000..aea4359
--- /dev/null
@@ -0,0 +1,226 @@
+/*
+ * arch/powerpc/sysdev/qe_lib/qe_io.c
+ *
+ * QE Parallel I/O ports configuration routines
+ *
+ * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
+ *
+ * Author: Li Yang <LeoLi@freescale.com>
+ * Based on code from Shlomi Gridish <gridish@freescale.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/ioport.h>
+
+#include <asm/io.h>
+#include <asm/prom.h>
+#include <sysdev/fsl_soc.h>
+
+#undef DEBUG
+
+#define NUM_OF_PINS    32
+
+struct port_regs {
+       __be32  cpodr;          /* Open drain register */
+       __be32  cpdata;         /* Data register */
+       __be32  cpdir1;         /* Direction register */
+       __be32  cpdir2;         /* Direction register */
+       __be32  cppar1;         /* Pin assignment register */
+       __be32  cppar2;         /* Pin assignment register */
+};
+
+static struct port_regs *par_io = NULL;
+static int num_par_io_ports = 0;
+
+int par_io_init(struct device_node *np)
+{
+       struct resource res;
+       int ret;
+       const u32 *num_ports;
+
+       /* Map Parallel I/O ports registers */
+       ret = of_address_to_resource(np, 0, &res);
+       if (ret)
+               return ret;
+       par_io = ioremap(res.start, res.end - res.start + 1);
+
+       num_ports = get_property(np, "num-ports", NULL);
+       if (num_ports)
+               num_par_io_ports = *num_ports;
+
+       return 0;
+}
+
+int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
+                     int assignment, int has_irq)
+{
+       u32 pin_mask1bit, pin_mask2bits, new_mask2bits, tmp_val;
+
+       if (!par_io)
+               return -1;
+
+       /* calculate pin location for single and 2 bits information */
+       pin_mask1bit = (u32) (1 << (NUM_OF_PINS - (pin + 1)));
+
+       /* Set open drain, if required */
+       tmp_val = in_be32(&par_io[port].cpodr);
+       if (open_drain)
+               out_be32(&par_io[port].cpodr, pin_mask1bit | tmp_val);
+       else
+               out_be32(&par_io[port].cpodr, ~pin_mask1bit & tmp_val);
+
+       /* define direction */
+       tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
+               in_be32(&par_io[port].cpdir2) :
+               in_be32(&par_io[port].cpdir1);
+
+       /* get all bits mask for 2 bit per port */
+       pin_mask2bits = (u32) (0x3 << (NUM_OF_PINS -
+                               (pin % (NUM_OF_PINS / 2) + 1) * 2));
+
+       /* Get the final mask we need for the right definition */
+       new_mask2bits = (u32) (dir << (NUM_OF_PINS -
+                               (pin % (NUM_OF_PINS / 2) + 1) * 2));
+
+       /* clear and set 2 bits mask */
+       if (pin > (NUM_OF_PINS / 2) - 1) {
+               out_be32(&par_io[port].cpdir2,
+                        ~pin_mask2bits & tmp_val);
+               tmp_val &= ~pin_mask2bits;
+               out_be32(&par_io[port].cpdir2, new_mask2bits | tmp_val);
+       } else {
+               out_be32(&par_io[port].cpdir1,
+                        ~pin_mask2bits & tmp_val);
+               tmp_val &= ~pin_mask2bits;
+               out_be32(&par_io[port].cpdir1, new_mask2bits | tmp_val);
+       }
+       /* define pin assignment */
+       tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
+               in_be32(&par_io[port].cppar2) :
+               in_be32(&par_io[port].cppar1);
+
+       new_mask2bits = (u32) (assignment << (NUM_OF_PINS -
+                       (pin % (NUM_OF_PINS / 2) + 1) * 2));
+       /* clear and set 2 bits mask */
+       if (pin > (NUM_OF_PINS / 2) - 1) {
+               out_be32(&par_io[port].cppar2,
+                        ~pin_mask2bits & tmp_val);
+               tmp_val &= ~pin_mask2bits;
+               out_be32(&par_io[port].cppar2, new_mask2bits | tmp_val);
+       } else {
+               out_be32(&par_io[port].cppar1,
+                        ~pin_mask2bits & tmp_val);
+               tmp_val &= ~pin_mask2bits;
+               out_be32(&par_io[port].cppar1, new_mask2bits | tmp_val);
+       }
+
+       return 0;
+}
+EXPORT_SYMBOL(par_io_config_pin);
+
+int par_io_data_set(u8 port, u8 pin, u8 val)
+{
+       u32 pin_mask, tmp_val;
+
+       if (port >= num_par_io_ports)
+               return -EINVAL;
+       if (pin >= NUM_OF_PINS)
+               return -EINVAL;
+       /* calculate pin location */
+       pin_mask = (u32) (1 << (NUM_OF_PINS - 1 - pin));
+
+       tmp_val = in_be32(&par_io[port].cpdata);
+
+       if (val == 0)           /* clear */
+               out_be32(&par_io[port].cpdata, ~pin_mask & tmp_val);
+       else                    /* set */
+               out_be32(&par_io[port].cpdata, pin_mask | tmp_val);
+
+       return 0;
+}
+EXPORT_SYMBOL(par_io_data_set);
+
+int par_io_of_config(struct device_node *np)
+{
+       struct device_node *pio;
+       const phandle *ph;
+       int pio_map_len;
+       const unsigned int *pio_map;
+
+       if (par_io == NULL) {
+               printk(KERN_ERR "par_io not initialized \n");
+               return -1;
+       }
+
+       ph = get_property(np, "pio-handle", NULL);
+       if (ph == 0) {
+               printk(KERN_ERR "pio-handle not available \n");
+               return -1;
+       }
+
+       pio = of_find_node_by_phandle(*ph);
+
+       pio_map = get_property(pio, "pio-map", &pio_map_len);
+       if (pio_map == NULL) {
+               printk(KERN_ERR "pio-map is not set! \n");
+               return -1;
+       }
+       pio_map_len /= sizeof(unsigned int);
+       if ((pio_map_len % 6) != 0) {
+               printk(KERN_ERR "pio-map format wrong! \n");
+               return -1;
+       }
+
+       while (pio_map_len > 0) {
+               par_io_config_pin((u8) pio_map[0], (u8) pio_map[1],
+                               (int) pio_map[2], (int) pio_map[3],
+                               (int) pio_map[4], (int) pio_map[5]);
+               pio_map += 6;
+               pio_map_len -= 6;
+       }
+       of_node_put(pio);
+       return 0;
+}
+EXPORT_SYMBOL(par_io_of_config);
+
+#ifdef DEBUG
+static void dump_par_io(void)
+{
+       int i;
+
+       printk(KERN_INFO "PAR IO registars:\n");
+       printk(KERN_INFO "Base address: 0x%08x\n", (u32) par_io);
+       for (i = 0; i < num_par_io_ports; i++) {
+               printk(KERN_INFO "cpodr[%d] : addr - 0x%08x, val - 0x%08x\n",
+                      i, (u32) & par_io[i].cpodr,
+                      in_be32(&par_io[i].cpodr));
+               printk(KERN_INFO "cpdata[%d]: addr - 0x%08x, val - 0x%08x\n",
+                      i, (u32) & par_io[i].cpdata,
+                      in_be32(&par_io[i].cpdata));
+               printk(KERN_INFO "cpdir1[%d]: addr - 0x%08x, val - 0x%08x\n",
+                      i, (u32) & par_io[i].cpdir1,
+                      in_be32(&par_io[i].cpdir1));
+               printk(KERN_INFO "cpdir2[%d]: addr - 0x%08x, val - 0x%08x\n",
+                      i, (u32) & par_io[i].cpdir2,
+                      in_be32(&par_io[i].cpdir2));
+               printk(KERN_INFO "cppar1[%d]: addr - 0x%08x, val - 0x%08x\n",
+                      i, (u32) & par_io[i].cppar1,
+                      in_be32(&par_io[i].cppar1));
+               printk(KERN_INFO "cppar2[%d]: addr - 0x%08x, val - 0x%08x\n",
+                      i, (u32) & par_io[i].cppar2,
+                      in_be32(&par_io[i].cppar2));
+       }
+
+}
+EXPORT_SYMBOL(dump_par_io);
+#endif /* DEBUG */
diff --git a/arch/powerpc/sysdev/qe_lib/ucc.c b/arch/powerpc/sysdev/qe_lib/ucc.c
new file mode 100644 (file)
index 0000000..916c9e5
--- /dev/null
@@ -0,0 +1,251 @@
+/*
+ * arch/powerpc/sysdev/qe_lib/ucc.c
+ *
+ * QE UCC API Set - UCC specific routines implementations.
+ *
+ * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
+ *
+ * Authors:    Shlomi Gridish <gridish@freescale.com>
+ *             Li Yang <leoli@freescale.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/slab.h>
+#include <linux/stddef.h>
+
+#include <asm/irq.h>
+#include <asm/io.h>
+#include <asm/immap_qe.h>
+#include <asm/qe.h>
+#include <asm/ucc.h>
+
+static DEFINE_SPINLOCK(ucc_lock);
+
+int ucc_set_qe_mux_mii_mng(int ucc_num)
+{
+       unsigned long flags;
+
+       spin_lock_irqsave(&ucc_lock, flags);
+       out_be32(&qe_immr->qmx.cmxgcr,
+                ((in_be32(&qe_immr->qmx.cmxgcr) &
+                  ~QE_CMXGCR_MII_ENET_MNG) |
+                 (ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT)));
+       spin_unlock_irqrestore(&ucc_lock, flags);
+
+       return 0;
+}
+
+int ucc_set_type(int ucc_num, struct ucc_common *regs,
+                enum ucc_speed_type speed)
+{
+       u8 guemr = 0;
+
+       /* check if the UCC number is in range. */
+       if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0))
+               return -EINVAL;
+
+       guemr = regs->guemr;
+       guemr &= ~(UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX);
+       switch (speed) {
+       case UCC_SPEED_TYPE_SLOW:
+               guemr |= (UCC_GUEMR_MODE_SLOW_RX | UCC_GUEMR_MODE_SLOW_TX);
+               break;
+       case UCC_SPEED_TYPE_FAST:
+               guemr |= (UCC_GUEMR_MODE_FAST_RX | UCC_GUEMR_MODE_FAST_TX);
+               break;
+       default:
+               return -EINVAL;
+       }
+       regs->guemr = guemr;
+
+       return 0;
+}
+
+int ucc_init_guemr(struct ucc_common *regs)
+{
+       u8 guemr = 0;
+
+       if (!regs)
+               return -EINVAL;
+
+       /* Set bit 3 (which is reserved in the GUEMR register) to 1 */
+       guemr = UCC_GUEMR_SET_RESERVED3;
+
+       regs->guemr = guemr;
+
+       return 0;
+}
+
+static void get_cmxucr_reg(int ucc_num, volatile u32 ** p_cmxucr, u8 * reg_num,
+                          u8 * shift)
+{
+       switch (ucc_num) {
+       case 0: *p_cmxucr = &(qe_immr->qmx.cmxucr1);
+               *reg_num = 1;
+               *shift = 16;
+               break;
+       case 2: *p_cmxucr = &(qe_immr->qmx.cmxucr1);
+               *reg_num = 1;
+               *shift = 0;
+               break;
+       case 4: *p_cmxucr = &(qe_immr->qmx.cmxucr2);
+               *reg_num = 2;
+               *shift = 16;
+               break;
+       case 6: *p_cmxucr = &(qe_immr->qmx.cmxucr2);
+               *reg_num = 2;
+               *shift = 0;
+               break;
+       case 1: *p_cmxucr = &(qe_immr->qmx.cmxucr3);
+               *reg_num = 3;
+               *shift = 16;
+               break;
+       case 3: *p_cmxucr = &(qe_immr->qmx.cmxucr3);
+               *reg_num = 3;
+               *shift = 0;
+               break;
+       case 5: *p_cmxucr = &(qe_immr->qmx.cmxucr4);
+               *reg_num = 4;
+               *shift = 16;
+               break;
+       case 7: *p_cmxucr = &(qe_immr->qmx.cmxucr4);
+               *reg_num = 4;
+               *shift = 0;
+               break;
+       default:
+               break;
+       }
+}
+
+int ucc_mux_set_grant_tsa_bkpt(int ucc_num, int set, u32 mask)
+{
+       volatile u32 *p_cmxucr;
+       u8 reg_num;
+       u8 shift;
+
+       /* check if the UCC number is in range. */
+       if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0))
+               return -EINVAL;
+
+       get_cmxucr_reg(ucc_num, &p_cmxucr, &reg_num, &shift);
+
+       if (set)
+               out_be32(p_cmxucr, in_be32(p_cmxucr) | (mask << shift));
+       else
+               out_be32(p_cmxucr, in_be32(p_cmxucr) & ~(mask << shift));
+
+       return 0;
+}
+
+int ucc_set_qe_mux_rxtx(int ucc_num, enum qe_clock clock, enum comm_dir mode)
+{
+       volatile u32 *p_cmxucr;
+       u8 reg_num;
+       u8 shift;
+       u32 clock_bits;
+       u32 clock_mask;
+       int source = -1;
+
+       /* check if the UCC number is in range. */
+       if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0))
+               return -EINVAL;
+
+       if (!((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX))) {
+               printk(KERN_ERR
+                      "ucc_set_qe_mux_rxtx: bad comm mode type passed.");
+               return -EINVAL;
+       }
+
+       get_cmxucr_reg(ucc_num, &p_cmxucr, &reg_num, &shift);
+
+       switch (reg_num) {
+       case 1:
+               switch (clock) {
+               case QE_BRG1:   source = 1; break;
+               case QE_BRG2:   source = 2; break;
+               case QE_BRG7:   source = 3; break;
+               case QE_BRG8:   source = 4; break;
+               case QE_CLK9:   source = 5; break;
+               case QE_CLK10:  source = 6; break;
+               case QE_CLK11:  source = 7; break;
+               case QE_CLK12:  source = 8; break;
+               case QE_CLK15:  source = 9; break;
+               case QE_CLK16:  source = 10; break;
+               default:        source = -1; break;
+               }
+               break;
+       case 2:
+               switch (clock) {
+               case QE_BRG5:   source = 1; break;
+               case QE_BRG6:   source = 2; break;
+               case QE_BRG7:   source = 3; break;
+               case QE_BRG8:   source = 4; break;
+               case QE_CLK13:  source = 5; break;
+               case QE_CLK14:  source = 6; break;
+               case QE_CLK19:  source = 7; break;
+               case QE_CLK20:  source = 8; break;
+               case QE_CLK15:  source = 9; break;
+               case QE_CLK16:  source = 10; break;
+               default:        source = -1; break;
+               }
+               break;
+       case 3:
+               switch (clock) {
+               case QE_BRG9:   source = 1; break;
+               case QE_BRG10:  source = 2; break;
+               case QE_BRG15:  source = 3; break;
+               case QE_BRG16:  source = 4; break;
+               case QE_CLK3:   source = 5; break;
+               case QE_CLK4:   source = 6; break;
+               case QE_CLK17:  source = 7; break;
+               case QE_CLK18:  source = 8; break;
+               case QE_CLK7:   source = 9; break;
+               case QE_CLK8:   source = 10; break;
+               default:        source = -1; break;
+               }
+               break;
+       case 4:
+               switch (clock) {
+               case QE_BRG13:  source = 1; break;
+               case QE_BRG14:  source = 2; break;
+               case QE_BRG15:  source = 3; break;
+               case QE_BRG16:  source = 4; break;
+               case QE_CLK5:   source = 5; break;
+               case QE_CLK6:   source = 6; break;
+               case QE_CLK21:  source = 7; break;
+               case QE_CLK22:  source = 8; break;
+               case QE_CLK7:   source = 9; break;
+               case QE_CLK8:   source = 10; break;
+               default:        source = -1; break;
+               }
+               break;
+       default:
+               source = -1;
+               break;
+       }
+
+       if (source == -1) {
+               printk(KERN_ERR
+                    "ucc_set_qe_mux_rxtx: Bad combination of clock and UCC.");
+               return -ENOENT;
+       }
+
+       clock_bits = (u32) source;
+       clock_mask = QE_CMXUCR_TX_CLK_SRC_MASK;
+       if (mode == COMM_DIR_RX) {
+               clock_bits <<= 4;  /* Rx field is 4 bits to left of Tx field */
+               clock_mask <<= 4;  /* Rx field is 4 bits to left of Tx field */
+       }
+       clock_bits <<= shift;
+       clock_mask <<= shift;
+
+       out_be32(p_cmxucr, (in_be32(p_cmxucr) & ~clock_mask) | clock_bits);
+
+       return 0;
+}
diff --git a/arch/powerpc/sysdev/qe_lib/ucc_fast.c b/arch/powerpc/sysdev/qe_lib/ucc_fast.c
new file mode 100644 (file)
index 0000000..c2be734
--- /dev/null
@@ -0,0 +1,396 @@
+/*
+ * arch/powerpc/sysdev/qe_lib/ucc_fast.c
+ *
+ * QE UCC Fast API Set - UCC Fast specific routines implementations.
+ *
+ * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
+ *
+ * Authors:    Shlomi Gridish <gridish@freescale.com>
+ *             Li Yang <leoli@freescale.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/slab.h>
+#include <linux/stddef.h>
+#include <linux/interrupt.h>
+
+#include <asm/io.h>
+#include <asm/immap_qe.h>
+#include <asm/qe.h>
+
+#include <asm/ucc.h>
+#include <asm/ucc_fast.h>
+
+#define uccf_printk(level, format, arg...) \
+       printk(level format "\n", ## arg)
+
+#define uccf_dbg(format, arg...) \
+       uccf_printk(KERN_DEBUG , format , ## arg)
+#define uccf_err(format, arg...) \
+       uccf_printk(KERN_ERR , format , ## arg)
+#define uccf_info(format, arg...) \
+       uccf_printk(KERN_INFO , format , ## arg)
+#define uccf_warn(format, arg...) \
+       uccf_printk(KERN_WARNING , format , ## arg)
+
+#ifdef UCCF_VERBOSE_DEBUG
+#define uccf_vdbg uccf_dbg
+#else
+#define uccf_vdbg(fmt, args...) do { } while (0)
+#endif                         /* UCCF_VERBOSE_DEBUG */
+
+void ucc_fast_dump_regs(struct ucc_fast_private * uccf)
+{
+       uccf_info("UCC%d Fast registers:", uccf->uf_info->ucc_num);
+       uccf_info("Base address: 0x%08x", (u32) uccf->uf_regs);
+
+       uccf_info("gumr  : addr - 0x%08x, val - 0x%08x",
+                 (u32) & uccf->uf_regs->gumr, in_be32(&uccf->uf_regs->gumr));
+       uccf_info("upsmr : addr - 0x%08x, val - 0x%08x",
+                 (u32) & uccf->uf_regs->upsmr, in_be32(&uccf->uf_regs->upsmr));
+       uccf_info("utodr : addr - 0x%08x, val - 0x%04x",
+                 (u32) & uccf->uf_regs->utodr, in_be16(&uccf->uf_regs->utodr));
+       uccf_info("udsr  : addr - 0x%08x, val - 0x%04x",
+                 (u32) & uccf->uf_regs->udsr, in_be16(&uccf->uf_regs->udsr));
+       uccf_info("ucce  : addr - 0x%08x, val - 0x%08x",
+                 (u32) & uccf->uf_regs->ucce, in_be32(&uccf->uf_regs->ucce));
+       uccf_info("uccm  : addr - 0x%08x, val - 0x%08x",
+                 (u32) & uccf->uf_regs->uccm, in_be32(&uccf->uf_regs->uccm));
+       uccf_info("uccs  : addr - 0x%08x, val - 0x%02x",
+                 (u32) & uccf->uf_regs->uccs, uccf->uf_regs->uccs);
+       uccf_info("urfb  : addr - 0x%08x, val - 0x%08x",
+                 (u32) & uccf->uf_regs->urfb, in_be32(&uccf->uf_regs->urfb));
+       uccf_info("urfs  : addr - 0x%08x, val - 0x%04x",
+                 (u32) & uccf->uf_regs->urfs, in_be16(&uccf->uf_regs->urfs));
+       uccf_info("urfet : addr - 0x%08x, val - 0x%04x",
+                 (u32) & uccf->uf_regs->urfet, in_be16(&uccf->uf_regs->urfet));
+       uccf_info("urfset: addr - 0x%08x, val - 0x%04x",
+                 (u32) & uccf->uf_regs->urfset,
+                 in_be16(&uccf->uf_regs->urfset));
+       uccf_info("utfb  : addr - 0x%08x, val - 0x%08x",
+                 (u32) & uccf->uf_regs->utfb, in_be32(&uccf->uf_regs->utfb));
+       uccf_info("utfs  : addr - 0x%08x, val - 0x%04x",
+                 (u32) & uccf->uf_regs->utfs, in_be16(&uccf->uf_regs->utfs));
+       uccf_info("utfet : addr - 0x%08x, val - 0x%04x",
+                 (u32) & uccf->uf_regs->utfet, in_be16(&uccf->uf_regs->utfet));
+       uccf_info("utftt : addr - 0x%08x, val - 0x%04x",
+                 (u32) & uccf->uf_regs->utftt, in_be16(&uccf->uf_regs->utftt));
+       uccf_info("utpt  : addr - 0x%08x, val - 0x%04x",
+                 (u32) & uccf->uf_regs->utpt, in_be16(&uccf->uf_regs->utpt));
+       uccf_info("urtry : addr - 0x%08x, val - 0x%08x",
+                 (u32) & uccf->uf_regs->urtry, in_be32(&uccf->uf_regs->urtry));
+       uccf_info("guemr : addr - 0x%08x, val - 0x%02x",
+                 (u32) & uccf->uf_regs->guemr, uccf->uf_regs->guemr);
+}
+
+u32 ucc_fast_get_qe_cr_subblock(int uccf_num)
+{
+       switch (uccf_num) {
+       case 0: return QE_CR_SUBBLOCK_UCCFAST1;
+       case 1: return QE_CR_SUBBLOCK_UCCFAST2;
+       case 2: return QE_CR_SUBBLOCK_UCCFAST3;
+       case 3: return QE_CR_SUBBLOCK_UCCFAST4;
+       case 4: return QE_CR_SUBBLOCK_UCCFAST5;
+       case 5: return QE_CR_SUBBLOCK_UCCFAST6;
+       case 6: return QE_CR_SUBBLOCK_UCCFAST7;
+       case 7: return QE_CR_SUBBLOCK_UCCFAST8;
+       default: return QE_CR_SUBBLOCK_INVALID;
+       }
+}
+
+void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf)
+{
+       out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);
+}
+
+void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode)
+{
+       struct ucc_fast *uf_regs;
+       u32 gumr;
+
+       uf_regs = uccf->uf_regs;
+
+       /* Enable reception and/or transmission on this UCC. */
+       gumr = in_be32(&uf_regs->gumr);
+       if (mode & COMM_DIR_TX) {
+               gumr |= UCC_FAST_GUMR_ENT;
+               uccf->enabled_tx = 1;
+       }
+       if (mode & COMM_DIR_RX) {
+               gumr |= UCC_FAST_GUMR_ENR;
+               uccf->enabled_rx = 1;
+       }
+       out_be32(&uf_regs->gumr, gumr);
+}
+
+void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode)
+{
+       struct ucc_fast *uf_regs;
+       u32 gumr;
+
+       uf_regs = uccf->uf_regs;
+
+       /* Disable reception and/or transmission on this UCC. */
+       gumr = in_be32(&uf_regs->gumr);
+       if (mode & COMM_DIR_TX) {
+               gumr &= ~UCC_FAST_GUMR_ENT;
+               uccf->enabled_tx = 0;
+       }
+       if (mode & COMM_DIR_RX) {
+               gumr &= ~UCC_FAST_GUMR_ENR;
+               uccf->enabled_rx = 0;
+       }
+       out_be32(&uf_regs->gumr, gumr);
+}
+
+int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** uccf_ret)
+{
+       struct ucc_fast_private *uccf;
+       struct ucc_fast *uf_regs;
+       u32 gumr = 0;
+       int ret;
+
+       uccf_vdbg("%s: IN", __FUNCTION__);
+
+       if (!uf_info)
+               return -EINVAL;
+
+       /* check if the UCC port number is in range. */
+       if ((uf_info->ucc_num < 0) || (uf_info->ucc_num > UCC_MAX_NUM - 1)) {
+               uccf_err("ucc_fast_init: Illagal UCC number!");
+               return -EINVAL;
+       }
+
+       /* Check that 'max_rx_buf_length' is properly aligned (4). */
+       if (uf_info->max_rx_buf_length & (UCC_FAST_MRBLR_ALIGNMENT - 1)) {
+               uccf_err("ucc_fast_init: max_rx_buf_length not aligned.");
+               return -EINVAL;
+       }
+
+       /* Validate Virtual Fifo register values */
+       if (uf_info->urfs < UCC_FAST_URFS_MIN_VAL) {
+               uccf_err
+                   ("ucc_fast_init: Virtual Fifo register urfs too small.");
+               return -EINVAL;
+       }
+
+       if (uf_info->urfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
+               uccf_err
+                   ("ucc_fast_init: Virtual Fifo register urfs not aligned.");
+               return -EINVAL;
+       }
+
+       if (uf_info->urfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
+               uccf_err
+                   ("ucc_fast_init: Virtual Fifo register urfet not aligned.");
+               return -EINVAL;
+       }
+
+       if (uf_info->urfset & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
+               uccf_err
+                  ("ucc_fast_init: Virtual Fifo register urfset not aligned.");
+               return -EINVAL;
+       }
+
+       if (uf_info->utfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
+               uccf_err
+                   ("ucc_fast_init: Virtual Fifo register utfs not aligned.");
+               return -EINVAL;
+       }
+
+       if (uf_info->utfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
+               uccf_err
+                   ("ucc_fast_init: Virtual Fifo register utfet not aligned.");
+               return -EINVAL;
+       }
+
+       if (uf_info->utftt & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
+               uccf_err
+                   ("ucc_fast_init: Virtual Fifo register utftt not aligned.");
+               return -EINVAL;
+       }
+
+       uccf = (struct ucc_fast_private *)
+                kmalloc(sizeof(struct ucc_fast_private), GFP_KERNEL);
+       if (!uccf) {
+               uccf_err
+                   ("ucc_fast_init: No memory for UCC slow data structure!");
+               return -ENOMEM;
+       }
+       memset(uccf, 0, sizeof(struct ucc_fast_private));
+
+       /* Fill fast UCC structure */
+       uccf->uf_info = uf_info;
+       /* Set the PHY base address */
+       uccf->uf_regs =
+           (struct ucc_fast *) ioremap(uf_info->regs, sizeof(struct ucc_fast));
+       if (uccf->uf_regs == NULL) {
+               uccf_err
+                   ("ucc_fast_init: No memory map for UCC slow controller!");
+               return -ENOMEM;
+       }
+
+       uccf->enabled_tx = 0;
+       uccf->enabled_rx = 0;
+       uccf->stopped_tx = 0;
+       uccf->stopped_rx = 0;
+       uf_regs = uccf->uf_regs;
+       uccf->p_ucce = (u32 *) & (uf_regs->ucce);
+       uccf->p_uccm = (u32 *) & (uf_regs->uccm);
+#ifdef STATISTICS
+       uccf->tx_frames = 0;
+       uccf->rx_frames = 0;
+       uccf->rx_discarded = 0;
+#endif                         /* STATISTICS */
+
+       /* Init Guemr register */
+       if ((ret = ucc_init_guemr((struct ucc_common *) (uf_regs)))) {
+               uccf_err("ucc_fast_init: Could not init the guemr register.");
+               ucc_fast_free(uccf);
+               return ret;
+       }
+
+       /* Set UCC to fast type */
+       if ((ret = ucc_set_type(uf_info->ucc_num,
+                               (struct ucc_common *) (uf_regs),
+                               UCC_SPEED_TYPE_FAST))) {
+               uccf_err("ucc_fast_init: Could not set type to fast.");
+               ucc_fast_free(uccf);
+               return ret;
+       }
+
+       uccf->mrblr = uf_info->max_rx_buf_length;
+
+       /* Set GUMR */
+       /* For more details see the hardware spec. */
+       /* gumr starts as zero. */
+       if (uf_info->tci)
+               gumr |= UCC_FAST_GUMR_TCI;
+       gumr |= uf_info->ttx_trx;
+       if (uf_info->cdp)
+               gumr |= UCC_FAST_GUMR_CDP;
+       if (uf_info->ctsp)
+               gumr |= UCC_FAST_GUMR_CTSP;
+       if (uf_info->cds)
+               gumr |= UCC_FAST_GUMR_CDS;
+       if (uf_info->ctss)
+               gumr |= UCC_FAST_GUMR_CTSS;
+       if (uf_info->txsy)
+               gumr |= UCC_FAST_GUMR_TXSY;
+       if (uf_info->rsyn)
+               gumr |= UCC_FAST_GUMR_RSYN;
+       gumr |= uf_info->synl;
+       if (uf_info->rtsm)
+               gumr |= UCC_FAST_GUMR_RTSM;
+       gumr |= uf_info->renc;
+       if (uf_info->revd)
+               gumr |= UCC_FAST_GUMR_REVD;
+       gumr |= uf_info->tenc;
+       gumr |= uf_info->tcrc;
+       gumr |= uf_info->mode;
+       out_be32(&uf_regs->gumr, gumr);
+
+       /* Allocate memory for Tx Virtual Fifo */
+       uccf->ucc_fast_tx_virtual_fifo_base_offset =
+           qe_muram_alloc(uf_info->utfs, UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
+       if (IS_MURAM_ERR(uccf->ucc_fast_tx_virtual_fifo_base_offset)) {
+               uccf_err
+                   ("ucc_fast_init: Can not allocate MURAM memory for "
+                       "struct ucc_fastx_virtual_fifo_base_offset.");
+               uccf->ucc_fast_tx_virtual_fifo_base_offset = 0;
+               ucc_fast_free(uccf);
+               return -ENOMEM;
+       }
+
+       /* Allocate memory for Rx Virtual Fifo */
+       uccf->ucc_fast_rx_virtual_fifo_base_offset =
+           qe_muram_alloc(uf_info->urfs +
+                          (u32)
+                          UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR,
+                          UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
+       if (IS_MURAM_ERR(uccf->ucc_fast_rx_virtual_fifo_base_offset)) {
+               uccf_err
+                   ("ucc_fast_init: Can not allocate MURAM memory for "
+                       "ucc_fast_rx_virtual_fifo_base_offset.");
+               uccf->ucc_fast_rx_virtual_fifo_base_offset = 0;
+               ucc_fast_free(uccf);
+               return -ENOMEM;
+       }
+
+       /* Set Virtual Fifo registers */
+       out_be16(&uf_regs->urfs, uf_info->urfs);
+       out_be16(&uf_regs->urfet, uf_info->urfet);
+       out_be16(&uf_regs->urfset, uf_info->urfset);
+       out_be16(&uf_regs->utfs, uf_info->utfs);
+       out_be16(&uf_regs->utfet, uf_info->utfet);
+       out_be16(&uf_regs->utftt, uf_info->utftt);
+       /* utfb, urfb are offsets from MURAM base */
+       out_be32(&uf_regs->utfb, uccf->ucc_fast_tx_virtual_fifo_base_offset);
+       out_be32(&uf_regs->urfb, uccf->ucc_fast_rx_virtual_fifo_base_offset);
+
+       /* Mux clocking */
+       /* Grant Support */
+       ucc_set_qe_mux_grant(uf_info->ucc_num, uf_info->grant_support);
+       /* Breakpoint Support */
+       ucc_set_qe_mux_bkpt(uf_info->ucc_num, uf_info->brkpt_support);
+       /* Set Tsa or NMSI mode. */
+       ucc_set_qe_mux_tsa(uf_info->ucc_num, uf_info->tsa);
+       /* If NMSI (not Tsa), set Tx and Rx clock. */
+       if (!uf_info->tsa) {
+               /* Rx clock routing */
+               if (uf_info->rx_clock != QE_CLK_NONE) {
+                       if (ucc_set_qe_mux_rxtx
+                           (uf_info->ucc_num, uf_info->rx_clock,
+                            COMM_DIR_RX)) {
+                               uccf_err
+               ("ucc_fast_init: Illegal value for parameter 'RxClock'.");
+                               ucc_fast_free(uccf);
+                               return -EINVAL;
+                       }
+               }
+               /* Tx clock routing */
+               if (uf_info->tx_clock != QE_CLK_NONE) {
+                       if (ucc_set_qe_mux_rxtx
+                           (uf_info->ucc_num, uf_info->tx_clock,
+                            COMM_DIR_TX)) {
+                               uccf_err
+               ("ucc_fast_init: Illegal value for parameter 'TxClock'.");
+                               ucc_fast_free(uccf);
+                               return -EINVAL;
+                       }
+               }
+       }
+
+       /* Set interrupt mask register at UCC level. */
+       out_be32(&uf_regs->uccm, uf_info->uccm_mask);
+
+       /* First, clear anything pending at UCC level,
+        * otherwise, old garbage may come through
+        * as soon as the dam is opened
+        * Writing '1' clears
+        */
+       out_be32(&uf_regs->ucce, 0xffffffff);
+
+       *uccf_ret = uccf;
+       return 0;
+}
+
+void ucc_fast_free(struct ucc_fast_private * uccf)
+{
+       if (!uccf)
+               return;
+
+       if (uccf->ucc_fast_tx_virtual_fifo_base_offset)
+               qe_muram_free(uccf->ucc_fast_tx_virtual_fifo_base_offset);
+
+       if (uccf->ucc_fast_rx_virtual_fifo_base_offset)
+               qe_muram_free(uccf->ucc_fast_rx_virtual_fifo_base_offset);
+
+       kfree(uccf);
+}
diff --git a/arch/powerpc/sysdev/qe_lib/ucc_slow.c b/arch/powerpc/sysdev/qe_lib/ucc_slow.c
new file mode 100644 (file)
index 0000000..1fb88ef
--- /dev/null
@@ -0,0 +1,404 @@
+/*
+ * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
+ *
+ * Authors:    Shlomi Gridish <gridish@freescale.com>
+ *             Li Yang <leoli@freescale.com>
+ *
+ * Description:
+ * QE UCC Slow API Set - UCC Slow specific routines implementations.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/slab.h>
+#include <linux/stddef.h>
+#include <linux/interrupt.h>
+
+#include <asm/irq.h>
+#include <asm/io.h>
+#include <asm/immap_qe.h>
+#include <asm/qe.h>
+
+#include <asm/ucc.h>
+#include <asm/ucc_slow.h>
+
+#define uccs_printk(level, format, arg...) \
+        printk(level format "\n", ## arg)
+
+#define uccs_dbg(format, arg...) \
+       uccs_printk(KERN_DEBUG , format , ## arg)
+#define uccs_err(format, arg...) \
+       uccs_printk(KERN_ERR , format , ## arg)
+#define uccs_info(format, arg...) \
+       uccs_printk(KERN_INFO , format , ## arg)
+#define uccs_warn(format, arg...) \
+       uccs_printk(KERN_WARNING , format , ## arg)
+
+#ifdef UCCS_VERBOSE_DEBUG
+#define uccs_vdbg uccs_dbg
+#else
+#define uccs_vdbg(fmt, args...) do { } while (0)
+#endif                         /* UCCS_VERBOSE_DEBUG */
+
+u32 ucc_slow_get_qe_cr_subblock(int uccs_num)
+{
+       switch (uccs_num) {
+       case 0: return QE_CR_SUBBLOCK_UCCSLOW1;
+       case 1: return QE_CR_SUBBLOCK_UCCSLOW2;
+       case 2: return QE_CR_SUBBLOCK_UCCSLOW3;
+       case 3: return QE_CR_SUBBLOCK_UCCSLOW4;
+       case 4: return QE_CR_SUBBLOCK_UCCSLOW5;
+       case 5: return QE_CR_SUBBLOCK_UCCSLOW6;
+       case 6: return QE_CR_SUBBLOCK_UCCSLOW7;
+       case 7: return QE_CR_SUBBLOCK_UCCSLOW8;
+       default: return QE_CR_SUBBLOCK_INVALID;
+       }
+}
+
+void ucc_slow_poll_transmitter_now(struct ucc_slow_private * uccs)
+{
+       out_be16(&uccs->us_regs->utodr, UCC_SLOW_TOD);
+}
+
+void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs)
+{
+       struct ucc_slow_info *us_info = uccs->us_info;
+       u32 id;
+
+       id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
+       qe_issue_cmd(QE_GRACEFUL_STOP_TX, id,
+                        QE_CR_PROTOCOL_UNSPECIFIED, 0);
+}
+
+void ucc_slow_stop_tx(struct ucc_slow_private * uccs)
+{
+       struct ucc_slow_info *us_info = uccs->us_info;
+       u32 id;
+
+       id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
+       qe_issue_cmd(QE_STOP_TX, id, QE_CR_PROTOCOL_UNSPECIFIED, 0);
+}
+
+void ucc_slow_restart_tx(struct ucc_slow_private * uccs)
+{
+       struct ucc_slow_info *us_info = uccs->us_info;
+       u32 id;
+
+       id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
+       qe_issue_cmd(QE_RESTART_TX, id, QE_CR_PROTOCOL_UNSPECIFIED, 0);
+}
+
+void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode)
+{
+       struct ucc_slow *us_regs;
+       u32 gumr_l;
+
+       us_regs = uccs->us_regs;
+
+       /* Enable reception and/or transmission on this UCC. */
+       gumr_l = in_be32(&us_regs->gumr_l);
+       if (mode & COMM_DIR_TX) {
+               gumr_l |= UCC_SLOW_GUMR_L_ENT;
+               uccs->enabled_tx = 1;
+       }
+       if (mode & COMM_DIR_RX) {
+               gumr_l |= UCC_SLOW_GUMR_L_ENR;
+               uccs->enabled_rx = 1;
+       }
+       out_be32(&us_regs->gumr_l, gumr_l);
+}
+
+void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)
+{
+       struct ucc_slow *us_regs;
+       u32 gumr_l;
+
+       us_regs = uccs->us_regs;
+
+       /* Disable reception and/or transmission on this UCC. */
+       gumr_l = in_be32(&us_regs->gumr_l);
+       if (mode & COMM_DIR_TX) {
+               gumr_l &= ~UCC_SLOW_GUMR_L_ENT;
+               uccs->enabled_tx = 0;
+       }
+       if (mode & COMM_DIR_RX) {
+               gumr_l &= ~UCC_SLOW_GUMR_L_ENR;
+               uccs->enabled_rx = 0;
+       }
+       out_be32(&us_regs->gumr_l, gumr_l);
+}
+
+int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** uccs_ret)
+{
+       u32 i;
+       struct ucc_slow *us_regs;
+       u32 gumr;
+       u8 function_code = 0;
+       u8 *bd;
+       struct ucc_slow_private *uccs;
+       u32 id;
+       u32 command;
+       int ret;
+
+       uccs_vdbg("%s: IN", __FUNCTION__);
+
+       if (!us_info)
+               return -EINVAL;
+
+       /* check if the UCC port number is in range. */
+       if ((us_info->ucc_num < 0) || (us_info->ucc_num > UCC_MAX_NUM - 1)) {
+               uccs_err("ucc_slow_init: Illagal UCC number!");
+               return -EINVAL;
+       }
+
+       /*
+        * Set mrblr
+        * Check that 'max_rx_buf_length' is properly aligned (4), unless
+        * rfw is 1, meaning that QE accepts one byte at a time, unlike normal
+        * case when QE accepts 32 bits at a time.
+        */
+       if ((!us_info->rfw) &&
+               (us_info->max_rx_buf_length & (UCC_SLOW_MRBLR_ALIGNMENT - 1))) {
+               uccs_err("max_rx_buf_length not aligned.");
+               return -EINVAL;
+       }
+
+       uccs = (struct ucc_slow_private *)
+               kmalloc(sizeof(struct ucc_slow_private), GFP_KERNEL);
+       if (!uccs) {
+               uccs_err
+                   ("ucc_slow_init: No memory for UCC slow data structure!");
+               return -ENOMEM;
+       }
+       memset(uccs, 0, sizeof(struct ucc_slow_private));
+
+       /* Fill slow UCC structure */
+       uccs->us_info = us_info;
+       uccs->saved_uccm = 0;
+       uccs->p_rx_frame = 0;
+       uccs->us_regs = us_info->us_regs;
+       us_regs = uccs->us_regs;
+       uccs->p_ucce = (u16 *) & (us_regs->ucce);
+       uccs->p_uccm = (u16 *) & (us_regs->uccm);
+#ifdef STATISTICS
+       uccs->rx_frames = 0;
+       uccs->tx_frames = 0;
+       uccs->rx_discarded = 0;
+#endif                         /* STATISTICS */
+
+       /* Get PRAM base */
+       uccs->us_pram_offset = qe_muram_alloc(UCC_SLOW_PRAM_SIZE,
+                                                ALIGNMENT_OF_UCC_SLOW_PRAM);
+       if (IS_MURAM_ERR(uccs->us_pram_offset)) {
+               uccs_err
+                   ("ucc_slow_init: Can not allocate MURAM memory "
+                       "for Slow UCC.");
+               ucc_slow_free(uccs);
+               return -ENOMEM;
+       }
+       id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
+       qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, id, QE_CR_PROTOCOL_UNSPECIFIED,
+                       (u32) uccs->us_pram_offset);
+
+       uccs->us_pram = qe_muram_addr(uccs->us_pram_offset);
+
+       /* Init Guemr register */
+       if ((ret = ucc_init_guemr((struct ucc_common *) (us_info->us_regs)))) {
+               uccs_err("ucc_slow_init: Could not init the guemr register.");
+               ucc_slow_free(uccs);
+               return ret;
+       }
+
+       /* Set UCC to slow type */
+       if ((ret = ucc_set_type(us_info->ucc_num,
+                               (struct ucc_common *) (us_info->us_regs),
+                               UCC_SPEED_TYPE_SLOW))) {
+               uccs_err("ucc_slow_init: Could not init the guemr register.");
+               ucc_slow_free(uccs);
+               return ret;
+       }
+
+       out_be16(&uccs->us_pram->mrblr, us_info->max_rx_buf_length);
+
+       INIT_LIST_HEAD(&uccs->confQ);
+
+       /* Allocate BDs. */
+       uccs->rx_base_offset =
+               qe_muram_alloc(us_info->rx_bd_ring_len * sizeof(struct qe_bd),
+                               QE_ALIGNMENT_OF_BD);
+       if (IS_MURAM_ERR(uccs->rx_base_offset)) {
+               uccs_err("ucc_slow_init: No memory for Rx BD's.");
+               uccs->rx_base_offset = 0;
+               ucc_slow_free(uccs);
+               return -ENOMEM;
+       }
+
+       uccs->tx_base_offset =
+               qe_muram_alloc(us_info->tx_bd_ring_len * sizeof(struct qe_bd),
+                       QE_ALIGNMENT_OF_BD);
+       if (IS_MURAM_ERR(uccs->tx_base_offset)) {
+               uccs_err("ucc_slow_init: No memory for Tx BD's.");
+               uccs->tx_base_offset = 0;
+               ucc_slow_free(uccs);
+               return -ENOMEM;
+       }
+
+       /* Init Tx bds */
+       bd = uccs->confBd = uccs->tx_bd = qe_muram_addr(uccs->tx_base_offset);
+       for (i = 0; i < us_info->tx_bd_ring_len; i++) {
+               /* clear bd buffer */
+               out_be32(&(((struct qe_bd *)bd)->buf), 0);
+               /* set bd status and length */
+               out_be32((u32*)bd, 0);
+               bd += sizeof(struct qe_bd);
+       }
+       bd -= sizeof(struct qe_bd);
+       /* set bd status and length */
+       out_be32((u32*)bd, T_W);        /* for last BD set Wrap bit */
+
+       /* Init Rx bds */
+       bd = uccs->rx_bd = qe_muram_addr(uccs->rx_base_offset);
+       for (i = 0; i < us_info->rx_bd_ring_len; i++) {
+               /* set bd status and length */
+               out_be32((u32*)bd, 0);
+               /* clear bd buffer */
+               out_be32(&(((struct qe_bd *)bd)->buf), 0);
+               bd += sizeof(struct qe_bd);
+       }
+       bd -= sizeof(struct qe_bd);
+       /* set bd status and length */
+       out_be32((u32*)bd, R_W);        /* for last BD set Wrap bit */
+
+       /* Set GUMR (For more details see the hardware spec.). */
+       /* gumr_h */
+       gumr = 0;
+       gumr |= us_info->tcrc;
+       if (us_info->cdp)
+               gumr |= UCC_SLOW_GUMR_H_CDP;
+       if (us_info->ctsp)
+               gumr |= UCC_SLOW_GUMR_H_CTSP;
+       if (us_info->cds)
+               gumr |= UCC_SLOW_GUMR_H_CDS;
+       if (us_info->ctss)
+               gumr |= UCC_SLOW_GUMR_H_CTSS;
+       if (us_info->tfl)
+               gumr |= UCC_SLOW_GUMR_H_TFL;
+       if (us_info->rfw)
+               gumr |= UCC_SLOW_GUMR_H_RFW;
+       if (us_info->txsy)
+               gumr |= UCC_SLOW_GUMR_H_TXSY;
+       if (us_info->rtsm)
+               gumr |= UCC_SLOW_GUMR_H_RTSM;
+       out_be32(&us_regs->gumr_h, gumr);
+
+       /* gumr_l */
+       gumr = 0;
+       if (us_info->tci)
+               gumr |= UCC_SLOW_GUMR_L_TCI;
+       if (us_info->rinv)
+               gumr |= UCC_SLOW_GUMR_L_RINV;
+       if (us_info->tinv)
+               gumr |= UCC_SLOW_GUMR_L_TINV;
+       if (us_info->tend)
+               gumr |= UCC_SLOW_GUMR_L_TEND;
+       gumr |= us_info->tdcr;
+       gumr |= us_info->rdcr;
+       gumr |= us_info->tenc;
+       gumr |= us_info->renc;
+       gumr |= us_info->diag;
+       gumr |= us_info->mode;
+       out_be32(&us_regs->gumr_l, gumr);
+
+       /* Function code registers */
+       /* function_code has initial value 0 */
+
+       /* if the data is in cachable memory, the 'global' */
+       /* in the function code should be set. */
+       function_code |= us_info->data_mem_part;
+       function_code |= QE_BMR_BYTE_ORDER_BO_MOT;      /* Required for QE */
+       uccs->us_pram->tfcr = function_code;
+       uccs->us_pram->rfcr = function_code;
+
+       /* rbase, tbase are offsets from MURAM base */
+       out_be16(&uccs->us_pram->rbase, uccs->us_pram_offset);
+       out_be16(&uccs->us_pram->tbase, uccs->us_pram_offset);
+
+       /* Mux clocking */
+       /* Grant Support */
+       ucc_set_qe_mux_grant(us_info->ucc_num, us_info->grant_support);
+       /* Breakpoint Support */
+       ucc_set_qe_mux_bkpt(us_info->ucc_num, us_info->brkpt_support);
+       /* Set Tsa or NMSI mode. */
+       ucc_set_qe_mux_tsa(us_info->ucc_num, us_info->tsa);
+       /* If NMSI (not Tsa), set Tx and Rx clock. */
+       if (!us_info->tsa) {
+               /* Rx clock routing */
+               if (ucc_set_qe_mux_rxtx
+                   (us_info->ucc_num, us_info->rx_clock, COMM_DIR_RX)) {
+                       uccs_err
+                           ("ucc_slow_init: Illegal value for parameter"
+                               " 'RxClock'.");
+                       ucc_slow_free(uccs);
+                       return -EINVAL;
+               }
+               /* Tx clock routing */
+               if (ucc_set_qe_mux_rxtx(us_info->ucc_num,
+                                us_info->tx_clock, COMM_DIR_TX)) {
+                       uccs_err
+                           ("ucc_slow_init: Illegal value for parameter "
+                               "'TxClock'.");
+                       ucc_slow_free(uccs);
+                       return -EINVAL;
+               }
+       }
+
+       /*
+        * INTERRUPTS
+        */
+       /* Set interrupt mask register at UCC level. */
+       out_be16(&us_regs->uccm, us_info->uccm_mask);
+
+       /* First, clear anything pending at UCC level, */
+       /* otherwise, old garbage may come through */
+       /* as soon as the dam is opened. */
+
+       /* Writing '1' clears */
+       out_be16(&us_regs->ucce, 0xffff);
+
+       /* Issue QE Init command */
+       if (us_info->init_tx && us_info->init_rx)
+               command = QE_INIT_TX_RX;
+       else if (us_info->init_tx)
+               command = QE_INIT_TX;
+       else
+               command = QE_INIT_RX;   /* We know at least one is TRUE */
+       id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
+       qe_issue_cmd(command, id, QE_CR_PROTOCOL_UNSPECIFIED, 0);
+
+       *uccs_ret = uccs;
+       return 0;
+}
+
+void ucc_slow_free(struct ucc_slow_private * uccs)
+{
+       if (!uccs)
+               return;
+
+       if (uccs->rx_base_offset)
+               qe_muram_free(uccs->rx_base_offset);
+
+       if (uccs->tx_base_offset)
+               qe_muram_free(uccs->tx_base_offset);
+
+       if (uccs->us_pram) {
+               qe_muram_free(uccs->us_pram_offset);
+               uccs->us_pram = NULL;
+       }
+
+       kfree(uccs);
+}
index 8adad14..708236f 100644 (file)
@@ -2,6 +2,8 @@
  * Routines providing a simple monitor for use on the PowerMac.
  *
  * Copyright (C) 1996-2005 Paul Mackerras.
+ * Copyright (C) 2001 PPC64 Team, IBM Corp
+ * Copyrignt (C) 2006 Michael Ellerman, IBM Corp
  *
  *      This program is free software; you can redistribute it and/or
  *      modify it under the terms of the GNU General Public License
@@ -503,7 +505,7 @@ static int xmon_core(struct pt_regs *regs, int fromipi)
 
        mtmsr(msr);             /* restore interrupt enable */
 
-       return cmd != 'X';
+       return cmd != 'X' && cmd != EOF;
 }
 
 int xmon(struct pt_regs *excp)
@@ -2597,3 +2599,34 @@ static int __init setup_xmon_sysrq(void)
 }
 __initcall(setup_xmon_sysrq);
 #endif /* CONFIG_MAGIC_SYSRQ */
+
+int __initdata xmon_early, xmon_off;
+
+static int __init early_parse_xmon(char *p)
+{
+       if (!p || strncmp(p, "early", 5) == 0) {
+               /* just "xmon" is equivalent to "xmon=early" */
+               xmon_init(1);
+               xmon_early = 1;
+       } else if (strncmp(p, "on", 2) == 0)
+               xmon_init(1);
+       else if (strncmp(p, "off", 3) == 0)
+               xmon_off = 1;
+       else if (strncmp(p, "nobt", 4) == 0)
+               xmon_no_auto_backtrace = 1;
+       else
+               return 1;
+
+       return 0;
+}
+early_param("xmon", early_parse_xmon);
+
+void __init xmon_setup(void)
+{
+#ifdef CONFIG_XMON_DEFAULT
+       if (!xmon_off)
+               xmon_init(1);
+#endif
+       if (xmon_early)
+               debugger(NULL);
+}
index f2305ee..fdc8f89 100644 (file)
@@ -636,7 +636,7 @@ static irqreturn_t swim3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
        intr = in_8(&sw->intr);
        err = (intr & ERROR_INTR)? in_8(&sw->error): 0;
        if ((intr & ERROR_INTR) && fs->state != do_transfer)
-               printk(KERN_ERR "swim3_interrupt, state=%d, dir=%lx, intr=%x, err=%x\n",
+               printk(KERN_ERR "swim3_interrupt, state=%d, dir=%x, intr=%x, err=%x\n",
                       fs->state, rq_data_dir(fd_req), intr, err);
        switch (fs->state) {
        case locating:
@@ -742,7 +742,7 @@ static irqreturn_t swim3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
                        if ((stat & ACTIVE) == 0 || resid != 0) {
                                /* musta been an error */
                                printk(KERN_ERR "swim3: fd dma: stat=%x resid=%d\n", stat, resid);
-                               printk(KERN_ERR "  state=%d, dir=%lx, intr=%x, err=%x\n",
+                               printk(KERN_ERR "  state=%d, dir=%x, intr=%x, err=%x\n",
                                       fs->state, rq_data_dir(fd_req), intr, err);
                                end_request(fd_req, 0);
                                fs->state = idle;
index 8b6f197..f144a94 100644 (file)
@@ -29,6 +29,7 @@
 #include <asm/hvconsole.h>
 #include <asm/vio.h>
 #include <asm/prom.h>
+#include <asm/firmware.h>
 #include <asm/iseries/vio.h>
 #include <asm/iseries/hv_call.h>
 #include <asm/iseries/hv_lp_config.h>
@@ -488,6 +489,9 @@ static int hvc_vio_init(void)
        atomic_t wait_flag;
        int rc;
 
+       if (!firmware_has_feature(FW_FEATURE_ISERIES))
+               return -EIO;
+
        /* +2 for fudge */
        rc = viopath_open(HvLpConfig_getPrimaryLpIndex(),
                        viomajorsubtype_chario, VIOCHAR_WINDOW + 2);
@@ -562,7 +566,7 @@ static int hvc_find_vtys(void)
 
        for (vty = of_find_node_by_name(NULL, "vty"); vty != NULL;
                        vty = of_find_node_by_name(vty, "vty")) {
-               uint32_t *vtermno;
+               const uint32_t *vtermno;
 
                /* We have statically defined space for only a certain number
                 * of console adapters.
@@ -571,7 +575,7 @@ static int hvc_find_vtys(void)
                                (num_found >= VTTY_PORTS))
                        break;
 
-               vtermno = (uint32_t *)get_property(vty, "reg", NULL);
+               vtermno = get_property(vty, "reg", NULL);
                if (!vtermno)
                        continue;
 
index cc95941..f9c0084 100644 (file)
@@ -35,6 +35,7 @@
 #include <asm/hvconsole.h>
 #include <asm/vio.h>
 #include <asm/prom.h>
+#include <asm/firmware.h>
 
 #include "hvc_console.h"
 
@@ -120,6 +121,9 @@ static int hvc_vio_init(void)
 {
        int rc;
 
+       if (firmware_has_feature(FW_FEATURE_ISERIES))
+               return -EIO;
+
        /* Register as a vio device to receive callbacks */
        rc = vio_register_driver(&hvc_vio_driver);
 
index 77069df..1022737 100644 (file)
 
 #ifdef __KERNEL__
 
-#ifndef __ASSEMBLY__
+#include <asm/asm-compat.h>
 
 /* firmware feature bitmask values */
 #define FIRMWARE_MAX_FEATURES 63
 
-#define FW_FEATURE_PFT         (1UL<<0)
-#define FW_FEATURE_TCE         (1UL<<1)
-#define FW_FEATURE_SPRG0       (1UL<<2)
-#define FW_FEATURE_DABR                (1UL<<3)
-#define FW_FEATURE_COPY                (1UL<<4)
-#define FW_FEATURE_ASR         (1UL<<5)
-#define FW_FEATURE_DEBUG       (1UL<<6)
-#define FW_FEATURE_TERM                (1UL<<7)
-#define FW_FEATURE_PERF                (1UL<<8)
-#define FW_FEATURE_DUMP                (1UL<<9)
-#define FW_FEATURE_INTERRUPT   (1UL<<10)
-#define FW_FEATURE_MIGRATE     (1UL<<11)
-#define FW_FEATURE_PERFMON     (1UL<<12)
-#define FW_FEATURE_CRQ         (1UL<<13)
-#define FW_FEATURE_VIO         (1UL<<14)
-#define FW_FEATURE_RDMA                (1UL<<15)
-#define FW_FEATURE_LLAN                (1UL<<16)
-#define FW_FEATURE_BULK                (1UL<<17)
-#define FW_FEATURE_XDABR       (1UL<<18)
-#define FW_FEATURE_MULTITCE    (1UL<<19)
-#define FW_FEATURE_SPLPAR      (1UL<<20)
-#define FW_FEATURE_ISERIES     (1UL<<21)
-#define FW_FEATURE_LPAR                (1UL<<22)
+#define FW_FEATURE_PFT         ASM_CONST(0x0000000000000001)
+#define FW_FEATURE_TCE         ASM_CONST(0x0000000000000002)
+#define FW_FEATURE_SPRG0       ASM_CONST(0x0000000000000004)
+#define FW_FEATURE_DABR                ASM_CONST(0x0000000000000008)
+#define FW_FEATURE_COPY                ASM_CONST(0x0000000000000010)
+#define FW_FEATURE_ASR         ASM_CONST(0x0000000000000020)
+#define FW_FEATURE_DEBUG       ASM_CONST(0x0000000000000040)
+#define FW_FEATURE_TERM                ASM_CONST(0x0000000000000080)
+#define FW_FEATURE_PERF                ASM_CONST(0x0000000000000100)
+#define FW_FEATURE_DUMP                ASM_CONST(0x0000000000000200)
+#define FW_FEATURE_INTERRUPT   ASM_CONST(0x0000000000000400)
+#define FW_FEATURE_MIGRATE     ASM_CONST(0x0000000000000800)
+#define FW_FEATURE_PERFMON     ASM_CONST(0x0000000000001000)
+#define FW_FEATURE_CRQ         ASM_CONST(0x0000000000002000)
+#define FW_FEATURE_VIO         ASM_CONST(0x0000000000004000)
+#define FW_FEATURE_RDMA                ASM_CONST(0x0000000000008000)
+#define FW_FEATURE_LLAN                ASM_CONST(0x0000000000010000)
+#define FW_FEATURE_BULK                ASM_CONST(0x0000000000020000)
+#define FW_FEATURE_XDABR       ASM_CONST(0x0000000000040000)
+#define FW_FEATURE_MULTITCE    ASM_CONST(0x0000000000080000)
+#define FW_FEATURE_SPLPAR      ASM_CONST(0x0000000000100000)
+#define FW_FEATURE_ISERIES     ASM_CONST(0x0000000000200000)
+#define FW_FEATURE_LPAR                ASM_CONST(0x0000000000400000)
+
+#ifndef __ASSEMBLY__
 
 enum {
 #ifdef CONFIG_PPC64
@@ -94,6 +96,23 @@ extern void machine_check_fwnmi(void);
 /* This is true if we are using the firmware NMI handler (typically LPAR) */
 extern int fwnmi_active;
 
+#else /* __ASSEMBLY__ */
+
+#define BEGIN_FW_FTR_SECTION           96:
+
+#define END_FW_FTR_SECTION(msk, val)           \
+97:                                            \
+       .section __fw_ftr_fixup,"a";            \
+       .align 3;                               \
+       .llong msk;                             \
+       .llong val;                             \
+       .llong 96b;                             \
+       .llong 97b;                             \
+       .previous
+
+#define END_FW_FTR_SECTION_IFSET(msk)  END_FW_FTR_SECTION((msk), (msk))
+#define END_FW_FTR_SECTION_IFCLR(msk)  END_FW_FTR_SECTION((msk), 0)
+
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL__ */
 #endif /* __ASM_POWERPC_FIRMWARE_H */
diff --git a/include/asm-powerpc/immap_qe.h b/include/asm-powerpc/immap_qe.h
new file mode 100644 (file)
index 0000000..ce12f85
--- /dev/null
@@ -0,0 +1,477 @@
+/*
+ * include/asm-powerpc/immap_qe.h
+ *
+ * QUICC Engine (QE) Internal Memory Map.
+ * The Internal Memory Map for devices with QE on them. This
+ * is the superset of all QE devices (8360, etc.).
+
+ * Copyright (C) 2006. Freescale Semicondutor, Inc. All rights reserved.
+ *
+ * Authors:    Shlomi Gridish <gridish@freescale.com>
+ *             Li Yang <leoli@freescale.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef _ASM_POWERPC_IMMAP_QE_H
+#define _ASM_POWERPC_IMMAP_QE_H
+#ifdef __KERNEL__
+
+#include <linux/kernel.h>
+
+#define QE_IMMAP_SIZE  (1024 * 1024)   /* 1MB from 1MB+IMMR */
+
+/* QE I-RAM */
+struct qe_iram {
+       __be32  iadd;           /* I-RAM Address Register */
+       __be32  idata;          /* I-RAM Data Register */
+       u8      res0[0x78];
+} __attribute__ ((packed));
+
+/* QE Interrupt Controller */
+struct qe_ic_regs {
+       __be32  qicr;
+       __be32  qivec;
+       __be32  qripnr;
+       __be32  qipnr;
+       __be32  qipxcc;
+       __be32  qipycc;
+       __be32  qipwcc;
+       __be32  qipzcc;
+       __be32  qimr;
+       __be32  qrimr;
+       __be32  qicnr;
+       u8      res0[0x4];
+       __be32  qiprta;
+       __be32  qiprtb;
+       u8      res1[0x4];
+       __be32  qricr;
+       u8      res2[0x20];
+       __be32  qhivec;
+       u8      res3[0x1C];
+} __attribute__ ((packed));
+
+/* Communications Processor */
+struct cp_qe {
+       __be32  cecr;           /* QE command register */
+       __be32  ceccr;          /* QE controller configuration register */
+       __be32  cecdr;          /* QE command data register */
+       u8      res0[0xA];
+       __be16  ceter;          /* QE timer event register */
+       u8      res1[0x2];
+       __be16  cetmr;          /* QE timers mask register */
+       __be32  cetscr;         /* QE time-stamp timer control register */
+       __be32  cetsr1;         /* QE time-stamp register 1 */
+       __be32  cetsr2;         /* QE time-stamp register 2 */
+       u8      res2[0x8];
+       __be32  cevter;         /* QE virtual tasks event register */
+       __be32  cevtmr;         /* QE virtual tasks mask register */
+       __be16  cercr;          /* QE RAM control register */
+       u8      res3[0x2];
+       u8      res4[0x24];
+       __be16  ceexe1;         /* QE external request 1 event register */
+       u8      res5[0x2];
+       __be16  ceexm1;         /* QE external request 1 mask register */
+       u8      res6[0x2];
+       __be16  ceexe2;         /* QE external request 2 event register */
+       u8      res7[0x2];
+       __be16  ceexm2;         /* QE external request 2 mask register */
+       u8      res8[0x2];
+       __be16  ceexe3;         /* QE external request 3 event register */
+       u8      res9[0x2];
+       __be16  ceexm3;         /* QE external request 3 mask register */
+       u8      res10[0x2];
+       __be16  ceexe4;         /* QE external request 4 event register */
+       u8      res11[0x2];
+       __be16  ceexm4;         /* QE external request 4 mask register */
+       u8      res12[0x2];
+       u8      res13[0x280];
+} __attribute__ ((packed));
+
+/* QE Multiplexer */
+struct qe_mux {
+       __be32  cmxgcr;         /* CMX general clock route register */
+       __be32  cmxsi1cr_l;     /* CMX SI1 clock route low register */
+       __be32  cmxsi1cr_h;     /* CMX SI1 clock route high register */
+       __be32  cmxsi1syr;      /* CMX SI1 SYNC route register */
+       __be32  cmxucr1;        /* CMX UCC1, UCC3 clock route register */
+       __be32  cmxucr2;        /* CMX UCC5, UCC7 clock route register */
+       __be32  cmxucr3;        /* CMX UCC2, UCC4 clock route register */
+       __be32  cmxucr4;        /* CMX UCC6, UCC8 clock route register */
+       __be32  cmxupcr;        /* CMX UPC clock route register */
+       u8      res0[0x1C];
+} __attribute__ ((packed));
+
+/* QE Timers */
+struct qe_timers {
+       u8      gtcfr1;         /* Timer 1 and Timer 2 global config register*/
+       u8      res0[0x3];
+       u8      gtcfr2;         /* Timer 3 and timer 4 global config register*/
+       u8      res1[0xB];
+       __be16  gtmdr1;         /* Timer 1 mode register */
+       __be16  gtmdr2;         /* Timer 2 mode register */
+       __be16  gtrfr1;         /* Timer 1 reference register */
+       __be16  gtrfr2;         /* Timer 2 reference register */
+       __be16  gtcpr1;         /* Timer 1 capture register */
+       __be16  gtcpr2;         /* Timer 2 capture register */
+       __be16  gtcnr1;         /* Timer 1 counter */
+       __be16  gtcnr2;         /* Timer 2 counter */
+       __be16  gtmdr3;         /* Timer 3 mode register */
+       __be16  gtmdr4;         /* Timer 4 mode register */
+       __be16  gtrfr3;         /* Timer 3 reference register */
+       __be16  gtrfr4;         /* Timer 4 reference register */
+       __be16  gtcpr3;         /* Timer 3 capture register */
+       __be16  gtcpr4;         /* Timer 4 capture register */
+       __be16  gtcnr3;         /* Timer 3 counter */
+       __be16  gtcnr4;         /* Timer 4 counter */
+       __be16  gtevr1;         /* Timer 1 event register */
+       __be16  gtevr2;         /* Timer 2 event register */
+       __be16  gtevr3;         /* Timer 3 event register */
+       __be16  gtevr4;         /* Timer 4 event register */
+       __be16  gtps;           /* Timer 1 prescale register */
+       u8 res2[0x46];
+} __attribute__ ((packed));
+
+/* BRG */
+struct qe_brg {
+       __be32  brgc1;          /* BRG1 configuration register */
+       __be32  brgc2;          /* BRG2 configuration register */
+       __be32  brgc3;          /* BRG3 configuration register */
+       __be32  brgc4;          /* BRG4 configuration register */
+       __be32  brgc5;          /* BRG5 configuration register */
+       __be32  brgc6;          /* BRG6 configuration register */
+       __be32  brgc7;          /* BRG7 configuration register */
+       __be32  brgc8;          /* BRG8 configuration register */
+       __be32  brgc9;          /* BRG9 configuration register */
+       __be32  brgc10;         /* BRG10 configuration register */
+       __be32  brgc11;         /* BRG11 configuration register */
+       __be32  brgc12;         /* BRG12 configuration register */
+       __be32  brgc13;         /* BRG13 configuration register */
+       __be32  brgc14;         /* BRG14 configuration register */
+       __be32  brgc15;         /* BRG15 configuration register */
+       __be32  brgc16;         /* BRG16 configuration register */
+       u8      res0[0x40];
+} __attribute__ ((packed));
+
+/* SPI */
+struct spi {
+       u8      res0[0x20];
+       __be32  spmode;         /* SPI mode register */
+       u8      res1[0x2];
+       u8      spie;           /* SPI event register */
+       u8      res2[0x1];
+       u8      res3[0x2];
+       u8      spim;           /* SPI mask register */
+       u8      res4[0x1];
+       u8      res5[0x1];
+       u8      spcom;          /* SPI command register */
+       u8      res6[0x2];
+       __be32  spitd;          /* SPI transmit data register (cpu mode) */
+       __be32  spird;          /* SPI receive data register (cpu mode) */
+       u8      res7[0x8];
+} __attribute__ ((packed));
+
+/* SI */
+struct si1 {
+       __be16  siamr1;         /* SI1 TDMA mode register */
+       __be16  sibmr1;         /* SI1 TDMB mode register */
+       __be16  sicmr1;         /* SI1 TDMC mode register */
+       __be16  sidmr1;         /* SI1 TDMD mode register */
+       u8      siglmr1_h;      /* SI1 global mode register high */
+       u8      res0[0x1];
+       u8      sicmdr1_h;      /* SI1 command register high */
+       u8      res2[0x1];
+       u8      sistr1_h;       /* SI1 status register high */
+       u8      res3[0x1];
+       __be16  sirsr1_h;       /* SI1 RAM shadow address register high */
+       u8      sitarc1;        /* SI1 RAM counter Tx TDMA */
+       u8      sitbrc1;        /* SI1 RAM counter Tx TDMB */
+       u8      sitcrc1;        /* SI1 RAM counter Tx TDMC */
+       u8      sitdrc1;        /* SI1 RAM counter Tx TDMD */
+       u8      sirarc1;        /* SI1 RAM counter Rx TDMA */
+       u8      sirbrc1;        /* SI1 RAM counter Rx TDMB */
+       u8      sircrc1;        /* SI1 RAM counter Rx TDMC */
+       u8      sirdrc1;        /* SI1 RAM counter Rx TDMD */
+       u8      res4[0x8];
+       __be16  siemr1;         /* SI1 TDME mode register 16 bits */
+       __be16  sifmr1;         /* SI1 TDMF mode register 16 bits */
+       __be16  sigmr1;         /* SI1 TDMG mode register 16 bits */
+       __be16  sihmr1;         /* SI1 TDMH mode register 16 bits */
+       u8      siglmg1_l;      /* SI1 global mode register low 8 bits */
+       u8      res5[0x1];
+       u8      sicmdr1_l;      /* SI1 command register low 8 bits */
+       u8      res6[0x1];
+       u8      sistr1_l;       /* SI1 status register low 8 bits */
+       u8      res7[0x1];
+       __be16  sirsr1_l;       /* SI1 RAM shadow address register low 16 bits*/
+       u8      siterc1;        /* SI1 RAM counter Tx TDME 8 bits */
+       u8      sitfrc1;        /* SI1 RAM counter Tx TDMF 8 bits */
+       u8      sitgrc1;        /* SI1 RAM counter Tx TDMG 8 bits */
+       u8      sithrc1;        /* SI1 RAM counter Tx TDMH 8 bits */
+       u8      sirerc1;        /* SI1 RAM counter Rx TDME 8 bits */
+       u8      sirfrc1;        /* SI1 RAM counter Rx TDMF 8 bits */
+       u8      sirgrc1;        /* SI1 RAM counter Rx TDMG 8 bits */
+       u8      sirhrc1;        /* SI1 RAM counter Rx TDMH 8 bits */
+       u8      res8[0x8];
+       __be32  siml1;          /* SI1 multiframe limit register */
+       u8      siedm1;         /* SI1 extended diagnostic mode register */
+       u8      res9[0xBB];
+} __attribute__ ((packed));
+
+/* SI Routing Tables */
+struct sir {
+       u8      tx[0x400];
+       u8      rx[0x400];
+       u8      res0[0x800];
+} __attribute__ ((packed));
+
+/* USB Controller */
+struct usb_ctlr {
+       u8      usb_usmod;
+       u8      usb_usadr;
+       u8      usb_uscom;
+       u8      res1[1];
+       __be16  usb_usep1;
+       __be16  usb_usep2;
+       __be16  usb_usep3;
+       __be16  usb_usep4;
+       u8      res2[4];
+       __be16  usb_usber;
+       u8      res3[2];
+       __be16  usb_usbmr;
+       u8      res4[1];
+       u8      usb_usbs;
+       __be16  usb_ussft;
+       u8      res5[2];
+       __be16  usb_usfrn;
+       u8      res6[0x22];
+} __attribute__ ((packed));
+
+/* MCC */
+struct mcc {
+       __be32  mcce;           /* MCC event register */
+       __be32  mccm;           /* MCC mask register */
+       __be32  mccf;           /* MCC configuration register */
+       __be32  merl;           /* MCC emergency request level register */
+       u8      res0[0xF0];
+} __attribute__ ((packed));
+
+/* QE UCC Slow */
+struct ucc_slow {
+       __be32  gumr_l;         /* UCCx general mode register (low) */
+       __be32  gumr_h;         /* UCCx general mode register (high) */
+       __be16  upsmr;          /* UCCx protocol-specific mode register */
+       u8      res0[0x2];
+       __be16  utodr;          /* UCCx transmit on demand register */
+       __be16  udsr;           /* UCCx data synchronization register */
+       __be16  ucce;           /* UCCx event register */
+       u8      res1[0x2];
+       __be16  uccm;           /* UCCx mask register */
+       u8      res2[0x1];
+       u8      uccs;           /* UCCx status register */
+       u8      res3[0x24];
+       __be16  utpt;
+       u8      guemr;          /* UCC general extended mode register */
+       u8      res4[0x200 - 0x091];
+} __attribute__ ((packed));
+
+/* QE UCC Fast */
+struct ucc_fast {
+       __be32  gumr;           /* UCCx general mode register */
+       __be32  upsmr;          /* UCCx protocol-specific mode register */
+       __be16  utodr;          /* UCCx transmit on demand register */
+       u8      res0[0x2];
+       __be16  udsr;           /* UCCx data synchronization register */
+       u8      res1[0x2];
+       __be32  ucce;           /* UCCx event register */
+       __be32  uccm;           /* UCCx mask register */
+       u8      uccs;           /* UCCx status register */
+       u8      res2[0x7];
+       __be32  urfb;           /* UCC receive FIFO base */
+       __be16  urfs;           /* UCC receive FIFO size */
+       u8      res3[0x2];
+       __be16  urfet;          /* UCC receive FIFO emergency threshold */
+       __be16  urfset;         /* UCC receive FIFO special emergency
+                                  threshold */
+       __be32  utfb;           /* UCC transmit FIFO base */
+       __be16  utfs;           /* UCC transmit FIFO size */
+       u8      res4[0x2];
+       __be16  utfet;          /* UCC transmit FIFO emergency threshold */
+       u8      res5[0x2];
+       __be16  utftt;          /* UCC transmit FIFO transmit threshold */
+       u8      res6[0x2];
+       __be16  utpt;           /* UCC transmit polling timer */
+       u8      res7[0x2];
+       __be32  urtry;          /* UCC retry counter register */
+       u8      res8[0x4C];
+       u8      guemr;          /* UCC general extended mode register */
+       u8      res9[0x100 - 0x091];
+} __attribute__ ((packed));
+
+/* QE UCC */
+struct ucc_common {
+       u8      res1[0x90];
+       u8      guemr;
+       u8      res2[0x200 - 0x091];
+} __attribute__ ((packed));
+
+struct ucc {
+       union {
+               struct  ucc_slow slow;
+               struct  ucc_fast fast;
+               struct  ucc_common common;
+       };
+} __attribute__ ((packed));
+
+/* MultiPHY UTOPIA POS Controllers (UPC) */
+struct upc {
+       __be32  upgcr;          /* UTOPIA/POS general configuration register */
+       __be32  uplpa;          /* UTOPIA/POS last PHY address */
+       __be32  uphec;          /* ATM HEC register */
+       __be32  upuc;           /* UTOPIA/POS UCC configuration */
+       __be32  updc1;          /* UTOPIA/POS device 1 configuration */
+       __be32  updc2;          /* UTOPIA/POS device 2 configuration */
+       __be32  updc3;          /* UTOPIA/POS device 3 configuration */
+       __be32  updc4;          /* UTOPIA/POS device 4 configuration */
+       __be32  upstpa;         /* UTOPIA/POS STPA threshold */
+       u8      res0[0xC];
+       __be32  updrs1_h;       /* UTOPIA/POS device 1 rate select */
+       __be32  updrs1_l;       /* UTOPIA/POS device 1 rate select */
+       __be32  updrs2_h;       /* UTOPIA/POS device 2 rate select */
+       __be32  updrs2_l;       /* UTOPIA/POS device 2 rate select */
+       __be32  updrs3_h;       /* UTOPIA/POS device 3 rate select */
+       __be32  updrs3_l;       /* UTOPIA/POS device 3 rate select */
+       __be32  updrs4_h;       /* UTOPIA/POS device 4 rate select */
+       __be32  updrs4_l;       /* UTOPIA/POS device 4 rate select */
+       __be32  updrp1;         /* UTOPIA/POS device 1 receive priority low */
+       __be32  updrp2;         /* UTOPIA/POS device 2 receive priority low */
+       __be32  updrp3;         /* UTOPIA/POS device 3 receive priority low */
+       __be32  updrp4;         /* UTOPIA/POS device 4 receive priority low */
+       __be32  upde1;          /* UTOPIA/POS device 1 event */
+       __be32  upde2;          /* UTOPIA/POS device 2 event */
+       __be32  upde3;          /* UTOPIA/POS device 3 event */
+       __be32  upde4;          /* UTOPIA/POS device 4 event */
+       __be16  uprp1;
+       __be16  uprp2;
+       __be16  uprp3;
+       __be16  uprp4;
+       u8      res1[0x8];
+       __be16  uptirr1_0;      /* Device 1 transmit internal rate 0 */
+       __be16  uptirr1_1;      /* Device 1 transmit internal rate 1 */
+       __be16  uptirr1_2;      /* Device 1 transmit internal rate 2 */
+       __be16  uptirr1_3;      /* Device 1 transmit internal rate 3 */
+       __be16  uptirr2_0;      /* Device 2 transmit internal rate 0 */
+       __be16  uptirr2_1;      /* Device 2 transmit internal rate 1 */
+       __be16  uptirr2_2;      /* Device 2 transmit internal rate 2 */
+       __be16  uptirr2_3;      /* Device 2 transmit internal rate 3 */
+       __be16  uptirr3_0;      /* Device 3 transmit internal rate 0 */
+       __be16  uptirr3_1;      /* Device 3 transmit internal rate 1 */
+       __be16  uptirr3_2;      /* Device 3 transmit internal rate 2 */
+       __be16  uptirr3_3;      /* Device 3 transmit internal rate 3 */
+       __be16  uptirr4_0;      /* Device 4 transmit internal rate 0 */
+       __be16  uptirr4_1;      /* Device 4 transmit internal rate 1 */
+       __be16  uptirr4_2;      /* Device 4 transmit internal rate 2 */
+       __be16  uptirr4_3;      /* Device 4 transmit internal rate 3 */
+       __be32  uper1;          /* Device 1 port enable register */
+       __be32  uper2;          /* Device 2 port enable register */
+       __be32  uper3;          /* Device 3 port enable register */
+       __be32  uper4;          /* Device 4 port enable register */
+       u8      res2[0x150];
+} __attribute__ ((packed));
+
+/* SDMA */
+struct sdma {
+       __be32  sdsr;           /* Serial DMA status register */
+       __be32  sdmr;           /* Serial DMA mode register */
+       __be32  sdtr1;          /* SDMA system bus threshold register */
+       __be32  sdtr2;          /* SDMA secondary bus threshold register */
+       __be32  sdhy1;          /* SDMA system bus hysteresis register */
+       __be32  sdhy2;          /* SDMA secondary bus hysteresis register */
+       __be32  sdta1;          /* SDMA system bus address register */
+       __be32  sdta2;          /* SDMA secondary bus address register */
+       __be32  sdtm1;          /* SDMA system bus MSNUM register */
+       __be32  sdtm2;          /* SDMA secondary bus MSNUM register */
+       u8      res0[0x10];
+       __be32  sdaqr;          /* SDMA address bus qualify register */
+       __be32  sdaqmr;         /* SDMA address bus qualify mask register */
+       u8      res1[0x4];
+       __be32  sdebcr;         /* SDMA CAM entries base register */
+       u8      res2[0x38];
+} __attribute__ ((packed));
+
+/* Debug Space */
+struct dbg {
+       __be32  bpdcr;          /* Breakpoint debug command register */
+       __be32  bpdsr;          /* Breakpoint debug status register */
+       __be32  bpdmr;          /* Breakpoint debug mask register */
+       __be32  bprmrr0;        /* Breakpoint request mode risc register 0 */
+       __be32  bprmrr1;        /* Breakpoint request mode risc register 1 */
+       u8      res0[0x8];
+       __be32  bprmtr0;        /* Breakpoint request mode trb register 0 */
+       __be32  bprmtr1;        /* Breakpoint request mode trb register 1 */
+       u8      res1[0x8];
+       __be32  bprmir;         /* Breakpoint request mode immediate register */
+       __be32  bprmsr;         /* Breakpoint request mode serial register */
+       __be32  bpemr;          /* Breakpoint exit mode register */
+       u8      res2[0x48];
+} __attribute__ ((packed));
+
+/* RISC Special Registers (Trap and Breakpoint) */
+struct rsp {
+       u8      fixme[0x100];
+} __attribute__ ((packed));
+
+struct qe_immap {
+       struct qe_iram          iram;           /* I-RAM */
+       struct qe_ic_regs       ic;             /* Interrupt Controller */
+       struct cp_qe            cp;             /* Communications Processor */
+       struct qe_mux           qmx;            /* QE Multiplexer */
+       struct qe_timers        qet;            /* QE Timers */
+       struct spi              spi[0x2];       /* spi */
+       struct mcc              mcc;            /* mcc */
+       struct qe_brg           brg;            /* brg */
+       struct usb_ctlr         usb;            /* USB */
+       struct si1              si1;            /* SI */
+       u8                      res11[0x800];
+       struct sir              sir;            /* SI Routing Tables */
+       struct ucc              ucc1;           /* ucc1 */
+       struct ucc              ucc3;           /* ucc3 */
+       struct ucc              ucc5;           /* ucc5 */
+       struct ucc              ucc7;           /* ucc7 */
+       u8                      res12[0x600];
+       struct upc              upc1;           /* MultiPHY UTOPIA POS Ctrlr 1*/
+       struct ucc              ucc2;           /* ucc2 */
+       struct ucc              ucc4;           /* ucc4 */
+       struct ucc              ucc6;           /* ucc6 */
+       struct ucc              ucc8;           /* ucc8 */
+       u8                      res13[0x600];
+       struct upc              upc2;           /* MultiPHY UTOPIA POS Ctrlr 2*/
+       struct sdma             sdma;           /* SDMA */
+       struct dbg              dbg;            /* Debug Space */
+       struct rsp              rsp[0x2];       /* RISC Special Registers
+                                                  (Trap and Breakpoint) */
+       u8                      res14[0x300];
+       u8                      res15[0x3A00];
+       u8                      res16[0x8000];  /* 0x108000 - 0x110000 */
+       u8                      muram[0xC000];  /* 0x110000 - 0x11C000
+                                                  Multi-user RAM */
+       u8                      res17[0x24000]; /* 0x11C000 - 0x140000 */
+       u8                      res18[0xC0000]; /* 0x140000 - 0x200000 */
+} __attribute__ ((packed));
+
+extern struct qe_immap *qe_immr;
+extern phys_addr_t get_qe_base(void);
+
+static inline unsigned long immrbar_virt_to_phys(volatile void * address)
+{
+       if ( ((u32)address >= (u32)qe_immr) &&
+                       ((u32)address < ((u32)qe_immr + QE_IMMAP_SIZE)) )
+               return (unsigned long)(address - (u32)qe_immr +
+                               (u32)get_qe_base());
+       return (unsigned long)virt_to_phys(address);
+}
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_IMMAP_QE_H */
diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h
new file mode 100644 (file)
index 0000000..a62168e
--- /dev/null
@@ -0,0 +1,457 @@
+/*
+ * Copyright (C) 2006