mtd: omap2: use busy pin monitoring

diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 713cb64..f33f5b1 100644 (file)
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -92,6 +92,7 @@ static struct omap_nand_platform_data pandora_nand_data = {
        .xfer_type      = NAND_OMAP_PREFETCH_DMA,
        .parts          = omap3pandora_nand_partitions,
        .nr_parts       = ARRAY_SIZE(omap3pandora_nand_partitions),
+       .dev_ready      = true,
 };
 
 static struct gpio_led pandora_gpio_leds[] = {

diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 8ad210b..0ebc8a1 100644 (file)
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -102,11 +102,6 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
                return err;
        }
 
-       /* Enable RD PIN Monitoring Reg */
-       if (gpmc_nand_data->dev_ready) {
-               gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1);
-       }
-
        err = platform_device_register(&gpmc_nand_device);
        if (err < 0) {
                dev_err(dev, "Unable to register NAND device\n");

diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index dfffbbf..82979d2 100644 (file)
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -480,6 +480,11 @@ int gpmc_read_status(int cmd)
                status = regval & GPMC_STATUS_BUFF_EMPTY;
                break;
 
+       case GPMC_STATUS_WAIT:
+               regval = gpmc_read_reg(GPMC_STATUS);
+               status = regval & 0x100;
+               break;
+
        default:
                printk(KERN_ERR "gpmc_read_status: Not supported\n");
        }

diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index 1527929..1340e37 100644 (file)
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -36,6 +36,7 @@
 #define GPMC_PREFETCH_FIFO_CNT 0x00000007 /* bytes available in FIFO for r/w */
 #define GPMC_PREFETCH_COUNT    0x00000008 /* remaining bytes to be read/write*/
 #define GPMC_STATUS_BUFFER     0x00000009 /* 1: buffer is available to write */
+#define GPMC_STATUS_WAIT       0x0000000e
 
 #define GPMC_NAND_COMMAND      0x0000000a
 #define GPMC_NAND_ADDRESS      0x0000000b

diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index f34e440..7f0d34b 100644 (file)
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -869,26 +869,7 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
  */
 static int omap_dev_ready(struct mtd_info *mtd)
 {
-       unsigned int val = 0;
-       struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
-                                                       mtd);
-
-       val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
-       if ((val & 0x100) == 0x100) {
-               /* Clear IRQ Interrupt */
-               val |= 0x100;
-               val &= ~(0x0);
-               gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, val);
-       } else {
-               unsigned int cnt = 0;
-               while (cnt++ < 0x1FF) {
-                       if  ((val & 0x100) == 0x100)
-                               return 0;
-                       val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
-               }
-       }
-
-       return 1;
+       return !!gpmc_read_status(GPMC_STATUS_WAIT);
 }
 
 static int __devinit omap_nand_probe(struct platform_device *pdev)