This adds an option to allow userspace access to the performance monitor
registers of the Cortex-A8.
Signed-off-by: Mans Rullgard <mans@mansr.com>
help
Enable userspace access to the L2 preload engine (PLE) available
in Cortex-A series ARM processors.
+
+config USER_PMON
+ bool "Enable userspace access to performance counters"
+ depends on CPU_V7
+ default n
+ help
+ Enable userspace access to the performance monitor registers.
mov r10, #0x1f @ domains 0, 1 = manager
mcr p15, 0, r10, c3, c0, 0 @ load domain access register
#endif
+
+#ifdef CONFIG_USER_PMON
+ mov r0, #1
+ mcr p15, 0, r0, c9, c14, 0
+#endif
+
adr r5, v7_crval
ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0, 0 @ read control register