EDAC, amd64_edac: Shift wrapping issue in f1x_get_norm_dct_addr()
authorDan Carpenter <dan.carpenter@oracle.com>
Wed, 20 Jan 2016 09:54:51 +0000 (12:54 +0300)
committerBen Hutchings <ben@decadent.org.uk>
Sat, 30 Apr 2016 22:05:14 +0000 (00:05 +0200)
commite0d2e02bdbc134227459f0feccc7fa6a14b50966
tree592edd3470ae8d232259dde0eb747b3d880d4f4a
parent161802562b8b7f546a4deafeb73f31f0afc7bd1e
EDAC, amd64_edac: Shift wrapping issue in f1x_get_norm_dct_addr()

commit 6f3508f61c814ee852c199988a62bd954c50dfc1 upstream.

dct_sel_base_off is declared as a u64 but we're only using the lower 32
bits because of a shift wrapping bug. This can possibly truncate the
upper 16 bits of DctSelBaseOffset[47:26], causing us to misdecode the CS
row.

Fixes: c8e518d5673d ('amd64_edac: Sanitize f10_get_base_addr_offset')
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Cc: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/20160120095451.GB19898@mwanda
Signed-off-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
drivers/edac/amd64_edac.c