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[POWERPC] 4xx: Clear new TLB cache attribute bits in Data Storage vector
authorJosh Boyer <jwboyer@linux.vnet.ibm.com>
Tue, 17 Jun 2008 22:34:39 +0000 (08:34 +1000)
committerPaul Mackerras <paulus@samba.org>
Wed, 18 Jun 2008 11:40:43 +0000 (21:40 +1000)
commitb17879f71c2eb4a10f5a63918819d9d572b23a9a
tree9a23e42f6d0aedaa2e8049d0338650a10934903btree | snapshot
parent952f4a0a9b27e6dbd5d32e330b3f609ebfa0b061commit | diff
[POWERPC] 4xx: Clear new TLB cache attribute bits in Data Storage vector

A recent commit added support for the new 440x6 and 464 cores that have the
added WL1, IL1I, IL1D, IL2I, and ILD2 bits for the caching attributes in the
TLBs.  The new bits were cleared in the finish_tlb_load function, however a
similar bit of code was missed in the DataStorage interrupt vector.

Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
arch/powerpc/kernel/head_44x.S diff | blob | history
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