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(parent: d8201ab) | patch
drm/i915: Add CxSR support on Pineview DDR3
authorLi Peng <peng.li@linux.intel.com>
Tue, 18 May 2010 10:58:44 +0000 (18:58 +0800)
committerEric Anholt <eric@anholt.net>
Wed, 26 May 2010 21:22:51 +0000 (14:22 -0700)
commit9553426372eef71c849499fb1d232f4b0577c0f9
tree8df1e5e08fd759c2c7279c232ef7e6732a3e65dbtree | snapshot
parentd8201ab6514f8dc1a0ccfac52c688d80976a425acommit | diff
drm/i915: Add CxSR support on Pineview DDR3

Pineview with DDR3 memory has different latencies to enable CxSR.
This patch updates CxSR latency table to add Pineview DDR3 latency
configuration. It also adds one flag "is_ddr3" for checking DDR3
setting in MCHBAR.

Cc: Shaohua Li <shaohua.li@intel.com>
Cc: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Li Peng <peng.li@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
drivers/gpu/drm/i915/i915_dma.c diff | blob | history
drivers/gpu/drm/i915/i915_drv.h diff | blob | history
drivers/gpu/drm/i915/i915_reg.h diff | blob | history
drivers/gpu/drm/i915/intel_display.c diff | blob | history
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