x86, cacheinfo: Reorganize AMD L3 cache structure
authorBorislav Petkov <borislav.petkov@amd.com>
Thu, 22 Apr 2010 14:07:00 +0000 (16:07 +0200)
committerH. Peter Anvin <hpa@zytor.com>
Fri, 23 Apr 2010 00:17:23 +0000 (17:17 -0700)
commit9350f982e4fe539e83a2d4a13e9b53ad8253c4a8
tree4ee595d0ba964446b2b06c026cbc6964e3ce2cdc
parentf2b20e41407fccfcfacf927ff91ec888832a37af
x86, cacheinfo: Reorganize AMD L3 cache structure

Add a struct representing L3 cache attributes (subcache sizes and
indices count) and move the respective members out of _cpuid4_info.
Also, stash the struct pci_dev ptr into the struct simplifying the code
even more.

There should be no functionality change resulting from this patch except
slightly slimming the _cpuid4_info per-cpu vars.

Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
LKML-Reference: <1271945222-5283-4-git-send-email-bp@amd64.org>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
arch/x86/kernel/cpu/intel_cacheinfo.c