perf/x86: Fix offcore_rsp valid mask for SNB/IVB
authorStephane Eranian <eranian@google.com>
Tue, 16 Apr 2013 11:51:43 +0000 (13:51 +0200)
committerBen Hutchings <ben@decadent.org.uk>
Mon, 13 May 2013 14:02:33 +0000 (15:02 +0100)
commit4fcd6db795fa0f317deb7b64cce89ca2502ff934
tree9d5c5b59efe142491b99b4431d838b42e85c214d
parent3fc8fc1cc2d585c1f695f7de914063258aafe50e
perf/x86: Fix offcore_rsp valid mask for SNB/IVB

commit f1923820c447e986a9da0fc6bf60c1dccdf0408e upstream.

The valid mask for both offcore_response_0 and
offcore_response_1 was wrong for SNB/SNB-EP,
IVB/IVB-EP. It was possible to write to
reserved bit and cause a GP fault crashing
the kernel.

This patch fixes the problem by correctly marking the
reserved bits in the valid mask for all the processors
mentioned above.

A distinction between desktop and server parts is introduced
because bits 24-30 are only available on the server parts.

This version of the  patch is just a rebase to perf/urgent tree
and should apply to older kernels as well.

Signed-off-by: Stephane Eranian <eranian@google.com>
Cc: peterz@infradead.org
Cc: jolsa@redhat.com
Cc: gregkh@linuxfoundation.org
Cc: security@kernel.org
Cc: ak@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
[bwh: Backported to 3.2: adjust context; drop the IVB case]
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
arch/x86/kernel/cpu/perf_event_intel.c