X-Git-Url: https://git.openpandora.org/cgi-bin/gitweb.cgi?p=pandora-kernel.git;a=blobdiff_plain;f=drivers%2Fnet%2Fwireless%2Fiwlwifi%2Fiwl-io.c;h=3ffa8e62b8565e442394083fad92a2c9c6fa6ad7;hp=aa4a90674452ef218c68262d748e835a9b9bc2be;hb=83ed90155f98bd949735c2cc22d832b557a6d7d1;hpb=a72b8b088c3465b28192c1a14ba97be8223a8cec diff --git a/drivers/net/wireless/iwlwifi/iwl-io.c b/drivers/net/wireless/iwlwifi/iwl-io.c index aa4a90674452..3ffa8e62b856 100644 --- a/drivers/net/wireless/iwlwifi/iwl-io.c +++ b/drivers/net/wireless/iwlwifi/iwl-io.c @@ -25,46 +25,50 @@ * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 * *****************************************************************************/ +#include +#include #include "iwl-io.h" +#include"iwl-csr.h" +#include "iwl-debug.h" #define IWL_POLL_INTERVAL 10 /* microseconds */ -static inline void __iwl_set_bit(struct iwl_priv *priv, u32 reg, u32 mask) +static inline void __iwl_set_bit(struct iwl_bus *bus, u32 reg, u32 mask) { - iwl_write32(priv, reg, iwl_read32(priv, reg) | mask); + iwl_write32(bus, reg, iwl_read32(bus, reg) | mask); } -static inline void __iwl_clear_bit(struct iwl_priv *priv, u32 reg, u32 mask) +static inline void __iwl_clear_bit(struct iwl_bus *bus, u32 reg, u32 mask) { - iwl_write32(priv, reg, iwl_read32(priv, reg) & ~mask); + iwl_write32(bus, reg, iwl_read32(bus, reg) & ~mask); } -void iwl_set_bit(struct iwl_priv *priv, u32 reg, u32 mask) +void iwl_set_bit(struct iwl_bus *bus, u32 reg, u32 mask) { unsigned long flags; - spin_lock_irqsave(&priv->reg_lock, flags); - __iwl_set_bit(priv, reg, mask); - spin_unlock_irqrestore(&priv->reg_lock, flags); + spin_lock_irqsave(&bus->reg_lock, flags); + __iwl_set_bit(bus, reg, mask); + spin_unlock_irqrestore(&bus->reg_lock, flags); } -void iwl_clear_bit(struct iwl_priv *priv, u32 reg, u32 mask) +void iwl_clear_bit(struct iwl_bus *bus, u32 reg, u32 mask) { unsigned long flags; - spin_lock_irqsave(&priv->reg_lock, flags); - __iwl_clear_bit(priv, reg, mask); - spin_unlock_irqrestore(&priv->reg_lock, flags); + spin_lock_irqsave(&bus->reg_lock, flags); + __iwl_clear_bit(bus, reg, mask); + spin_unlock_irqrestore(&bus->reg_lock, flags); } -int iwl_poll_bit(struct iwl_priv *priv, u32 addr, +int iwl_poll_bit(struct iwl_bus *bus, u32 addr, u32 bits, u32 mask, int timeout) { int t = 0; do { - if ((iwl_read32(priv, addr) & mask) == (bits & mask)) + if ((iwl_read32(bus, addr) & mask) == (bits & mask)) return t; udelay(IWL_POLL_INTERVAL); t += IWL_POLL_INTERVAL; @@ -73,14 +77,14 @@ int iwl_poll_bit(struct iwl_priv *priv, u32 addr, return -ETIMEDOUT; } -int iwl_grab_nic_access_silent(struct iwl_priv *priv) +int iwl_grab_nic_access_silent(struct iwl_bus *bus) { int ret; - lockdep_assert_held(&priv->reg_lock); + lockdep_assert_held(&bus->reg_lock); /* this bit wakes up the NIC */ - __iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); + __iwl_set_bit(bus, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); /* * These bits say the device is running, and should keep running for @@ -101,70 +105,70 @@ int iwl_grab_nic_access_silent(struct iwl_priv *priv) * 5000 series and later (including 1000 series) have non-volatile SRAM, * and do not save/restore SRAM when power cycling. */ - ret = iwl_poll_bit(priv, CSR_GP_CNTRL, + ret = iwl_poll_bit(bus, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); if (ret < 0) { - iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); + iwl_write32(bus, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); return -EIO; } return 0; } -int iwl_grab_nic_access(struct iwl_priv *priv) +int iwl_grab_nic_access(struct iwl_bus *bus) { - int ret = iwl_grab_nic_access_silent(priv); + int ret = iwl_grab_nic_access_silent(bus); if (ret) { - u32 val = iwl_read32(priv, CSR_GP_CNTRL); - IWL_ERR(priv, + u32 val = iwl_read32(bus, CSR_GP_CNTRL); + IWL_ERR(bus, "MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val); } return ret; } -void iwl_release_nic_access(struct iwl_priv *priv) +void iwl_release_nic_access(struct iwl_bus *bus) { - lockdep_assert_held(&priv->reg_lock); - __iwl_clear_bit(priv, CSR_GP_CNTRL, + lockdep_assert_held(&bus->reg_lock); + __iwl_clear_bit(bus, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); } -u32 iwl_read_direct32(struct iwl_priv *priv, u32 reg) +u32 iwl_read_direct32(struct iwl_bus *bus, u32 reg) { u32 value; unsigned long flags; - spin_lock_irqsave(&priv->reg_lock, flags); - iwl_grab_nic_access(priv); - value = iwl_read32(priv, reg); - iwl_release_nic_access(priv); - spin_unlock_irqrestore(&priv->reg_lock, flags); + spin_lock_irqsave(&bus->reg_lock, flags); + iwl_grab_nic_access(bus); + value = iwl_read32(bus(bus), reg); + iwl_release_nic_access(bus); + spin_unlock_irqrestore(&bus->reg_lock, flags); return value; } -void iwl_write_direct32(struct iwl_priv *priv, u32 reg, u32 value) +void iwl_write_direct32(struct iwl_bus *bus, u32 reg, u32 value) { unsigned long flags; - spin_lock_irqsave(&priv->reg_lock, flags); - if (!iwl_grab_nic_access(priv)) { - iwl_write32(priv, reg, value); - iwl_release_nic_access(priv); + spin_lock_irqsave(&bus->reg_lock, flags); + if (!iwl_grab_nic_access(bus)) { + iwl_write32(bus, reg, value); + iwl_release_nic_access(bus); } - spin_unlock_irqrestore(&priv->reg_lock, flags); + spin_unlock_irqrestore(&bus->reg_lock, flags); } -int iwl_poll_direct_bit(struct iwl_priv *priv, u32 addr, u32 mask, +int iwl_poll_direct_bit(struct iwl_bus *bus, u32 addr, u32 mask, int timeout) { int t = 0; do { - if ((iwl_read_direct32(priv, addr) & mask) == mask) + if ((iwl_read_direct32(bus, addr) & mask) == mask) return t; udelay(IWL_POLL_INTERVAL); t += IWL_POLL_INTERVAL; @@ -173,122 +177,122 @@ int iwl_poll_direct_bit(struct iwl_priv *priv, u32 addr, u32 mask, return -ETIMEDOUT; } -static inline u32 __iwl_read_prph(struct iwl_priv *priv, u32 reg) +static inline u32 __iwl_read_prph(struct iwl_bus *bus, u32 reg) { - iwl_write32(priv, HBUS_TARG_PRPH_RADDR, reg | (3 << 24)); + iwl_write32(bus, HBUS_TARG_PRPH_RADDR, reg | (3 << 24)); rmb(); - return iwl_read32(priv, HBUS_TARG_PRPH_RDAT); + return iwl_read32(bus, HBUS_TARG_PRPH_RDAT); } -static inline void __iwl_write_prph(struct iwl_priv *priv, u32 addr, u32 val) +static inline void __iwl_write_prph(struct iwl_bus *bus, u32 addr, u32 val) { - iwl_write32(priv, HBUS_TARG_PRPH_WADDR, + iwl_write32(bus, HBUS_TARG_PRPH_WADDR, ((addr & 0x0000FFFF) | (3 << 24))); wmb(); - iwl_write32(priv, HBUS_TARG_PRPH_WDAT, val); + iwl_write32(bus, HBUS_TARG_PRPH_WDAT, val); } -u32 iwl_read_prph(struct iwl_priv *priv, u32 reg) +u32 iwl_read_prph(struct iwl_bus *bus, u32 reg) { unsigned long flags; u32 val; - spin_lock_irqsave(&priv->reg_lock, flags); - iwl_grab_nic_access(priv); - val = __iwl_read_prph(priv, reg); - iwl_release_nic_access(priv); - spin_unlock_irqrestore(&priv->reg_lock, flags); + spin_lock_irqsave(&bus->reg_lock, flags); + iwl_grab_nic_access(bus); + val = __iwl_read_prph(bus, reg); + iwl_release_nic_access(bus); + spin_unlock_irqrestore(&bus->reg_lock, flags); return val; } -void iwl_write_prph(struct iwl_priv *priv, u32 addr, u32 val) +void iwl_write_prph(struct iwl_bus *bus, u32 addr, u32 val) { unsigned long flags; - spin_lock_irqsave(&priv->reg_lock, flags); - if (!iwl_grab_nic_access(priv)) { - __iwl_write_prph(priv, addr, val); - iwl_release_nic_access(priv); + spin_lock_irqsave(&bus->reg_lock, flags); + if (!iwl_grab_nic_access(bus)) { + __iwl_write_prph(bus, addr, val); + iwl_release_nic_access(bus); } - spin_unlock_irqrestore(&priv->reg_lock, flags); + spin_unlock_irqrestore(&bus->reg_lock, flags); } -void iwl_set_bits_prph(struct iwl_priv *priv, u32 reg, u32 mask) +void iwl_set_bits_prph(struct iwl_bus *bus, u32 reg, u32 mask) { unsigned long flags; - spin_lock_irqsave(&priv->reg_lock, flags); - iwl_grab_nic_access(priv); - __iwl_write_prph(priv, reg, __iwl_read_prph(priv, reg) | mask); - iwl_release_nic_access(priv); - spin_unlock_irqrestore(&priv->reg_lock, flags); + spin_lock_irqsave(&bus->reg_lock, flags); + iwl_grab_nic_access(bus); + __iwl_write_prph(bus, reg, __iwl_read_prph(bus, reg) | mask); + iwl_release_nic_access(bus); + spin_unlock_irqrestore(&bus->reg_lock, flags); } -void iwl_set_bits_mask_prph(struct iwl_priv *priv, u32 reg, +void iwl_set_bits_mask_prph(struct iwl_bus *bus, u32 reg, u32 bits, u32 mask) { unsigned long flags; - spin_lock_irqsave(&priv->reg_lock, flags); - iwl_grab_nic_access(priv); - __iwl_write_prph(priv, reg, - (__iwl_read_prph(priv, reg) & mask) | bits); - iwl_release_nic_access(priv); - spin_unlock_irqrestore(&priv->reg_lock, flags); + spin_lock_irqsave(&bus->reg_lock, flags); + iwl_grab_nic_access(bus); + __iwl_write_prph(bus, reg, + (__iwl_read_prph(bus, reg) & mask) | bits); + iwl_release_nic_access(bus); + spin_unlock_irqrestore(&bus->reg_lock, flags); } -void iwl_clear_bits_prph(struct iwl_priv *priv, u32 reg, u32 mask) +void iwl_clear_bits_prph(struct iwl_bus *bus, u32 reg, u32 mask) { unsigned long flags; u32 val; - spin_lock_irqsave(&priv->reg_lock, flags); - iwl_grab_nic_access(priv); - val = __iwl_read_prph(priv, reg); - __iwl_write_prph(priv, reg, (val & ~mask)); - iwl_release_nic_access(priv); - spin_unlock_irqrestore(&priv->reg_lock, flags); + spin_lock_irqsave(&bus->reg_lock, flags); + iwl_grab_nic_access(bus); + val = __iwl_read_prph(bus, reg); + __iwl_write_prph(bus, reg, (val & ~mask)); + iwl_release_nic_access(bus); + spin_unlock_irqrestore(&bus->reg_lock, flags); } -void _iwl_read_targ_mem_words(struct iwl_priv *priv, u32 addr, +void _iwl_read_targ_mem_words(struct iwl_bus *bus, u32 addr, void *buf, int words) { unsigned long flags; int offs; u32 *vals = buf; - spin_lock_irqsave(&priv->reg_lock, flags); - iwl_grab_nic_access(priv); + spin_lock_irqsave(&bus->reg_lock, flags); + iwl_grab_nic_access(bus); - iwl_write32(priv, HBUS_TARG_MEM_RADDR, addr); + iwl_write32(bus, HBUS_TARG_MEM_RADDR, addr); rmb(); for (offs = 0; offs < words; offs++) - vals[offs] = iwl_read32(priv, HBUS_TARG_MEM_RDAT); + vals[offs] = iwl_read32(bus, HBUS_TARG_MEM_RDAT); - iwl_release_nic_access(priv); - spin_unlock_irqrestore(&priv->reg_lock, flags); + iwl_release_nic_access(bus); + spin_unlock_irqrestore(&bus->reg_lock, flags); } -u32 iwl_read_targ_mem(struct iwl_priv *priv, u32 addr) +u32 iwl_read_targ_mem(struct iwl_bus *bus, u32 addr) { u32 value; - _iwl_read_targ_mem_words(priv, addr, &value, 1); + _iwl_read_targ_mem_words(bus, addr, &value, 1); return value; } -void iwl_write_targ_mem(struct iwl_priv *priv, u32 addr, u32 val) +void iwl_write_targ_mem(struct iwl_bus *bus, u32 addr, u32 val) { unsigned long flags; - spin_lock_irqsave(&priv->reg_lock, flags); - if (!iwl_grab_nic_access(priv)) { - iwl_write32(priv, HBUS_TARG_MEM_WADDR, addr); + spin_lock_irqsave(&bus->reg_lock, flags); + if (!iwl_grab_nic_access(bus)) { + iwl_write32(bus, HBUS_TARG_MEM_WADDR, addr); wmb(); - iwl_write32(priv, HBUS_TARG_MEM_WDAT, val); - iwl_release_nic_access(priv); + iwl_write32(bus, HBUS_TARG_MEM_WDAT, val); + iwl_release_nic_access(bus); } - spin_unlock_irqrestore(&priv->reg_lock, flags); + spin_unlock_irqrestore(&bus->reg_lock, flags); }