X-Git-Url: https://git.openpandora.org/cgi-bin/gitweb.cgi?p=pandora-kernel.git;a=blobdiff_plain;f=arch%2Fsh%2Fboards%2Fboard-sh7785lcr.c;h=42410a15d2552762a13604f37e9985dabb7d027d;hp=6f94f17adc467dd00d13aaa20ef5891b2ee064ed;hb=df36b439c5fedefe013d4449cb6a50d15e2f4d70;hpb=72e31981a4e91f84c5b5e8994f5d25b1cf22b6cf diff --git a/arch/sh/boards/board-sh7785lcr.c b/arch/sh/boards/board-sh7785lcr.c index 6f94f17adc46..42410a15d255 100644 --- a/arch/sh/boards/board-sh7785lcr.c +++ b/arch/sh/boards/board-sh7785lcr.c @@ -2,12 +2,12 @@ * Renesas Technology Corp. R0P7785LC0011RL Support. * * Copyright (C) 2008 Yoshihiro Shimoda + * Copyright (C) 2009 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. */ - #include #include #include @@ -15,12 +15,18 @@ #include #include #include +#include #include #include #include +#include #include -#include +#include +#include #include +#include +#include +#include /* * NOTE: This board has 2 physical memory maps. @@ -94,18 +100,21 @@ static struct platform_device nor_flash_device = { .resource = nor_flash_resources, }; +static struct r8a66597_platdata r8a66597_data = { + .xtal = R8A66597_PLATDATA_XTAL_12MHZ, + .vif = 1, +}; + static struct resource r8a66597_usb_host_resources[] = { [0] = { - .name = "r8a66597_hcd", .start = R8A66597_ADDR, .end = R8A66597_ADDR + R8A66597_SIZE - 1, .flags = IORESOURCE_MEM, }, [1] = { - .name = "r8a66597_hcd", .start = 2, .end = 2, - .flags = IORESOURCE_IRQ, + .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, }, }; @@ -115,6 +124,7 @@ static struct platform_device r8a66597_usb_host_device = { .dev = { .dma_mask = NULL, .coherent_dma_mask = 0xffffffff, + .platform_data = &r8a66597_data, }, .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources), .resource = r8a66597_usb_host_resources, @@ -273,6 +283,20 @@ void __init init_sh7785lcr_IRQ(void) plat_irq_setup_pins(IRQ_MODE_IRQ3210); } +static int sh7785lcr_clk_init(void) +{ + struct clk *clk; + int ret; + + clk = clk_get(NULL, "extal"); + if (!clk || IS_ERR(clk)) + return PTR_ERR(clk); + ret = clk_set_rate(clk, 33333333); + clk_put(clk); + + return ret; +} + static void sh7785lcr_power_off(void) { unsigned char *p; @@ -303,12 +327,34 @@ static void __init sh7785lcr_setup(char **cmdline_p) writel(0x000307c2, sm501_reg); } +/* Return the board specific boot mode pin configuration */ +static int sh7785lcr_mode_pins(void) +{ + int value = 0; + + /* These are the factory default settings of S1 and S2. + * If you change these dip switches then you will need to + * adjust the values below as well. + */ + value |= MODE_PIN4; /* Clock Mode 16 */ + value |= MODE_PIN5; /* 32-bit Area0 bus width */ + value |= MODE_PIN6; /* 32-bit Area0 bus width */ + value |= MODE_PIN7; /* Area 0 SRAM interface [fixed] */ + value |= MODE_PIN8; /* Little Endian */ + value |= MODE_PIN9; /* Master Mode */ + value |= MODE_PIN14; /* No PLL step-up */ + + return value; +} + /* * The Machine Vector */ static struct sh_machine_vector mv_sh7785lcr __initmv = { .mv_name = "SH7785LCR", .mv_setup = sh7785lcr_setup, + .mv_clk_init = sh7785lcr_clk_init, .mv_init_irq = init_sh7785lcr_IRQ, + .mv_mode_pins = sh7785lcr_mode_pins, };