X-Git-Url: https://git.openpandora.org/cgi-bin/gitweb.cgi?p=pandora-kernel.git;a=blobdiff_plain;f=arch%2Farm%2Fmach-omap2%2Fomap_hwmod_3xxx_data.c;h=34b2dfa5104e809ee82a06a7df1b98ec13dfe227;hp=7f8915ad50990b1af2e877ed169c32cd0d15cd02;hb=40d3e984595c7bd2557e232d86fbfb4ddb96d370;hpb=f9143eae1035195352da7577d89ec5982cbc9f72 diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 7f8915ad5099..34b2dfa5104e 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -29,6 +29,7 @@ #include "omap_hwmod_common_data.h" +#include "smartreflex.h" #include "prm-regbits-34xx.h" #include "cm-regbits-34xx.h" #include "wd_timer.h" @@ -65,7 +66,9 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod; static struct omap_hwmod omap3xxx_gpio5_hwmod; static struct omap_hwmod omap3xxx_gpio6_hwmod; static struct omap_hwmod omap34xx_sr1_hwmod; +static struct omap_hwmod omap36xx_sr1_hwmod; static struct omap_hwmod omap34xx_sr2_hwmod; +static struct omap_hwmod omap36xx_sr2_hwmod; static struct omap_hwmod omap34xx_mcspi1; static struct omap_hwmod omap34xx_mcspi2; static struct omap_hwmod omap34xx_mcspi3; @@ -163,7 +166,7 @@ static struct omap_hwmod omap3xxx_l4_wkup_hwmod; static struct omap_hwmod omap3xxx_uart1_hwmod; static struct omap_hwmod omap3xxx_uart2_hwmod; static struct omap_hwmod omap3xxx_uart3_hwmod; -static struct omap_hwmod omap3xxx_uart4_hwmod; +static struct omap_hwmod omap36xx_uart4_hwmod; static struct omap_hwmod omap3xxx_usbhsotg_hwmod; /* l3_core -> usbhsotg interface */ @@ -282,7 +285,7 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { }; /* L4 PER -> UART4 interface */ -static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = { +static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = { { .pa_start = OMAP3_UART4_BASE, .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, @@ -291,11 +294,11 @@ static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = { { } }; -static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = { +static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = { .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_uart4_hwmod, + .slave = &omap36xx_uart4_hwmod, .clk = "uart4_ick", - .addr = omap3xxx_uart4_addr_space, + .addr = omap36xx_uart4_addr_space, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -356,6 +359,16 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = { + { .irq = 18}, + { .irq = -1 } +}; + +static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = { + { .irq = 19}, + { .irq = -1 } +}; + /* L4 CORE -> SR1 interface */ static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { { @@ -366,7 +379,7 @@ static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { { } }; -static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = { +static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = { .master = &omap3xxx_l4_core_hwmod, .slave = &omap34xx_sr1_hwmod, .clk = "sr_l4_ick", @@ -374,6 +387,14 @@ static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = { .user = OCP_USER_MPU, }; +static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap36xx_sr1_hwmod, + .clk = "sr_l4_ick", + .addr = omap3_sr1_addr_space, + .user = OCP_USER_MPU, +}; + /* L4 CORE -> SR1 interface */ static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { { @@ -384,7 +405,7 @@ static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { { } }; -static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = { +static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = { .master = &omap3xxx_l4_core_hwmod, .slave = &omap34xx_sr2_hwmod, .clk = "sr_l4_ick", @@ -392,6 +413,14 @@ static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = { .user = OCP_USER_MPU, }; +static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap36xx_sr2_hwmod, + .clk = "sr_l4_ick", + .addr = omap3_sr2_addr_space, + .user = OCP_USER_MPU, +}; + /* * usbhsotg interface data */ @@ -1067,7 +1096,7 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = { .class = &omap3xxx_timer_hwmod_class, }; -/* timer12*/ +/* timer12 */ static struct omap_hwmod omap3xxx_timer12_hwmod; static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { { .irq = 95, }, @@ -1287,14 +1316,15 @@ static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { }; static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = { - &omap3_l4_per__uart4, + &omap36xx_l4_per__uart4, }; -static struct omap_hwmod omap3xxx_uart4_hwmod = { +static struct omap_hwmod omap36xx_uart4_hwmod = { .name = "uart4", .mpu_irqs = uart4_mpu_irqs, .sdma_reqs = uart4_sdma_reqs, .main_clk = "uart4_fck", + .flags = HWMOD_SWSUP_SIDLE, .prcm = { .omap2 = { .module_offs = OMAP3430_PER_MOD, @@ -1426,6 +1456,28 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = { .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), }; +/* + * 'dispc' class + * display controller + */ + +static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | + SYSC_HAS_ENAWAKEUP), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3_dispc_hwmod_class = { + .name = "dispc", + .sysc = &omap3_dispc_sysc, +}; + /* l4_core -> dss_dispc */ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { .master = &omap3xxx_l4_core_hwmod, @@ -1449,7 +1501,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = { static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { .name = "dss_dispc", - .class = &omap2_dispc_hwmod_class, + .class = &omap3_dispc_hwmod_class, .mpu_irqs = omap2_dispc_irqs, .main_clk = "dss1_alwon_fck", .prcm = { @@ -2588,15 +2640,18 @@ static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = { }; /* SR1 */ -static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = { - &omap3_l4_core__sr1, +static struct omap_smartreflex_dev_attr sr1_dev_attr = { + .sensor_voltdm_name = "mpu_iva", +}; + +static struct omap_hwmod_ocp_if *omap34xx_sr1_slaves[] = { + &omap34xx_l4_core__sr1, }; static struct omap_hwmod omap34xx_sr1_hwmod = { - .name = "sr1_hwmod", + .name = "sr1", .class = &omap34xx_smartreflex_hwmod_class, .main_clk = "sr1_fck", - .vdd_name = "mpu_iva", .prcm = { .omap2 = { .prcm_reg_id = 1, @@ -2606,16 +2661,21 @@ static struct omap_hwmod omap34xx_sr1_hwmod = { .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, }, }, - .slaves = omap3_sr1_slaves, - .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves), + .slaves = omap34xx_sr1_slaves, + .slaves_cnt = ARRAY_SIZE(omap34xx_sr1_slaves), + .dev_attr = &sr1_dev_attr, + .mpu_irqs = omap3_smartreflex_mpu_irqs, .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; +static struct omap_hwmod_ocp_if *omap36xx_sr1_slaves[] = { + &omap36xx_l4_core__sr1, +}; + static struct omap_hwmod omap36xx_sr1_hwmod = { - .name = "sr1_hwmod", + .name = "sr1", .class = &omap36xx_smartreflex_hwmod_class, .main_clk = "sr1_fck", - .vdd_name = "mpu_iva", .prcm = { .omap2 = { .prcm_reg_id = 1, @@ -2625,20 +2685,25 @@ static struct omap_hwmod omap36xx_sr1_hwmod = { .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, }, }, - .slaves = omap3_sr1_slaves, - .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves), + .slaves = omap36xx_sr1_slaves, + .slaves_cnt = ARRAY_SIZE(omap36xx_sr1_slaves), + .dev_attr = &sr1_dev_attr, + .mpu_irqs = omap3_smartreflex_mpu_irqs, }; /* SR2 */ -static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = { - &omap3_l4_core__sr2, +static struct omap_smartreflex_dev_attr sr2_dev_attr = { + .sensor_voltdm_name = "core", +}; + +static struct omap_hwmod_ocp_if *omap34xx_sr2_slaves[] = { + &omap34xx_l4_core__sr2, }; static struct omap_hwmod omap34xx_sr2_hwmod = { - .name = "sr2_hwmod", + .name = "sr2", .class = &omap34xx_smartreflex_hwmod_class, .main_clk = "sr2_fck", - .vdd_name = "core", .prcm = { .omap2 = { .prcm_reg_id = 1, @@ -2648,16 +2713,21 @@ static struct omap_hwmod omap34xx_sr2_hwmod = { .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, }, }, - .slaves = omap3_sr2_slaves, - .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves), + .slaves = omap34xx_sr2_slaves, + .slaves_cnt = ARRAY_SIZE(omap34xx_sr2_slaves), + .dev_attr = &sr2_dev_attr, + .mpu_irqs = omap3_smartreflex_core_irqs, .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; +static struct omap_hwmod_ocp_if *omap36xx_sr2_slaves[] = { + &omap36xx_l4_core__sr2, +}; + static struct omap_hwmod omap36xx_sr2_hwmod = { - .name = "sr2_hwmod", + .name = "sr2", .class = &omap36xx_smartreflex_hwmod_class, .main_clk = "sr2_fck", - .vdd_name = "core", .prcm = { .omap2 = { .prcm_reg_id = 1, @@ -2667,8 +2737,10 @@ static struct omap_hwmod omap36xx_sr2_hwmod = { .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, }, }, - .slaves = omap3_sr2_slaves, - .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves), + .slaves = omap36xx_sr2_slaves, + .slaves_cnt = ARRAY_SIZE(omap36xx_sr2_slaves), + .dev_attr = &sr2_dev_attr, + .mpu_irqs = omap3_smartreflex_core_irqs, }; /* @@ -2946,6 +3018,44 @@ static struct omap_hwmod omap34xx_mcspi4 = { .dev_attr = &omap_mcspi4_dev_attr, }; +/* temp. sensor */ +struct omap_hwmod_class omap34xx_bandgap_ts_class = { + .name = "bandgap_ts", +}; + +static struct omap_hwmod_addr_space omap3xxx_bandgap_ts_addrs[] = { + { + .name = "mpu", + .pa_start = 0x48002524, + .pa_end = 0x48002524 + 4, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod omap34xx_bandgap_ts; + +/* l4_core -> bandgap */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__bandgap_ts = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap34xx_bandgap_ts, + .addr = omap3xxx_bandgap_ts_addrs, + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_bandgap_ts_slaves[] = { + &omap3xxx_l4_core__bandgap_ts, +}; + +static struct omap_hwmod omap34xx_bandgap_ts = { + .name = "bandgap_ts", + .main_clk = "ts_fck", + .slaves = omap3xxx_bandgap_ts_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_bandgap_ts_slaves), + .class = &omap34xx_bandgap_ts_class, + .flags = HWMOD_NO_IDLEST, +}; + /* * usbhsotg */ @@ -2997,9 +3107,14 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { * Erratum ID: i479 idle_req / idle_ack mechanism potentially * broken when autoidle is enabled * workaround is to disable the autoidle bit at module level. + * + * Enabling the device in any other MIDLEMODE setting but force-idle + * causes core_pwrdm not enter idle states at least on OMAP3630. + * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY + * signal when MIDLEMODE is set to force-idle. */ .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE - | HWMOD_SWSUP_MSTANDBY, + | HWMOD_FORCE_MSTANDBY, }; /* usb_otg_hs */ @@ -3072,7 +3187,35 @@ static struct omap_mmc_dev_attr mmc1_dev_attr = { .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, }; -static struct omap_hwmod omap3xxx_mmc1_hwmod = { +/* See 35xx errata 2.1.1.128 in SPRZ278F */ +static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = { + .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT | + OMAP_HSMMC_BROKEN_MULTIBLOCK_READ), +}; + +static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = { + .name = "mmc1", + .mpu_irqs = omap34xx_mmc1_mpu_irqs, + .sdma_reqs = omap34xx_mmc1_sdma_reqs, + .opt_clks = omap34xx_mmc1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), + .main_clk = "mmchs1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MMC1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, + }, + }, + .dev_attr = &mmc1_pre_es3_dev_attr, + .slaves = omap3xxx_mmc1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves), + .class = &omap34xx_mmc_class, +}; + +static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { .name = "mmc1", .mpu_irqs = omap34xx_mmc1_mpu_irqs, .sdma_reqs = omap34xx_mmc1_sdma_reqs, @@ -3115,7 +3258,34 @@ static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = { &omap3xxx_l4_core__mmc2, }; -static struct omap_hwmod omap3xxx_mmc2_hwmod = { +/* See 35xx errata 2.1.1.128 in SPRZ278F */ +static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = { + .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, +}; + +static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = { + .name = "mmc2", + .mpu_irqs = omap34xx_mmc2_mpu_irqs, + .sdma_reqs = omap34xx_mmc2_sdma_reqs, + .opt_clks = omap34xx_mmc2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), + .main_clk = "mmchs2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_MMC2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, + }, + }, + .dev_attr = &mmc2_pre_es3_dev_attr, + .slaves = omap3xxx_mmc2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves), + .class = &omap34xx_mmc_class, +}; + +static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { .name = "mmc2", .mpu_irqs = omap34xx_mmc2_mpu_irqs, .sdma_reqs = omap34xx_mmc2_sdma_reqs, @@ -3182,8 +3352,6 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_l4_core_hwmod, &omap3xxx_l4_per_hwmod, &omap3xxx_l4_wkup_hwmod, - &omap3xxx_mmc1_hwmod, - &omap3xxx_mmc2_hwmod, &omap3xxx_mmc3_hwmod, &omap3xxx_mpu_hwmod, @@ -3198,17 +3366,11 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_timer9_hwmod, &omap3xxx_timer10_hwmod, &omap3xxx_timer11_hwmod, - &omap3xxx_timer12_hwmod, &omap3xxx_wd_timer2_hwmod, &omap3xxx_uart1_hwmod, &omap3xxx_uart2_hwmod, &omap3xxx_uart3_hwmod, - /* dss class */ - &omap3xxx_dss_dispc_hwmod, - &omap3xxx_dss_dsi1_hwmod, - &omap3xxx_dss_rfbi_hwmod, - &omap3xxx_dss_venc_hwmod, /* i2c class */ &omap3xxx_i2c1_hwmod, @@ -3242,23 +3404,41 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap34xx_mcspi3, &omap34xx_mcspi4, + &omap34xx_bandgap_ts, + NULL, }; +/* GP-only hwmods */ +static __initdata struct omap_hwmod *omap3xxx_gp_hwmods[] = { + &omap3xxx_timer12_hwmod, + NULL +}; + /* 3430ES1-only hwmods */ static __initdata struct omap_hwmod *omap3430es1_hwmods[] = { - &omap3xxx_iva_hwmod, &omap3430es1_dss_core_hwmod, - &omap3xxx_mailbox_hwmod, NULL }; /* 3430ES2+-only hwmods */ static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = { - &omap3xxx_iva_hwmod, &omap3xxx_dss_core_hwmod, &omap3xxx_usbhsotg_hwmod, - &omap3xxx_mailbox_hwmod, + NULL +}; + +/* <= 3430ES3-only hwmods */ +static struct omap_hwmod *omap3430_pre_es3_hwmods[] __initdata = { + &omap3xxx_pre_es3_mmc1_hwmod, + &omap3xxx_pre_es3_mmc2_hwmod, + NULL +}; + +/* 3430ES3+-only hwmods */ +static struct omap_hwmod *omap3430_es3plus_hwmods[] __initdata = { + &omap3xxx_es3plus_mmc1_hwmod, + &omap3xxx_es3plus_mmc2_hwmod, NULL }; @@ -3274,18 +3454,31 @@ static __initdata struct omap_hwmod *omap34xx_hwmods[] = { /* 36xx-only hwmods (all ES revisions) */ static __initdata struct omap_hwmod *omap36xx_hwmods[] = { &omap3xxx_iva_hwmod, - &omap3xxx_uart4_hwmod, + &omap36xx_uart4_hwmod, &omap3xxx_dss_core_hwmod, &omap36xx_sr1_hwmod, &omap36xx_sr2_hwmod, &omap3xxx_usbhsotg_hwmod, &omap3xxx_mailbox_hwmod, + &omap3xxx_es3plus_mmc1_hwmod, + &omap3xxx_es3plus_mmc2_hwmod, NULL }; static __initdata struct omap_hwmod *am35xx_hwmods[] = { &omap3xxx_dss_core_hwmod, /* XXX ??? */ &am35xx_usbhsotg_hwmod, + &omap3xxx_es3plus_mmc1_hwmod, + &omap3xxx_es3plus_mmc2_hwmod, + NULL +}; + +static __initdata struct omap_hwmod *omap3xxx_dss_hwmods[] = { + /* dss class */ + &omap3xxx_dss_dispc_hwmod, + &omap3xxx_dss_dsi1_hwmod, + &omap3xxx_dss_rfbi_hwmod, + &omap3xxx_dss_venc_hwmod, NULL }; @@ -3300,6 +3493,13 @@ int __init omap3xxx_hwmod_init(void) if (r < 0) return r; + /* Register GP-only hwmods. */ + if (omap_type() == OMAP2_DEVICE_TYPE_GP) { + r = omap_hwmod_register(omap3xxx_gp_hwmods); + if (r < 0) + return r; + } + rev = omap_rev(); /* @@ -3338,8 +3538,36 @@ int __init omap3xxx_hwmod_init(void) h = omap3430es2plus_hwmods; }; + if (h) { + r = omap_hwmod_register(h); + if (r < 0) + return r; + } + + h = NULL; + if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || + rev == OMAP3430_REV_ES2_1) { + h = omap3430_pre_es3_hwmods; + } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || + rev == OMAP3430_REV_ES3_1_2) { + h = omap3430_es3plus_hwmods; + }; + if (h) r = omap_hwmod_register(h); + if (r < 0) + return r; + + /* + * DSS code presumes that dss_core hwmod is handled first, + * _before_ any other DSS related hwmods so register common + * DSS hwmods last to ensure that dss_core is already registered. + * Otherwise some change things may happen, for ex. if dispc + * is handled before dss_core and DSS is enabled in bootloader + * DIPSC will be reset with outputs enabled which sometimes leads + * to unrecoverable L3 error. + */ + r = omap_hwmod_register(omap3xxx_dss_hwmods); return r; }