X-Git-Url: https://git.openpandora.org/cgi-bin/gitweb.cgi?p=pandora-kernel.git;a=blobdiff_plain;f=arch%2Farm%2Fmach-omap1%2Fclock.c;h=f1958e882e8694e3bd480dd46b62af3f351c6d28;hp=4277eee44ed5cc392a94c390011027f1f379f0b8;hb=e82ca04387dd6c98722f5f48235089839fd04268;hpb=5643f000c1e10ab991182478b76550e1364c3570 diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index 4277eee44ed5..f1958e882e86 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -1,3 +1,4 @@ +//kernel/linux-omap-fsample/arch/arm/mach-omap1/clock.c#2 - edit change 3808 (text) /* * linux/arch/arm/mach-omap1/clock.c * @@ -16,10 +17,11 @@ #include #include #include +#include #include -#include +#include #include #include #include @@ -50,10 +52,10 @@ static int omap1_clk_enable_dsp_domain(struct clk *clk) { int retval; - retval = omap1_clk_use(&api_ck.clk); + retval = omap1_clk_enable(&api_ck.clk); if (!retval) { - retval = omap1_clk_enable(clk); - omap1_clk_unuse(&api_ck.clk); + retval = omap1_clk_enable_generic(clk); + omap1_clk_disable(&api_ck.clk); } return retval; @@ -61,9 +63,9 @@ static int omap1_clk_enable_dsp_domain(struct clk *clk) static void omap1_clk_disable_dsp_domain(struct clk *clk) { - if (omap1_clk_use(&api_ck.clk) == 0) { - omap1_clk_disable(clk); - omap1_clk_unuse(&api_ck.clk); + if (omap1_clk_enable(&api_ck.clk) == 0) { + omap1_clk_disable_generic(clk); + omap1_clk_disable(&api_ck.clk); } } @@ -72,7 +74,7 @@ static int omap1_clk_enable_uart_functional(struct clk *clk) int ret; struct uart_clk *uclk; - ret = omap1_clk_enable(clk); + ret = omap1_clk_enable_generic(clk); if (ret == 0) { /* Set smart idle acknowledgement mode */ uclk = (struct uart_clk *)clk; @@ -91,7 +93,7 @@ static void omap1_clk_disable_uart_functional(struct clk *clk) uclk = (struct uart_clk *)clk; omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr); - omap1_clk_disable(clk); + omap1_clk_disable_generic(clk); } static void omap1_clk_allow_idle(struct clk *clk) @@ -230,9 +232,9 @@ static void omap1_ckctl_recalc_dsp_domain(struct clk * clk) * Note that DSP_CKCTL virt addr = phys addr, so * we must use __raw_readw() instead of omap_readw(). */ - omap1_clk_use(&api_ck.clk); + omap1_clk_enable(&api_ck.clk); dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset)); - omap1_clk_unuse(&api_ck.clk); + omap1_clk_disable(&api_ck.clk); if (unlikely(clk->rate == clk->parent->rate / dsor)) return; /* No change, quick exit */ @@ -270,8 +272,12 @@ static int omap1_select_table_rate(struct clk * clk, unsigned long rate) /* * In most cases we should not need to reprogram DPLL. * Reprogramming the DPLL is tricky, it must be done from SRAM. + * (on 730, bit 13 must always be 1) */ - omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); + if (cpu_is_omap730()) + omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000); + else + omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); ck_dpll1.rate = ptr->pll_rate; propagate_rate(&ck_dpll1); @@ -345,7 +351,7 @@ static unsigned calc_ext_dsor(unsigned long rate) */ for (dsor = 2; dsor < 96; ++dsor) { if ((dsor & 1) && dsor > 8) - continue; + continue; if (rate >= 96000000 / dsor) break; } @@ -412,12 +418,12 @@ static void omap1_init_ext_clk(struct clk * clk) clk-> rate = 96000000 / dsor; } -static int omap1_clk_use(struct clk *clk) +static int omap1_clk_enable(struct clk *clk) { int ret = 0; if (clk->usecount++ == 0) { if (likely(clk->parent)) { - ret = omap1_clk_use(clk->parent); + ret = omap1_clk_enable(clk->parent); if (unlikely(ret != 0)) { clk->usecount--; @@ -432,7 +438,7 @@ static int omap1_clk_use(struct clk *clk) ret = clk->enable(clk); if (unlikely(ret != 0) && clk->parent) { - omap1_clk_unuse(clk->parent); + omap1_clk_disable(clk->parent); clk->usecount--; } } @@ -440,12 +446,12 @@ static int omap1_clk_use(struct clk *clk) return ret; } -static void omap1_clk_unuse(struct clk *clk) +static void omap1_clk_disable(struct clk *clk) { if (clk->usecount > 0 && !(--clk->usecount)) { clk->disable(clk); if (likely(clk->parent)) { - omap1_clk_unuse(clk->parent); + omap1_clk_disable(clk->parent); if (clk->flags & CLOCK_NO_IDLE_PARENT) if (!cpu_is_omap24xx()) omap1_clk_allow_idle(clk->parent); @@ -453,7 +459,7 @@ static void omap1_clk_unuse(struct clk *clk) } } -static int omap1_clk_enable(struct clk *clk) +static int omap1_clk_enable_generic(struct clk *clk) { __u16 regval16; __u32 regval32; @@ -492,7 +498,7 @@ static int omap1_clk_enable(struct clk *clk) return 0; } -static void omap1_clk_disable(struct clk *clk) +static void omap1_clk_disable_generic(struct clk *clk) { __u16 regval16; __u32 regval32; @@ -654,8 +660,8 @@ late_initcall(omap1_late_clk_reset); #endif static struct clk_functions omap1_clk_functions = { - .clk_use = omap1_clk_use, - .clk_unuse = omap1_clk_unuse, + .clk_enable = omap1_clk_enable, + .clk_disable = omap1_clk_disable, .clk_round_rate = omap1_clk_round_rate, .clk_set_rate = omap1_clk_set_rate, }; @@ -687,6 +693,11 @@ int __init omap1_clk_init(void) clk_register(*clkp); continue; } + + if (((*clkp)->flags &CLOCK_IN_OMAP310) && cpu_is_omap310()) { + clk_register(*clkp); + continue; + } } info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config); @@ -743,7 +754,7 @@ int __init omap1_clk_init(void) printk(KERN_ERR "System frequencies not set. Check your config.\n"); /* Guess sane values (60MHz) */ omap_writew(0x2290, DPLL_CTL); - omap_writew(0x1005, ARM_CKCTL); + omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL); ck_dpll1.rate = 60000000; propagate_rate(&ck_dpll1); } @@ -756,13 +767,17 @@ int __init omap1_clk_init(void) ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); -#ifdef CONFIG_MACH_OMAP_PERSEUS2 +#if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE) /* Select slicer output as OMAP input clock */ omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL); #endif /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ - omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); + /* (on 730, bit 13 must not be cleared) */ + if (cpu_is_omap730()) + omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); + else + omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); /* Put DSP/MPUI into reset until needed */ omap_writew(0, ARM_RSTCT1); @@ -780,11 +795,11 @@ int __init omap1_clk_init(void) * Only enable those clocks we will need, let the drivers * enable other clocks as necessary */ - clk_use(&armper_ck.clk); - clk_use(&armxor_ck.clk); - clk_use(&armtim_ck.clk); /* This should be done by timer code */ + clk_enable(&armper_ck.clk); + clk_enable(&armxor_ck.clk); + clk_enable(&armtim_ck.clk); /* This should be done by timer code */ - if (cpu_is_omap1510()) + if (cpu_is_omap15xx()) clk_enable(&arm_gpio_ck); return 0;