X-Git-Url: https://git.openpandora.org/cgi-bin/gitweb.cgi?p=pandora-kernel.git;a=blobdiff_plain;f=arch%2Farm%2Fmach-at91%2Fat91sam9260.c;h=cb397be14448eaa767ddbfd94bdf4fbdf8c25254;hp=57974b19d7a76bdf445e3d17c8482ff4fe325d74;hb=f33c596a2f921696391801b637ed50d514634079;hpb=1ff5b1b411bf8a8157ae949a1b3ed8666d96c1db diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c index 57974b19d7a7..cb397be14448 100644 --- a/arch/arm/mach-at91/at91sam9260.c +++ b/arch/arm/mach-at91/at91sam9260.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -26,41 +27,6 @@ #include "generic.h" #include "clock.h" -static struct map_desc at91sam9260_sram_desc[] __initdata = { - { - .virtual = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE, - .pfn = __phys_to_pfn(AT91SAM9260_SRAM0_BASE), - .length = AT91SAM9260_SRAM0_SIZE, - .type = MT_DEVICE, - }, { - .virtual = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE - AT91SAM9260_SRAM1_SIZE, - .pfn = __phys_to_pfn(AT91SAM9260_SRAM1_BASE), - .length = AT91SAM9260_SRAM1_SIZE, - .type = MT_DEVICE, - } -}; - -static struct map_desc at91sam9g20_sram_desc[] __initdata = { - { - .virtual = AT91_IO_VIRT_BASE - AT91SAM9G20_SRAM0_SIZE, - .pfn = __phys_to_pfn(AT91SAM9G20_SRAM0_BASE), - .length = AT91SAM9G20_SRAM0_SIZE, - .type = MT_DEVICE, - }, { - .virtual = AT91_IO_VIRT_BASE - AT91SAM9G20_SRAM0_SIZE - AT91SAM9G20_SRAM1_SIZE, - .pfn = __phys_to_pfn(AT91SAM9G20_SRAM1_BASE), - .length = AT91SAM9G20_SRAM1_SIZE, - .type = MT_DEVICE, - } -}; - -static struct map_desc at91sam9xe_sram_desc[] __initdata = { - { - .pfn = __phys_to_pfn(AT91SAM9XE_SRAM_BASE), - .type = MT_DEVICE, - } -}; - /* -------------------------------------------------------------------- * Clocks * -------------------------------------------------------------------- */ @@ -322,11 +288,9 @@ static void at91sam9260_poweroff(void) static void __init at91sam9xe_map_io(void) { - unsigned long cidr, sram_size; - - cidr = dbgu_readl(AT91_DBGU, CIDR); + unsigned long sram_size; - switch (cidr & AT91_CIDR_SRAMSIZ) { + switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) { case AT91_CIDR_SRAMSIZ_32K: sram_size = 2 * SZ_16K; break; @@ -335,35 +299,29 @@ static void __init at91sam9xe_map_io(void) sram_size = SZ_16K; } - at91sam9xe_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size; - at91sam9xe_sram_desc->length = sram_size; - - iotable_init(at91sam9xe_sram_desc, ARRAY_SIZE(at91sam9xe_sram_desc)); + at91_init_sram(0, AT91SAM9XE_SRAM_BASE, sram_size); } static void __init at91sam9260_map_io(void) { - if (cpu_is_at91sam9xe()) + if (cpu_is_at91sam9xe()) { at91sam9xe_map_io(); - else if (cpu_is_at91sam9g20()) - iotable_init(at91sam9g20_sram_desc, ARRAY_SIZE(at91sam9g20_sram_desc)); - else - iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc)); + } else if (cpu_is_at91sam9g20()) { + at91_init_sram(0, AT91SAM9G20_SRAM0_BASE, AT91SAM9G20_SRAM0_SIZE); + at91_init_sram(1, AT91SAM9G20_SRAM1_BASE, AT91SAM9G20_SRAM1_SIZE); + } else { + at91_init_sram(0, AT91SAM9260_SRAM0_BASE, AT91SAM9260_SRAM0_SIZE); + at91_init_sram(1, AT91SAM9260_SRAM1_BASE, AT91SAM9260_SRAM1_SIZE); + } } -static void __init at91sam9260_initialize(unsigned long main_clock) +static void __init at91sam9260_initialize(void) { at91_arch_reset = at91sam9_alt_reset; pm_power_off = at91sam9260_poweroff; at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1) | (1 << AT91SAM9260_ID_IRQ2); - /* Init clock subsystem */ - at91_clock_init(main_clock); - - /* Register the processor-specific clocks */ - at91sam9260_register_clocks(); - /* Register GPIO subsystem */ at91_gpio_init(at91sam9260_gpio, 3); } @@ -410,8 +368,9 @@ static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller */ }; -struct at91_soc __initdata at91sam9260_soc = { +struct at91_init_soc __initdata at91sam9260_soc = { .map_io = at91sam9260_map_io, .default_irq_priority = at91sam9260_default_irq_priority, + .register_clocks = at91sam9260_register_clocks, .init = at91sam9260_initialize, };