break;
case SND_SOC_DAIFMT_DSP_A:
regs->srgr2 |= FPER(wlen * 2 - 1);
- regs->srgr1 |= FWID(0);
+ regs->srgr1 |= FWID(wlen * 2 - 2);
break;
}
{
struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
- unsigned int temp_fmt = fmt;
if (mcbsp_data->configured)
return 0;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
- /* 0-bit data delay */
- regs->rcr2 |= RDATDLY(0);
- regs->xcr2 |= XDATDLY(0);
- /* Invert bit clock and FS polarity configuration for DSP_A */
- temp_fmt ^= SND_SOC_DAIFMT_IB_IF;
- break;
- default:
- /* Unsupported data format */
+ /* 0-bit data delay */
+ regs->rcr2 |= RDATDLY(0);
+ regs->xcr2 |= XDATDLY(0);
+ break;
+ default:
+ /* Unsupported data format */
return -EINVAL;
}
}
/* Set bit clock (CLKX/CLKR) and FS polarities */
- switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {
+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
/*
* Normal BCLK + FS.