ATH9K_HW_CAP_AUTOSLEEP = BIT(19),
ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(20),
ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT = BIT(21),
+ ATH9K_HW_CAP_BT_COEX = BIT(22)
};
enum ath9k_capability_type {
CHANNEL_HT40MINUS)
struct ath9k_channel {
+ struct ieee80211_channel *chan;
u16 channel;
u32 channelFlags;
u8 privFlags;
#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
+#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
u16 ah_currentRD5G;
u16 ah_currentRD2G;
char ah_iso[4];
+ enum ath9k_power_mode ah_power_mode;
+ enum ath9k_power_mode ah_restore_mode;
struct ath9k_channel ah_channels[150];
struct ath9k_channel *ah_curchan;
u16 ah_rfsilent;
u32 ah_rfkill_gpio;
u32 ah_rfkill_polarity;
+ u32 ah_btactive_gpio;
+ u32 ah_wlanactive_gpio;
#ifndef ATH_NF_PER_CHAN
struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
#endif
+
+ bool sw_mgmt_crypto;
};
struct chan_centers {
/* HW Reset */
-bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
- enum ath9k_ht_macmode macmode,
- u8 txchainmask, u8 rxchainmask,
- enum ath9k_ht_extprotspacing extprotspacing,
- bool bChannelChange, int *status);
+int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
+ bool bChannelChange);
/* Key Cache Management */
/* Calibration */
-void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan,
- bool *isCalDone);
+bool ath9k_hw_reset_calvalid(struct ath_hal *ah);
void ath9k_hw_start_nfcal(struct ath_hal *ah);
void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan);
int16_t ath9k_hw_getnf(struct ath_hal *ah,
void ath9k_hw_startpcureceive(struct ath_hal *ah);
void ath9k_hw_stoppcurecv(struct ath_hal *ah);
bool ath9k_hw_stopdmarecv(struct ath_hal *ah);
+void ath9k_hw_btcoex_enable(struct ath_hal *ah);
#endif