ath9k: Enable dynamic power save in ath9k.

[pandora-kernel.git] / drivers / net / wireless / ath9k / ath9k.h

diff --git a/drivers/net/wireless/ath9k/ath9k.h b/drivers/net/wireless/ath9k/ath9k.h
index 3a180ce..0b305b8 100644 (file)
--- a/drivers/net/wireless/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath9k/ath9k.h
@@ -26,6 +26,7 @@
 #define AR9160_DEVID_PCI       0x0027
 #define AR9280_DEVID_PCI       0x0029
 #define AR9280_DEVID_PCIE      0x002a
+#define AR9285_DEVID_PCIE      0x002b
 
 #define AR5416_AR9100_DEVID    0x000b
 
@@ -197,6 +198,7 @@ enum ath9k_hw_caps {
        ATH9K_HW_CAP_AUTOSLEEP                  = BIT(19),
        ATH9K_HW_CAP_4KB_SPLITTRANS             = BIT(20),
        ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT     = BIT(21),
+       ATH9K_HW_CAP_BT_COEX                    = BIT(22)
 };
 
 enum ath9k_capability_type {
@@ -401,22 +403,6 @@ enum ath9k_int {
        ATH9K_INT_NOCARD = 0xffffffff
 };
 
-struct ath9k_rate_table {
-       int rateCount;
-       u8 rateCodeToIndex[256];
-       struct {
-               u8 valid;
-               u8 phy;
-               u32 rateKbps;
-               u8 rateCode;
-               u8 shortPreamble;
-               u8 dot11Rate;
-               u8 controlRate;
-               u16 lpAckDuration;
-               u16 spAckDuration;
-       } info[32];
-};
-
 #define ATH9K_RATESERIES_RTS_CTS  0x0001
 #define ATH9K_RATESERIES_2040     0x0002
 #define ATH9K_RATESERIES_HALFGI   0x0004
@@ -468,6 +454,7 @@ struct ath9k_11n_rate_series {
         CHANNEL_HT40MINUS)
 
 struct ath9k_channel {
+       struct ieee80211_channel *chan;
        u16 channel;
        u32 channelFlags;
        u8 privFlags;
@@ -492,12 +479,10 @@ struct ath9k_channel {
        (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20) || \
        (((_c)->channelFlags & CHANNEL_A_HT40PLUS) == CHANNEL_A_HT40PLUS) || \
        (((_c)->channelFlags & CHANNEL_A_HT40MINUS) == CHANNEL_A_HT40MINUS))
-#define IS_CHAN_B(_c) (((_c)->channelFlags & CHANNEL_B) == CHANNEL_B)
 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
        (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
        (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
        (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
-#define IS_CHAN_CCK(_c) (((_c)->channelFlags & CHANNEL_CCK) != 0)
 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
@@ -506,6 +491,7 @@ struct ath9k_channel {
 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
 
 /* These macros check chanmode and not channelFlags */
+#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) ||        \
                          ((_c)->chanmode == CHANNEL_G_HT20))
 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) ||    \
@@ -664,13 +650,6 @@ enum ath9k_ant_setting {
        ATH9K_ANT_FIXED_B
 };
 
-enum ath9k_opmode {
-       ATH9K_M_STA = 1,
-       ATH9K_M_IBSS = 0,
-       ATH9K_M_HOSTAP = 6,
-       ATH9K_M_MONITOR = 8
-};
-
 #define ATH9K_SLOT_TIME_6 6
 #define ATH9K_SLOT_TIME_9 9
 #define ATH9K_SLOT_TIME_20 20
@@ -702,13 +681,19 @@ enum ath9k_ani_cmd {
        ATH9K_ANI_ALL = 0xff
 };
 
-enum phytype {
-       PHY_DS,
-       PHY_FH,
-       PHY_OFDM,
-       PHY_HT,
+enum {
+       WLAN_RC_PHY_OFDM,
+       WLAN_RC_PHY_CCK,
+       WLAN_RC_PHY_HT_20_SS,
+       WLAN_RC_PHY_HT_20_DS,
+       WLAN_RC_PHY_HT_40_SS,
+       WLAN_RC_PHY_HT_40_DS,
+       WLAN_RC_PHY_HT_20_SS_HGI,
+       WLAN_RC_PHY_HT_20_DS_HGI,
+       WLAN_RC_PHY_HT_40_SS_HGI,
+       WLAN_RC_PHY_HT_40_DS_HGI,
+       WLAN_RC_PHY_MAX
 };
-#define PHY_CCK PHY_DS
 
 enum ath9k_tp_scale {
        ATH9K_TP_SCALE_MAX = 0,
@@ -768,6 +753,7 @@ struct ath9k_node_stats {
 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT             0
 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED     2
+#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME           3
 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED    5
 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED      6
 
@@ -791,7 +777,8 @@ struct ath_hal {
 
        void __iomem *ah_sh;
        struct ath_softc *ah_sc;
-       enum ath9k_opmode ah_opmode;
+
+       enum nl80211_iftype ah_opmode;
        struct ath9k_ops_config ah_config;
        struct ath9k_hw_capabilities ah_caps;
 
@@ -806,6 +793,8 @@ struct ath_hal {
        u16 ah_currentRD5G;
        u16 ah_currentRD2G;
        char ah_iso[4];
+       enum ath9k_power_mode ah_power_mode;
+       enum ath9k_power_mode ah_restore_mode;
 
        struct ath9k_channel ah_channels[150];
        struct ath9k_channel *ah_curchan;
@@ -816,10 +805,14 @@ struct ath_hal {
        u16 ah_rfsilent;
        u32 ah_rfkill_gpio;
        u32 ah_rfkill_polarity;
+       u32 ah_btactive_gpio;
+       u32 ah_wlanactive_gpio;
 
 #ifndef ATH_NF_PER_CHAN
        struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
 #endif
+
+       bool sw_mgmt_crypto;
 };
 
 struct chan_centers {
@@ -828,6 +821,8 @@ struct chan_centers {
        u16 ext_center;
 };
 
+struct ath_rate_table;
+
 /* Helpers */
 
 enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
@@ -838,7 +833,7 @@ bool ath9k_get_channel_edges(struct ath_hal *ah,
                             u16 flags, u16 *low,
                             u16 *high);
 u16 ath9k_hw_computetxtime(struct ath_hal *ah,
-                          const struct ath9k_rate_table *rates,
+                          struct ath_rate_table *rates,
                           u32 frameLen, u16 rateix,
                           bool shortPreamble);
 u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags);
@@ -857,11 +852,8 @@ void ath9k_hw_rfdetach(struct ath_hal *ah);
 
 /* HW Reset */
 
-bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
-                   enum ath9k_ht_macmode macmode,
-                   u8 txchainmask, u8 rxchainmask,
-                   enum ath9k_ht_extprotspacing extprotspacing,
-                   bool bChannelChange, int *status);
+int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
+                   bool bChannelChange);
 
 /* Key Cache Management */
 
@@ -883,12 +875,6 @@ void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore);
 void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period);
 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
                                    const struct ath9k_beacon_state *bs);
-
-/* Rate table */
-
-const struct ath9k_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
-                                                    u32 mode);
-
 /* HW Capabilities */
 
 bool ath9k_hw_fill_cap_info(struct ath_hal *ah);
@@ -904,7 +890,7 @@ u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio);
 void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
                         u32 ah_signal_type);
 void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val);
-#ifdef CONFIG_RFKILL
+#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
 void ath9k_enable_rfkill(struct ath_hal *ah);
 #endif
 int ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg);
@@ -971,8 +957,7 @@ void ath9k_hw_ani_detach(struct ath_hal *ah);
 
 /* Calibration */
 
-void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan,
-                            bool *isCalDone);
+bool ath9k_hw_reset_calvalid(struct ath_hal *ah);
 void ath9k_hw_start_nfcal(struct ath_hal *ah);
 void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan);
 int16_t ath9k_hw_getnf(struct ath_hal *ah,
@@ -1024,7 +1009,6 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints);
 
 /* MAC (PCU/QCU) */
 
-void ath9k_hw_dmaRegDump(struct ath_hal *ah);
 u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q);
 bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q, u32 txdp);
 bool ath9k_hw_txstart(struct ath_hal *ah, u32 q);
@@ -1074,5 +1058,6 @@ void ath9k_hw_rxena(struct ath_hal *ah);
 void ath9k_hw_startpcureceive(struct ath_hal *ah);
 void ath9k_hw_stoppcurecv(struct ath_hal *ah);
 bool ath9k_hw_stopdmarecv(struct ath_hal *ah);
+void ath9k_hw_btcoex_enable(struct ath_hal *ah);
 
 #endif