mmc: sdhci: add eMMC hardware reset support

[pandora-kernel.git] / drivers / mmc / host / sdhci.h

diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 25e8bde..7bd919c 100644 (file)
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -25,6 +25,7 @@
  */
 
 #define SDHCI_DMA_ADDRESS      0x00
+#define SDHCI_ARGUMENT2                SDHCI_DMA_ADDRESS
 
 #define SDHCI_BLOCK_SIZE       0x04
 #define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
@@ -36,7 +37,8 @@
 #define SDHCI_TRANSFER_MODE    0x0C
 #define  SDHCI_TRNS_DMA                0x01
 #define  SDHCI_TRNS_BLK_CNT_EN 0x02
-#define  SDHCI_TRNS_ACMD12     0x04
+#define  SDHCI_TRNS_AUTO_CMD12 0x04
+#define  SDHCI_TRNS_AUTO_CMD23 0x08
 #define  SDHCI_TRNS_READ       0x10
 #define  SDHCI_TRNS_MULTI      0x20
 
@@ -68,8 +70,10 @@
 #define  SDHCI_DATA_AVAILABLE  0x00000800
 #define  SDHCI_CARD_PRESENT    0x00010000
 #define  SDHCI_WRITE_PROTECT   0x00080000
+#define  SDHCI_DATA_LVL_MASK   0x00F00000
+#define   SDHCI_DATA_LVL_SHIFT 20
 
-#define SDHCI_HOST_CONTROL     0x28
+#define SDHCI_HOST_CONTROL     0x28
 #define  SDHCI_CTRL_LED                0x01
 #define  SDHCI_CTRL_4BITBUS    0x02
 #define  SDHCI_CTRL_HISPD      0x04
@@ -99,6 +103,7 @@
 #define  SDHCI_DIV_MASK        0xFF
 #define  SDHCI_DIV_MASK_LEN    8
 #define  SDHCI_DIV_HI_MASK     0x300
+#define  SDHCI_PROG_CLOCK_MODE 0x0020
 #define  SDHCI_CLOCK_CARD_EN   0x0004
 #define  SDHCI_CLOCK_INT_STABLE        0x0002
 #define  SDHCI_CLOCK_INT_EN    0x0001
@@ -146,7 +151,22 @@
 
 #define SDHCI_ACMD12_ERR       0x3C
 
-/* 3E-3F reserved */
+#define SDHCI_HOST_CONTROL2            0x3E
+#define  SDHCI_CTRL_UHS_MASK           0x0007
+#define   SDHCI_CTRL_UHS_SDR12         0x0000
+#define   SDHCI_CTRL_UHS_SDR25         0x0001
+#define   SDHCI_CTRL_UHS_SDR50         0x0002
+#define   SDHCI_CTRL_UHS_SDR104                0x0003
+#define   SDHCI_CTRL_UHS_DDR50         0x0004
+#define  SDHCI_CTRL_VDD_180            0x0008
+#define  SDHCI_CTRL_DRV_TYPE_MASK      0x0030
+#define   SDHCI_CTRL_DRV_TYPE_B                0x0000
+#define   SDHCI_CTRL_DRV_TYPE_A                0x0010
+#define   SDHCI_CTRL_DRV_TYPE_C                0x0020
+#define   SDHCI_CTRL_DRV_TYPE_D                0x0030
+#define  SDHCI_CTRL_EXEC_TUNING                0x0040
+#define  SDHCI_CTRL_TUNED_CLK          0x0080
+#define  SDHCI_CTRL_PRESET_VAL_ENABLE  0x8000
 
 #define SDHCI_CAPABILITIES     0x40
 #define  SDHCI_TIMEOUT_CLK_MASK        0x0000003F
@@ -167,9 +187,30 @@
 #define  SDHCI_CAN_VDD_180     0x04000000
 #define  SDHCI_CAN_64BIT       0x10000000
 
+#define  SDHCI_SUPPORT_SDR50   0x00000001
+#define  SDHCI_SUPPORT_SDR104  0x00000002
+#define  SDHCI_SUPPORT_DDR50   0x00000004
+#define  SDHCI_DRIVER_TYPE_A   0x00000010
+#define  SDHCI_DRIVER_TYPE_C   0x00000020
+#define  SDHCI_DRIVER_TYPE_D   0x00000040
+#define  SDHCI_RETUNING_TIMER_COUNT_MASK       0x00000F00
+#define  SDHCI_RETUNING_TIMER_COUNT_SHIFT      8
+#define  SDHCI_USE_SDR50_TUNING                        0x00002000
+#define  SDHCI_RETUNING_MODE_MASK              0x0000C000
+#define  SDHCI_RETUNING_MODE_SHIFT             14
+#define  SDHCI_CLOCK_MUL_MASK  0x00FF0000
+#define  SDHCI_CLOCK_MUL_SHIFT 16
+
 #define SDHCI_CAPABILITIES_1   0x44
 
-#define SDHCI_MAX_CURRENT      0x48
+#define SDHCI_MAX_CURRENT              0x48
+#define  SDHCI_MAX_CURRENT_330_MASK    0x0000FF
+#define  SDHCI_MAX_CURRENT_330_SHIFT   0
+#define  SDHCI_MAX_CURRENT_300_MASK    0x00FF00
+#define  SDHCI_MAX_CURRENT_300_SHIFT   8
+#define  SDHCI_MAX_CURRENT_180_MASK    0xFF0000
+#define  SDHCI_MAX_CURRENT_180_SHIFT   16
+#define   SDHCI_MAX_CURRENT_MULTIPLIER 4
 
 /* 4C-4F reserved for more max current */
 
@@ -202,6 +243,12 @@
 #define SDHCI_MAX_DIV_SPEC_200 256
 #define SDHCI_MAX_DIV_SPEC_300 2046
 
+/*
+ * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
+ */
+#define SDHCI_DEFAULT_BOUNDARY_SIZE  (512 * 1024)
+#define SDHCI_DEFAULT_BOUNDARY_ARG   (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
+
 struct sdhci_ops {
 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
        u32             (*read_l)(struct sdhci_host *host, int reg);
@@ -223,6 +270,10 @@ struct sdhci_ops {
        void (*platform_send_init_74_clocks)(struct sdhci_host *host,
                                             u8 power_mode);
        unsigned int    (*get_ro)(struct sdhci_host *host);
+       void    (*platform_reset_enter)(struct sdhci_host *host, u8 mask);
+       void    (*platform_reset_exit)(struct sdhci_host *host, u8 mask);
+       int     (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
+       void    (*hw_reset)(struct sdhci_host *host);
 };
 
 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS