drm/radeon: fix the r100/r200 ums block 0 page fix

[pandora-kernel.git] / drivers / gpu / drm / radeon / radeon_state.c

diff --git a/drivers/gpu/drm/radeon/radeon_state.c b/drivers/gpu/drm/radeon/radeon_state.c
index 3c32f84..11ce94c 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_state.c
+++ b/drivers/gpu/drm/radeon/radeon_state.c
@@ -900,9 +900,10 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
                        flags |= RADEON_FRONT;
        }
        if (flags & (RADEON_DEPTH|RADEON_STENCIL)) {
-               if (!dev_priv->have_z_offset)
+               if (!dev_priv->have_z_offset) {
                        printk_once(KERN_ERR "radeon: illegal depth clear request. Buggy mesa detected - please update.\n");
-               flags &= ~(RADEON_DEPTH | RADEON_STENCIL);
+                       flags &= ~(RADEON_DEPTH | RADEON_STENCIL);
+               }
        }
 
        if (flags & (RADEON_FRONT | RADEON_BACK)) {
@@ -1093,7 +1094,7 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
                                        /* judging by the first tile offset needed, could possibly
                                           directly address/clear 4x4 tiles instead of 8x2 * 4x4
                                           macro tiles, though would still need clear mask for
-                                          right/bottom if truely 4x4 granularity is desired ? */
+                                          right/bottom if truly 4x4 granularity is desired ? */
                                        OUT_RING(tileoffset * 16);
                                        /* the number of tiles to clear */
                                        OUT_RING(nrtilesx + 1);