Merge branch 'stable-3.2' into pandora-3.2

[pandora-kernel.git] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4a5e662..124dd87 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -27,6 +27,8 @@
 
 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
 
+#define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
+
 /*
  * The Bridge device's PCI config space has information about the
  * fb aperture size and the amount of pre-reserved memory.
@@ -389,6 +391,7 @@
  * the enables for writing to the corresponding low bit.
  */
 #define _3D_CHICKEN    0x02084
+#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB      (1 << 10)
 #define _3D_CHICKEN2   0x0208c
 /* Disables pipelining of read flushes past the SF-WIZ interface.
  * Required on all Ironlake steppings according to the B-Spec, but the
@@ -399,7 +402,11 @@
 
 #define MI_MODE                0x0209c
 # define VS_TIMER_DISPATCH                             (1 << 6)
-# define MI_FLUSH_ENABLE                               (1 << 11)
+# define MI_FLUSH_ENABLE                               (1 << 12)
+# define ASYNC_FLIP_PERF_DISABLE                       (1 << 14)
+
+#define GEN6_GT_MODE   0x20d0
+#define   GEN6_GT_MODE_HI      (1 << 9)
 
 #define GFX_MODE       0x02520
 #define GFX_MODE_GEN7  0x0229c
@@ -1557,6 +1564,10 @@
 
 /* Video Data Island Packet control */
 #define VIDEO_DIP_DATA         0x61178
+/* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC
+ * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
+ * of the infoframe structure specified by CEA-861. */
+#define   VIDEO_DIP_DATA_SIZE  32
 #define VIDEO_DIP_CTL          0x61170
 #define   VIDEO_DIP_ENABLE             (1 << 31)
 #define   VIDEO_DIP_PORT_B             (1 << 29)
@@ -2809,6 +2820,8 @@
 #define _PFA_CTL_1               0x68080
 #define _PFB_CTL_1               0x68880
 #define  PF_ENABLE              (1<<31)
+#define  PF_PIPE_SEL_MASK_IVB  (3<<29)
+#define  PF_PIPE_SEL_IVB(pipe) ((pipe)<<29)
 #define  PF_FILTER_MASK                (3<<23)
 #define  PF_FILTER_PROGRAMMED  (0<<23)
 #define  PF_FILTER_MED_3x3     (1<<23)