x86, apic: APIC code touches invalid MSR on P5 class machines

[pandora-kernel.git] / arch / x86 / kernel / apic / apic.c

diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index f98d84c..c4e3581 100644 (file)
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1577,9 +1577,11 @@ static int __init apic_verify(void)
        mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
 
        /* The BIOS may have set up the APIC at some other address */
-       rdmsr(MSR_IA32_APICBASE, l, h);
-       if (l & MSR_IA32_APICBASE_ENABLE)
-               mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
+       if (boot_cpu_data.x86 >= 6) {
+               rdmsr(MSR_IA32_APICBASE, l, h);
+               if (l & MSR_IA32_APICBASE_ENABLE)
+                       mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
+       }
 
        pr_info("Found and enabled local APIC!\n");
        return 0;
@@ -1597,13 +1599,15 @@ int __init apic_force_enable(unsigned long addr)
         * MSR. This can only be done in software for Intel P6 or later
         * and AMD K7 (Model > 1) or later.
         */
-       rdmsr(MSR_IA32_APICBASE, l, h);
-       if (!(l & MSR_IA32_APICBASE_ENABLE)) {
-               pr_info("Local APIC disabled by BIOS -- reenabling.\n");
-               l &= ~MSR_IA32_APICBASE_BASE;
-               l |= MSR_IA32_APICBASE_ENABLE | addr;
-               wrmsr(MSR_IA32_APICBASE, l, h);
-               enabled_via_apicbase = 1;
+       if (boot_cpu_data.x86 >= 6) {
+               rdmsr(MSR_IA32_APICBASE, l, h);
+               if (!(l & MSR_IA32_APICBASE_ENABLE)) {
+                       pr_info("Local APIC disabled by BIOS -- reenabling.\n");
+                       l &= ~MSR_IA32_APICBASE_BASE;
+                       l |= MSR_IA32_APICBASE_ENABLE | addr;
+                       wrmsr(MSR_IA32_APICBASE, l, h);
+                       enabled_via_apicbase = 1;
+               }
        }
        return apic_verify();
 }
@@ -2149,10 +2153,12 @@ static void lapic_resume(void)
                 * FIXME! This will be wrong if we ever support suspend on
                 * SMP! We'll need to do this as part of the CPU restore!
                 */
-               rdmsr(MSR_IA32_APICBASE, l, h);
-               l &= ~MSR_IA32_APICBASE_BASE;
-               l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
-               wrmsr(MSR_IA32_APICBASE, l, h);
+               if (boot_cpu_data.x86 >= 6) {
+                       rdmsr(MSR_IA32_APICBASE, l, h);
+                       l &= ~MSR_IA32_APICBASE_BASE;
+                       l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
+                       wrmsr(MSR_IA32_APICBASE, l, h);
+               }
        }
 
        maxlvt = lapic_get_maxlvt();