Merge branch 'next/cleanup2' of git://git.linaro.org/people/arnd/arm-soc

[pandora-kernel.git] / arch / arm / plat-omap / i2c.c

diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index c20beb8..679cbd4 100644 (file)
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -108,6 +108,22 @@ static inline int omap1_i2c_add_bus(int bus_id)
        res[1].start = INT_I2C;
        pdata = &i2c_pdata[bus_id - 1];
 
+       /* all OMAP1 have IP version 1 register set */
+       pdata->rev = OMAP_I2C_IP_VERSION_1;
+
+       /* all OMAP1 I2C are implemented like this */
+       pdata->flags = OMAP_I2C_FLAG_NO_FIFO |
+                      OMAP_I2C_FLAG_SIMPLE_CLOCK |
+                      OMAP_I2C_FLAG_16BIT_DATA_REG |
+                      OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK;
+
+       /* how the cpu bus is wired up differs for 7xx only */
+
+       if (cpu_is_omap7xx())
+               pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_1;
+       else
+               pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_2;
+
        return platform_device_register(pdev);
 }
 
@@ -130,6 +146,7 @@ static inline int omap2_i2c_add_bus(int bus_id)
        struct platform_device *pdev;
        char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN];
        struct omap_i2c_bus_platform_data *pdata;
+       struct omap_i2c_dev_attr *dev_attr;
 
        omap2_i2c_mux_pins(bus_id);
 
@@ -143,6 +160,16 @@ static inline int omap2_i2c_add_bus(int bus_id)
        }
 
        pdata = &i2c_pdata[bus_id - 1];
+       /*
+        * pass the hwmod class's CPU-specific knowledge of I2C IP revision in
+        * use, and functionality implementation flags, up to the OMAP I2C
+        * driver via platform data
+        */
+       pdata->rev = oh->class->rev;
+
+       dev_attr = (struct omap_i2c_dev_attr *)oh->dev_attr;
+       pdata->flags = dev_attr->flags;
+
        /*
         * When waiting for completion of a i2c transfer, we need to
         * set a wake up latency constraint for the MPU. This is to