ARM: OMAP: Add DMTIMER definitions for posted mode

[pandora-kernel.git] / arch / arm / mach-omap2 / timer.c

diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 037b0d7..56b8e11 100644 (file)
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -90,7 +90,7 @@ static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
 }
 
 static struct irqaction omap2_gp_timer_irq = {
-       .name           = "gp timer",
+       .name           = "gp_timer",
        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
        .handler        = omap2_gp_timer_interrupt,
 };
@@ -99,7 +99,7 @@ static int omap2_gp_timer_set_next_event(unsigned long cycles,
                                         struct clock_event_device *evt)
 {
        __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
-                                               0xffffffff - cycles, 1);
+                                  0xffffffff - cycles, OMAP_TIMER_POSTED);
 
        return 0;
 }
@@ -109,7 +109,7 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
 {
        u32 period;
 
-       __omap_dm_timer_stop(&clkev, 1, clkev.rate);
+       __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
 
        switch (mode) {
        case CLOCK_EVT_MODE_PERIODIC:
@@ -117,10 +117,10 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
                period -= 1;
                /* Looks like we need to first set the load value separately */
                __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
-                                       0xffffffff - period, 1);
+                                     0xffffffff - period, OMAP_TIMER_POSTED);
                __omap_dm_timer_load_start(&clkev,
                                        OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
-                                               0xffffffff - period, 1);
+                                       0xffffffff - period, OMAP_TIMER_POSTED);
                break;
        case CLOCK_EVT_MODE_ONESHOT:
                break;
@@ -132,7 +132,7 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
 }
 
 static struct clock_event_device clockevent_gpt = {
-       .name           = "gp timer",
+       .name           = "gp_timer",
        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
        .shift          = 32,
        .set_next_event = omap2_gp_timer_set_next_event,
@@ -169,13 +169,6 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
        if (IS_ERR(timer->fclk))
                return -ENODEV;
 
-       sprintf(name, "gpt%d_ick", gptimer_id);
-       timer->iclk = clk_get(NULL, name);
-       if (IS_ERR(timer->iclk)) {
-               clk_put(timer->fclk);
-               return -ENODEV;
-       }
-
        omap_hwmod_enable(oh);
 
        sys_timer_reserved |= (1 << (gptimer_id - 1));
@@ -254,37 +247,27 @@ static struct omap_dm_timer clksrc;
 /*
  * clocksource
  */
-static DEFINE_CLOCK_DATA(cd);
 static cycle_t clocksource_read_cycles(struct clocksource *cs)
 {
-       return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1);
+       return (cycle_t)__omap_dm_timer_read_counter(&clksrc,
+                                                    OMAP_TIMER_POSTED);
 }
 
 static struct clocksource clocksource_gpt = {
-       .name           = "gp timer",
+       .name           = "gp_timer",
        .rating         = 300,
        .read           = clocksource_read_cycles,
        .mask           = CLOCKSOURCE_MASK(32),
        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
-static void notrace dmtimer_update_sched_clock(void)
-{
-       u32 cyc;
-
-       cyc = __omap_dm_timer_read_counter(&clksrc, 1);
-
-       update_sched_clock(&cd, cyc, (u32)~0);
-}
-
-unsigned long long notrace sched_clock(void)
+static u32 notrace dmtimer_read_sched_clock(void)
 {
-       u32 cyc = 0;
-
        if (clksrc.reserved)
-               cyc = __omap_dm_timer_read_counter(&clksrc, 1);
+               return __omap_dm_timer_read_counter(&clksrc,
+                                                   OMAP_TIMER_POSTED);
 
-       return cyc_to_sched_clock(&cd, cyc, (u32)~0);
+       return 0;
 }
 
 /* Setup free-running counter for clocksource */
@@ -300,8 +283,9 @@ static void __init omap2_gp_clocksource_init(int gptimer_id,
                gptimer_id, clksrc.rate);
 
        __omap_dm_timer_load_start(&clksrc,
-                       OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
-       init_sched_clock(&cd, dmtimer_update_sched_clock, 32, clksrc.rate);
+                                  OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
+                                  OMAP_TIMER_POSTED);
+       setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
 
        if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
                pr_err("Could not register clocksource %s\n",